From patchwork Wed Apr 14 13:20:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12202787 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27144C433B4 for ; Wed, 14 Apr 2021 13:22:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2E5661132 for ; Wed, 14 Apr 2021 13:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231336AbhDNNXM (ORCPT ); Wed, 14 Apr 2021 09:23:12 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:34600 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351322AbhDNNXG (ORCPT ); Wed, 14 Apr 2021 09:23:06 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13EDG1va020128; Wed, 14 Apr 2021 06:21:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=1w1aOW3ghY/Ww+N67gF96mJvYXQ0kxUthm1XoYVB+Qs=; b=XU1tpVxJX/dIFConuEnm/ZXW/ygcd1ydOQTmb4p8/g5KzAg6KrawOQUDOOaBDix2voux pIGUobGsKWUvwQsQKeukeSRZXlRyziq/u5IeTODQUb80QJctTSlpEx7xTatvdgjYAjwv o3F8lFU/bvWqXtkNXa9PxIyKEw3Q5UeoDcBdXyBjYGBQLPRqCNchAH/wRFuEK86LgUW1 gm4FWA7AUjCGt8dxQXRF3cS6NkiiZnOlx9uHUHVJwDhLybG6p0rbpqLghVeLrhg7odcz 0183ry55ejbKsMW2iM5cXmbah3TJdlRZy5uLMAv8q86B4k0F0UhDlSKxXVHHJMJZAq5P 9w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37wqtm1svd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Apr 2021 06:21:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Apr 2021 06:21:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Apr 2021 06:21:06 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 22F443F7043; Wed, 14 Apr 2021 06:21:01 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Ben Peled , Marc St-Amand Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_v2_1/5=5D_PCI=3A_armada8k=3A_D?= =?utf-8?q?isable_LTSSM_on_link_down_interrupts?= Date: Wed, 14 Apr 2021 16:20:50 +0300 Message-ID: <1618406454-7953-2-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com> References: <1618406454-7953-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: WDbkL8ZwggSTTIPgQA8z11jWe6SvOfXT X-Proofpoint-GUID: WDbkL8ZwggSTTIPgQA8z11jWe6SvOfXT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-14_07:2021-04-14,2021-04-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled When a PCI link down condition is detected, the link training state machine must be disabled immediately. Signed-off-by: Marc St-Amand Signed-off-by: Konstantin Porotchkin Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 13901f3..b2278b1 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -54,6 +54,10 @@ struct armada8k_pcie { #define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_D_ASSERT_MASK BIT(12) +#define PCIE_GLOBAL_INT_CAUSE2_REG (PCIE_VENDOR_REGS_OFFSET + 0x24) +#define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) +#define PCIE_INT2_PHY_RST_LINK_DOWN BIT(1) + #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) @@ -193,6 +197,11 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + /* Also enable link down interrupts */ + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + reg |= PCIE_INT2_PHY_RST_LINK_DOWN; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, reg); + if (!dw_pcie_link_up(pci)) { /* Configuration done. Start LTSSM */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); @@ -230,6 +239,35 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG); + + if (PCIE_INT2_PHY_RST_LINK_DOWN & val) { + u32 ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + /* + * The link went down. Disable LTSSM immediately. This + * unlocks the root complex config registers. Downstream + * device accesses will return all-Fs + */ + ctrl_reg &= ~(PCIE_APP_LTSSM_EN); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, ctrl_reg); + /* + * Mask link down interrupts. They can be re-enabled once + * the link is retrained. + */ + ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + ctrl_reg &= ~PCIE_INT2_PHY_RST_LINK_DOWN; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, ctrl_reg); + /* + * At this point a worker thread can be triggered to + * initiate a link retrain. If link retrains were + * possible, that is. + */ + dev_dbg(pci->dev, "%s: link went down\n", __func__); + } + + /* Now clear the second interrupt cause. */ + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG, val); + return IRQ_HANDLED; } From patchwork Wed Apr 14 13:20:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12202767 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47632C43460 for ; Wed, 14 Apr 2021 13:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21DD561176 for ; Wed, 14 Apr 2021 13:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351274AbhDNNVr (ORCPT ); Wed, 14 Apr 2021 09:21:47 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:30160 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229450AbhDNNVp (ORCPT ); Wed, 14 Apr 2021 09:21:45 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13EDHAmw022142; Wed, 14 Apr 2021 06:21:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=+In1dmXSvzWoLOLoOW3zbdaENtcaeg4FVjkc6FVfWJA=; b=OXqF90UGPG8E7gxcYbeoM6TNol6yXu9S3BOE/hMDmUticZ2Au9EgbTOa9vf/BrtjXQ+d gZwZsUP3WgGFjydqBHfkaLdZG6HttazfrNBDI51BgCmuPS0N9DeqSLfJCXK0Ojmu7uSB g+sKjbMfCh7nDF/AZCPR9PqnnFK6yUBIx77xNvQpmkfH63wUWAYvmFi88sjBE7uJThNF mv8/vAe4C4wGYOdNSGnKGPAN3I/olzAZDtFe8dC/RJK1uHkoMTyu+DatCAXF0kpqSimU NLJstwyBVbt8hHpi1Cv3SDkVIJGBN8049HaoCibdhHQ8IEm/fXJAnbgiS4teiq8YS9xI 2w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37wqtm1svq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Apr 2021 06:21:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Apr 2021 06:21:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Apr 2021 06:21:10 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id A8CA73F703F; Wed, 14 Apr 2021 06:21:06 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Ben Peled Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_v2_2/5=5D_PCI=3A_armada8k=3A_A?= =?utf-8?q?dd_link-down_handle?= Date: Wed, 14 Apr 2021 16:20:51 +0300 Message-ID: <1618406454-7953-3-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com> References: <1618406454-7953-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: iVoA1STEdLXTtoQCgdBpdwNWT_rX2frW X-Proofpoint-GUID: iVoA1STEdLXTtoQCgdBpdwNWT_rX2frW X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-14_07:2021-04-14,2021-04-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled In PCIE ISR routine caused by RST_LINK_DOWN we schedule work to handle the link-down procedure. Link-down procedure will: 1. Remove PCIe bus 2. Reset the MAC 3. Reconfigure link back up 4. Rescan PCIe bus Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 69 ++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index b2278b1..34b253c 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include "pcie-designware.h" @@ -33,6 +35,9 @@ struct armada8k_pcie { struct clk *clk_reg; struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; unsigned int phy_count; + struct regmap *sysctrl_base; + u32 mac_rest_bitmask; + struct work_struct recover_link_work; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000 @@ -73,6 +78,8 @@ struct armada8k_pcie { #define AX_USER_DOMAIN_MASK 0x3 #define AX_USER_DOMAIN_SHIFT 4 +#define UNIT_SOFT_RESET_CONFIG_REG 0x268 + #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) @@ -225,6 +232,50 @@ static int armada8k_pcie_host_init(struct pcie_port *pp) return 0; } +static void armada8k_pcie_recover_link(struct work_struct *ws) +{ + struct armada8k_pcie *pcie = container_of(ws, struct armada8k_pcie, recover_link_work); + struct pcie_port *pp = &pcie->pci->pp; + struct pci_bus *bus = pp->bridge->bus; + struct pci_dev *root_port; + int ret; + + root_port = pci_get_slot(bus, 0); + if (!root_port) { + dev_err(pcie->pci->dev, "failed to get root port\n"); + return; + } + pci_lock_rescan_remove(); + pci_stop_and_remove_bus_device(root_port); + /* + * Sleep needed to make sure all pcie transactions and access + * are flushed before resetting the mac + */ + msleep(100); + + /* Reset mac */ + regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG, + pcie->mac_rest_bitmask, 0, NULL, false, true); + udelay(1); + regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG, + pcie->mac_rest_bitmask, pcie->mac_rest_bitmask, + NULL, false, true); + udelay(1); + ret = armada8k_pcie_host_init(pp); + if (ret) { + dev_err(pcie->pci->dev, "failed to initialize host: %d\n", ret); + pci_unlock_rescan_remove(); + pci_dev_put(root_port); + return; + } + + bus = NULL; + while ((bus = pci_find_next_bus(bus)) != NULL) + pci_rescan_bus(bus); + pci_unlock_rescan_remove(); + pci_dev_put(root_port); +} + static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) { struct armada8k_pcie *pcie = arg; @@ -262,6 +313,9 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) * initiate a link retrain. If link retrains were * possible, that is. */ + if (pcie->sysctrl_base && pcie->mac_rest_bitmask) + schedule_work(&pcie->recover_link_work); + dev_dbg(pci->dev, "%s: link went down\n", __func__); } @@ -330,6 +384,8 @@ static int armada8k_pcie_probe(struct platform_device *pdev) pcie->pci = pci; + INIT_WORK(&pcie->recover_link_work, armada8k_pcie_recover_link); + pcie->clk = devm_clk_get(dev, NULL); if (IS_ERR(pcie->clk)) return PTR_ERR(pcie->clk); @@ -357,6 +413,19 @@ static int armada8k_pcie_probe(struct platform_device *pdev) goto fail_clkreg; } + pcie->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,system-controller"); + if (IS_ERR(pcie->sysctrl_base)) { + dev_warn(dev, "failed to find marvell,system-controller\n"); + pcie->sysctrl_base = 0x0; + } + + ret = of_property_read_u32(pdev->dev.of_node, "marvell,mac-reset-bit-mask", + &pcie->mac_rest_bitmask); + if (ret < 0) { + dev_warn(dev, "couldn't find mac reset bit mask: %d\n", ret); + pcie->mac_rest_bitmask = 0x0; + } ret = armada8k_pcie_setup_phys(pcie); if (ret) goto fail_clkreg; From patchwork Wed Apr 14 13:20:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12202769 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E31EC43461 for ; Wed, 14 Apr 2021 13:21:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60731611F2 for ; Wed, 14 Apr 2021 13:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351284AbhDNNVv (ORCPT ); Wed, 14 Apr 2021 09:21:51 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:13864 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229450AbhDNNVu (ORCPT ); Wed, 14 Apr 2021 09:21:50 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13EDGEr1020572; Wed, 14 Apr 2021 06:21:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=GymurhClTLZ4ST/n6Oo2CGklmnbA31pLqRq8fnRk7Yg=; b=Tn6a73rZ0cIRXAe9X24yzdxGBoX+lfwLF1tdiHyglQAxRJe7enBJf584xawLP59u1Q4m sdSo0mtzhIEeVD9PlOs9vm1AzWKSJeIGWr9QvMGasb32Y79AavVpotF61/pqldsLFhPN L4octCOqcl8Q1npTXRlJc43vctBA5F5AQG8/Zo4Mj6Cu0TeBBpyzzqSuB8mbtHSZEh75 K53YVF8pIv/iTjX8geCmdAQtALUUwdk89nunVOxdt6GyZn1GR60uidgAlzMgBBJJXn8I Z+Ppvu45rCHJu5UGPfc+s1slbYuRqvRpfwa3x8yHEWhAdc2ppE7m6o0T+pfpavQ4rPYu nw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37wqtm1sw8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Apr 2021 06:21:17 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Apr 2021 06:21:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Apr 2021 06:21:15 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 0B3EE3F7040; Wed, 14 Apr 2021 06:21:10 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Ben Peled Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_v2_3/5=5D_dt-bindings=3A_pci?= =?utf-8?q?=3A_add_system_controller_and_MAC_reset_bit_to_Armada_7K/8K_contr?= =?utf-8?q?oller_bindings?= Date: Wed, 14 Apr 2021 16:20:52 +0300 Message-ID: <1618406454-7953-4-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com> References: <1618406454-7953-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mfDONwb7ygtDSHLNtSxgPUiQ5HJDAFUC X-Proofpoint-GUID: mfDONwb7ygtDSHLNtSxgPUiQ5HJDAFUC X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-14_07:2021-04-14,2021-04-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Adding optional system-controller and mac-reset-bit-mask needed for linkdown procedure. Signed-off-by: Ben Peled --- Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0..2696e79 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -24,6 +24,10 @@ Optional properties: - phy-names: names of the PHYs corresponding to the number of lanes. Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for 2 PHYs. +- marvell,system-controller: address of system controller needed + in order to reset MAC used by link-down handle +- marvell,mac-reset-bit-mask: MAC reset bit of system controller + needed in order to reset MAC used by link-down handle Example: @@ -45,4 +49,6 @@ Example: interrupts = ; num-lanes = <1>; clocks = <&cpm_syscon0 1 13>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; }; From patchwork Wed Apr 14 13:20:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12202771 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC93C433B4 for ; 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Wed, 14 Apr 2021 06:21:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Apr 2021 06:21:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Apr 2021 06:21:19 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 6AFC53F7045; Wed, 14 Apr 2021 06:21:15 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Ben Peled Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_v2_4/5=5D_arm64=3A_dts=3A_marv?= =?utf-8?q?ell=3A_add_pcie_mac_reset_to_pcie?= Date: Wed, 14 Apr 2021 16:20:53 +0300 Message-ID: <1618406454-7953-5-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com> References: <1618406454-7953-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: p7_gtBD-RNQNkH_SBfi2yiwINBSNHiIV X-Proofpoint-GUID: p7_gtBD-RNQNkH_SBfi2yiwINBSNHiIV X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-14_07:2021-04-14,2021-04-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Add system controller and reset bit to each pcie to enable pcie mac reset Signed-off-by: Ben Peled --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16b..eb60e73 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -11,6 +11,7 @@ #include "armada-common.dtsi" #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) +#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n) (0x1 << 11 + ((n + 2) % 3)) / { /* @@ -513,6 +514,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; @@ -538,6 +541,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; @@ -563,6 +568,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; }; From patchwork Wed Apr 14 13:20:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12202773 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB1B6C433B4 for ; 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Wed, 14 Apr 2021 06:21:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Apr 2021 06:21:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Apr 2021 06:21:23 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id C05B83F7040; Wed, 14 Apr 2021 06:21:19 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Ben Peled Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_v2_5/5=5D_PCI=3A_armada8k=3A_a?= =?utf-8?q?dd_device_reset_to_link-down_handle?= Date: Wed, 14 Apr 2021 16:20:54 +0300 Message-ID: <1618406454-7953-6-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com> References: <1618406454-7953-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: -cKwrM6rjjzn37Rup-lWxZXYcioIbeMp X-Proofpoint-GUID: -cKwrM6rjjzn37Rup-lWxZXYcioIbeMp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-14_07:2021-04-14,2021-04-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Added pcie reset via gpio support as described in the designware-pcie.txt DT binding document. In cases link down cause still exist in device. The device need to be reset to reestablish the link. If reset-gpio pin provided in the device tree, then the linkdown handle resets the device before reestablishing link. Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 24 ++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 34b253c..04bba97 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "pcie-designware.h" @@ -38,6 +39,8 @@ struct armada8k_pcie { struct regmap *sysctrl_base; u32 mac_rest_bitmask; struct work_struct recover_link_work; + enum of_gpio_flags flags; + struct gpio_desc *reset_gpio; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000 @@ -247,9 +250,18 @@ static void armada8k_pcie_recover_link(struct work_struct *ws) } pci_lock_rescan_remove(); pci_stop_and_remove_bus_device(root_port); + /* Reset device if reset gpio is set */ + if (pcie->reset_gpio) { + /* assert and then deassert the reset signal */ + gpiod_set_value_cansleep(pcie->reset_gpio, 0); + msleep(100); + gpiod_set_value_cansleep(pcie->reset_gpio, + (pcie->flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1); + } /* - * Sleep needed to make sure all pcie transactions and access - * are flushed before resetting the mac + * Sleep used for two reasons. + * First make sure all pcie transactions and access are flushed before resetting the mac + * and second to make sure pci device is ready in case we reset the device */ msleep(100); @@ -369,6 +381,7 @@ static int armada8k_pcie_probe(struct platform_device *pdev) struct armada8k_pcie *pcie; struct device *dev = &pdev->dev; struct resource *base; + int reset_gpio; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -413,6 +426,13 @@ static int armada8k_pcie_probe(struct platform_device *pdev) goto fail_clkreg; } + /* Config reset gpio for pcie if the reset connected to gpio */ + reset_gpio = of_get_named_gpio_flags(pdev->dev.of_node, + "reset-gpios", 0, + &pcie->flags); + if (gpio_is_valid(reset_gpio)) + pcie->reset_gpio = gpio_to_desc(reset_gpio); + pcie->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "marvell,system-controller"); if (IS_ERR(pcie->sysctrl_base)) {