From patchwork Wed Apr 14 19:18:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F3ECC433B4 for ; Wed, 14 Apr 2021 19:22:30 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9698A61132 for ; Wed, 14 Apr 2021 19:22:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9698A61132 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yFB7aknK3AInRWTR7gmsH2jUbaMYm/5q1dSMUC1RTLs=; b=RRFp/Qui/GNrZ5NePOK4pbhjW7 SToBYijwz48kZLMxpeOI4mcXuMkxWLQujW1dorMEjQCDM7QJ4mQo0C3Prw1Kqs/81nFDCwRJzJtOG CdLXqLuhah/VA4QEtC4NJYD4yhlzulXRvRLNUbp59rBo6IswCZwHZrIY8Pm516ijgIhzVave1SSpv L1SZ7EUsullXtbwKIWb4DBNa4pm8B1e9H3WcKzhwrZk934rG38jxI1udksXXxS1fwLTKkJ02mAwCT qLg4oIOgud8DIfRl//g8rysitOaj0nAYc082VAZ7XO9+WDuswRUWhEGqirRyhhRZ8eGkcB5IkO1XB DvOFF1MA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl3a-00DX96-3Q; Wed, 14 Apr 2021 19:20:17 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2e-00DX3l-Nv for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=fHAgKTuaD0fmCJZBNP9KzdSyhBzwhPEilWkB+vAAgho=; b=nMeO7vwR5Od08HcTUFh4iZyzIS 8y7IGYeoc8bB3VfXETBUf9vtM6TSk5kOVv/nTBzOmJGxPIV+RyXZoCwtLsnMth2rdtnGC15ixP+XH Jy+ocnxE3IHhLs+bTZ3o7OlG08pJeyjt7QZ295dO90g2Zrxm61p0wGi0UPp3FwjJVx2LJzsvB1VQu cD5M5oD+TCBOyiJHg75ft9ho0yF/7tddB6wJghNBiDkgl0FOdyaY2uv8xDzA3U+fsdpf/4VCQwVNu Z0YZVjmHPAgT32ga+M/O0sXNLAg6dLY0aUWlpSXBGoJ0Qv4zecTSw8rXoF8QMdnlu/P/xc/SIzLys U7jl+Kgg==; Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2b-0082pp-6b for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:11 +0000 Received: by mail-wr1-x42b.google.com with SMTP id k26so4508205wrc.8 for ; Wed, 14 Apr 2021 12:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fHAgKTuaD0fmCJZBNP9KzdSyhBzwhPEilWkB+vAAgho=; b=rwICsq4VYRnDsxHsWKXBDjI1XhXqLR0KiqCgmokQWMKWluSFQnJM/R6aMqdyMwhoyF QiyTpA9wjlPrc6OnG31qLItI2IOs2tURNYCgg/tk/CBtvRK9fyBTqSF1yQqXL5D/NgY9 vtSLkYSWjLA9VN2lCehxTHTfjV4lkU4Z3uTBGXDvdQhGL/JJO4QSVkHvPbGyohih6044 ZD/banvOh3oxL5y9JY68IKBobLVYV4CDbUh4Smt2OOTBBj279EM5GdaNdxRW0/atMVuu nkZ0VZUlYIBoveNmuscmr9u73JJScEObDJ60NYCTSq/IfLmsE0Pcc4wMMcNBqgGvtgke lmQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fHAgKTuaD0fmCJZBNP9KzdSyhBzwhPEilWkB+vAAgho=; b=lLzIXXwAFJEk3mP91eFtNSqyZTdc1/4wQG4hUmbMutlzI2gLx/TIL9JAfNFaIdxV8e oM0N60Vysd0RjjJfDgV7Lowx90sU/+stT+apEJQpJQ1rHzEfCDooTPAn1ZkODXievJ+f b9NakD2guOxoOnm8E4v2I9qejqpSvTg02B/+CQXYT/KcZleQ+BTz9EsabEGRCrNEc0WF J//quA4h+ZwFyTwdlbex9r8QQjm/fil4kCUMnPUt9lb/0rZaaOIP881QmgmN2Q3gH2+0 5z2ZJXZbUvvFVZCpWltuCtOhXQGUt+a48L3uO59JOPT8B1zk+Mpf8VATx2d5zNKz2RGf gYCg== X-Gm-Message-State: AOAM532GFXM2mOjZkSTURxPsgy4tOXKUDEa4vlP8+KjZm8rOmPJ1guHO pfW8TKsQtU0Lo2tLu0/gYXG/8VJn0NFRhw== X-Google-Smtp-Source: ABdhPJzTXFHiK6Dz4d/TtqZdlFPuBq3UmXVHpQftYR2TJje3RV7bBEtkKOOQVfmuk0C3+HJLnEdTRg== X-Received: by 2002:adf:f186:: with SMTP id h6mr26948603wro.89.1618427947314; Wed, 14 Apr 2021 12:19:07 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:06 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 01/10] coresight: syscfg: Initial coresight system configuration Date: Wed, 14 Apr 2021 20:18:54 +0100 Message-Id: <20210414191903.18349-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121909_273615_77A9294E X-CRM114-Status: GOOD ( 40.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Creates an system management API to allow complex configurations and features to be programmed into a CoreSight infrastructure. A feature is defined as a programming set for a device or class of devices. A configuration is a set of features across the system that are enabled for a trace session. The API will manage system wide configuration, and allow complex programmed features to be added to individual device instances, and provide for system wide configuration selection on trace capture operations. This patch creates the initial data object and the initial API for loading configurations and features. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-config.h | 142 +++++++++++++ drivers/hwtracing/coresight/coresight-core.c | 12 +- .../hwtracing/coresight/coresight-etm-perf.c | 2 +- .../hwtracing/coresight/coresight-etm-perf.h | 2 +- .../hwtracing/coresight/coresight-syscfg.c | 199 ++++++++++++++++++ .../hwtracing/coresight/coresight-syscfg.h | 46 ++++ 7 files changed, 401 insertions(+), 4 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index d60816509755..3d037f17aade 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -4,7 +4,7 @@ # obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ - coresight-sysfs.o + coresight-sysfs.o coresight-syscfg.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h new file mode 100644 index 000000000000..21aa7464dcdc --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Linaro Limited, All rights reserved. + * Author: Mike Leach + */ + +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H +#define _CORESIGHT_CORESIGHT_CONFIG_H + +#include +#include + +/* CoreSight Configuration Management - component and system wide configuration */ + +/* + * Register type flags for register value descriptor: + * describe how the value is interpreted, and handled. + */ +#define CS_CFG_REG_TYPE_STD 0x80 /* reg is standard reg */ +#define CS_CFG_REG_TYPE_RESOURCE 0x40 /* reg is a resource */ +#define CS_CFG_REG_TYPE_VAL_PARAM 0x08 /* reg value uses param */ +#define CS_CFG_REG_TYPE_VAL_MASK 0x04 /* reg value bit masked */ +#define CS_CFG_REG_TYPE_VAL_64BIT 0x02 /* reg value 64 bit */ +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01 /* reg value save on disable */ + +/* + * flags defining what device class a feature will match to when processing a + * system configuration - used by config data and devices. + */ +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ + +/* flags defining device instance matching - used in config match desc data. */ +#define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ + +/* + * Limit number of presets in a configuration + * This is related to the number of bits (4) we use to select the preset on + * the perf command line. Preset 0 is always none selected. + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c + */ +#define CS_CFG_CONFIG_PRESET_MAX 15 + +/** + * Parameter descriptor for a device feature. + * + * @name: Name of parameter. + * @value: Initial or default value. + */ +struct cscfg_parameter_desc { + const char *name; + u64 value; +}; + +/** + * Representation of register value and a descriptor of register usage. + * + * Used as a descriptor in the feature descriptors. + * Used as a value in when in a feature loading into a csdev. + * + * Supports full 64 bit register value, or 32 bit value with optional mask + * value. + * + * @type: define register usage and interpretation. + * @offset: the address offset for register in the hardware device (per device specification). + * @hw_info: optional hardware device type specific information. (ETM / CTI specific etc) + * @val64: 64 bit value. + * @val32: 32 bit value. + * @mask32: 32 bit mask when using 32 bit value to access device register - if mask type. + * @param_idx: parameter index value into parameter array if param type. + */ +struct cscfg_regval_desc { + struct { + u32 type:8; + u32 offset:12; + u32 hw_info:12; + }; + union { + u64 val64; + struct { + u32 val32; + u32 mask32; + }; + u32 param_idx; + }; +}; + +/** + * Device feature descriptor - combination of registers and parameters to + * program a device to implement a specific complex function. + * + * @name: feature name. + * @description: brief description of the feature. + * @item: List entry. + * @match_flags: matching information if loading into a device + * @nr_params: number of parameters used. + * @params_desc: array of parameters used. + * @nr_regs: number of registers used. + * @regs_desc: array of registers used. + */ +struct cscfg_feature_desc { + const char *name; + const char *description; + struct list_head item; + u32 match_flags; + int nr_params; + struct cscfg_parameter_desc *params_desc; + int nr_regs; + struct cscfg_regval_desc *regs_desc; +}; + +/** + * Configuration descriptor - describes selectable system configuration. + * + * A configuration describes device features in use, and may provide preset + * values for the parameters in those features. + * + * A single set of presets is the sum of the parameters declared by + * all the features in use - this value is @nr_total_params. + * + * @name: name of the configuration - used for selection. + * @description: description of the purpose of the configuration. + * @item: list entry. + * @nr_feat_refs: Number of features used in this configuration. + * @feat_ref_names: references to features used in this configuration. + * @nr_presets: Number of sets of presets supplied by this configuration. + * @nr_total_params: Sum of all parameters declared by used features + * @presets: Array of preset values. + * + */ +struct cscfg_config_desc { + const char *name; + const char *description; + struct list_head item; + int nr_feat_refs; + const char **feat_ref_names; + int nr_presets; + int nr_total_params; + const u64 *presets; /* nr_presets * nr_total_params */ +}; + +#endif /* _CORESIGHT_CORESIGHT_CONFIG_H */ diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ca75b0b54e1f..868785983c79 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -21,6 +21,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" +#include "coresight-syscfg.h" static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -1764,13 +1765,22 @@ static int __init coresight_init(void) ret = etm_perf_init(); if (ret) - bus_unregister(&coresight_bustype); + goto exit_bus_unregister; + /* initialise the coresight syscfg API */ + ret = cscfg_init(); + if (!ret) + return 0; + + etm_perf_exit(); +exit_bus_unregister: + bus_unregister(&coresight_bustype); return ret; } static void __exit coresight_exit(void) { + cscfg_exit(); etm_perf_exit(); bus_unregister(&coresight_bustype); } diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index f123c26b9f54..15310c72f89f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -748,7 +748,7 @@ int __init etm_perf_init(void) return ret; } -void __exit etm_perf_exit(void) +void etm_perf_exit(void) { perf_pmu_unregister(&etm_pmu); } diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 3e4f2ad5e193..29d90dfeba31 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -83,6 +83,6 @@ static inline void *etm_perf_sink_config(struct perf_output_handle *handle) #endif /* CONFIG_CORESIGHT */ int __init etm_perf_init(void); -void __exit etm_perf_exit(void); +void etm_perf_exit(void); #endif diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c new file mode 100644 index 000000000000..417db3f92c2f --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Linaro Limited, All rights reserved. + * Author: Mike Leach + */ + +#include + +#include "coresight-config.h" +#include "coresight-syscfg.h" + +/* + * cscfg_ API manages configurations and features for the entire coresight + * infrastructure. + * + * It allows the loading of configurations and features, and loads these into + * coresight devices as appropriate. + */ + +/* protect the cscsg_data and device */ +static DEFINE_MUTEX(cscfg_mutex); + +/* only one of these */ +static struct cscfg_manager *cscfg_mgr; + +/* load features and configuations into the lists */ + +/* check feature list for a named feature - call with mutex locked. */ +static bool cscfg_match_list_feat(const char *name) +{ + struct cscfg_feature_desc *feat_desc; + + list_for_each_entry(feat_desc, &cscfg_mgr->feat_desc_list, item) { + if (strcmp(feat_desc->name, name) == 0) + return true; + } + return false; +} + +/* check all feat needed for cfg are in the list - call with mutex locked. */ +static int cscfg_check_feat_for_cfg(struct cscfg_config_desc *config_desc) +{ + int i; + + for (i = 0; i < config_desc->nr_feat_refs; i++) + if (!cscfg_match_list_feat(config_desc->feat_ref_names[i])) + return -EINVAL; + return 0; +} + +/* + * load feature - add to feature list. + */ +static int cscfg_load_feat(struct cscfg_feature_desc *feat_desc) +{ + list_add(&feat_desc->item, &cscfg_mgr->feat_desc_list); + + return 0; +} + +/* + * load config into the system - validate used features exist then add to + * config list. + */ +static int cscfg_load_config(struct cscfg_config_desc *config_desc) +{ + int err; + + /* validate features are present */ + err = cscfg_check_feat_for_cfg(config_desc); + if (err) + return err; + + list_add(&config_desc->item, &cscfg_mgr->config_desc_list); + return 0; +} + +/** + * cscfg_load_config_sets - API function to load feature and config sets. + * + * Take a 0 terminated array of feature descriptors and/or configuration + * descriptors and load into the system. + * Features are loaded first to ensure configuration dependencies can be met. + * + * @config_descs: 0 terminated array of configuration descriptors. + * @feat_descs: 0 terminated array of feature descriptors. + */ +int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, + struct cscfg_feature_desc **feat_descs) +{ + int err, i = 0; + + mutex_lock(&cscfg_mutex); + + /* load features first */ + if (feat_descs) { + while (feat_descs[i]) { + err = cscfg_load_feat(feat_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load feature %s\n", + feat_descs[i]->name); + goto exit_unlock; + } + i++; + } + } + + /* next any configurations to check feature dependencies */ + i = 0; + if (config_descs) { + while (config_descs[i]) { + err = cscfg_load_config(config_descs[i]); + if (err) { + pr_err("coresight-syscfg: Failed to load configuration %s\n", + config_descs[i]->name); + goto exit_unlock; + } + i++; + } + } + +exit_unlock: + mutex_unlock(&cscfg_mutex); + return err; +} +EXPORT_SYMBOL_GPL(cscfg_load_config_sets); + +/* Initialise system configuration management device. */ + +struct device *cscfg_device(void) +{ + return cscfg_mgr ? &cscfg_mgr->dev : NULL; +} + +/* Must have a release function or the kernel will complain on module unload */ +static void cscfg_dev_release(struct device *dev) +{ + kfree(cscfg_mgr); + cscfg_mgr = NULL; +} + +/* a device is needed to "own" some kernel elements such as sysfs entries. */ +static int cscfg_create_device(void) +{ + struct device *dev; + int err = -ENOMEM; + + mutex_lock(&cscfg_mutex); + if (cscfg_mgr) { + err = -EINVAL; + goto create_dev_exit_unlock; + } + + cscfg_mgr = kzalloc(sizeof(struct cscfg_manager), GFP_KERNEL); + if (!cscfg_mgr) + goto create_dev_exit_unlock; + + /* setup the device */ + dev = cscfg_device(); + dev->release = cscfg_dev_release; + dev->init_name = "cs_system_cfg"; + + err = device_register(dev); + if (err) + cscfg_dev_release(dev); + +create_dev_exit_unlock: + mutex_unlock(&cscfg_mutex); + return err; +} + +static void cscfg_clear_device(void) +{ + mutex_lock(&cscfg_mutex); + device_unregister(cscfg_device()); + mutex_unlock(&cscfg_mutex); +} + +/* Initialise system config management API device */ +int __init cscfg_init(void) +{ + int err = 0; + + err = cscfg_create_device(); + if (err) + return err; + + INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); + INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); + + dev_info(cscfg_device(), "CoreSight Configuration manager initialised"); + return 0; +} + +void cscfg_exit(void) +{ + cscfg_clear_device(); +} diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h new file mode 100644 index 000000000000..18be9b58cd0b --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Coresight system configuration driver. + */ + +#ifndef CORESIGHT_SYSCFG_H +#define CORESIGHT_SYSCFG_H + +#include +#include + +#include "coresight-config.h" + +/** + * System configuration manager device. + * + * Contains lists of the loaded configurations and features, plus a list of CoreSight devices + * registered with the system as supporting configuration management. + * + * Need a device to 'own' some coresight system wide sysfs entries in + * perf events, configfs etc. + * + * @dev: The device. + * @csdev_desc_list: List of coresight devices registered with the configuration manager. + * @feat_desc_list: List of feature descriptors to load into registered devices. + * @config_desc_list: List of system configuration descriptors to load into registered devices. + */ +struct cscfg_manager { + struct device dev; + struct list_head csdev_desc_list; + struct list_head feat_desc_list; + struct list_head config_desc_list; +}; + +/* get reference to dev in cscfg_manager */ +struct device *cscfg_device(void); + +/* internal core operations for cscfg */ +int __init cscfg_init(void); +void cscfg_exit(void); + +/* syscfg manager external API */ +int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs, + struct cscfg_feature_desc **feat_descs); + +#endif /* CORESIGHT_SYSCFG_H */ From patchwork Wed Apr 14 19:18:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0253FC433ED for ; Wed, 14 Apr 2021 19:22:57 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6206E6113B for ; Wed, 14 Apr 2021 19:22:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6206E6113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WRzaouqBZEX0lJ0HiagDHYwlUU0tL8fb7tRhJVlRzKE=; b=cgbf3rWaFoLH7845wJ1t6bK9Gw RWwiJtmjjUF+D+Utj2/1m84JXHD+uUHpL/ynfdc6YHwI3Kegom5OUa/eemVH9aLNyJvkjRBcPy2J8 VpnvC8kRW31zgwYoQd4XGRUugANbX1lajbi3CL2y5ntr8jdbvD6AC5JK3kADH58RAKpQbgYgfsmyZ imxEo12opY2h/zIldyuO3PFBkoNojxG3g6ZH0e7anse8qWLLCuGahmuIXfKOUuLIAvgKRrcPVSige tu9uuxk9WK/nkIe+ZlLB5BXkRi2lcHBpdwCEzO7VVqa9jnwpWIV0gPya9CWCm0xIvAPKp3krApgOb Mr8zhHHA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl4L-00DXFd-5x; Wed, 14 Apr 2021 19:20:57 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2f-00DX3p-PF for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=xZEy6otIn9QzW4wjt3/PP1uMPlfagWclfQgHLjZeOsE=; b=KQW98u9NYhilwjhh16K2ng/Dkg iSHSy1EJfZaDDsGcxFkxREgz7hvY9hgvERzY9NFzVhxJAm/xEn29fYLCKSoyURIncMIhHXWkVEYCm UKl/Ws07jMbuTZ9pNk+IuA4ZYRneUDNopxsymcjMs5Loq4pNLXT8Kfv4qZzxB5JCY/1ESXrAcg7Rv mcYkOSETg1m9GeC/jiy8eRWB6Cf0HU3ClakU26Vbrh3DymdgrKcZPlFfA/SlvzUVIdiTOjrslTWDi 7ODaAgvtpljGQw5xIDIKuqXaLwrIhAEQ82BGKTGOW2KRfPXBLom2hm3E3QqsHXei03Q0QmiU9/Uiq FVv/Zl2A==; Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2b-0082q5-Dk for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:12 +0000 Received: by mail-wr1-x42b.google.com with SMTP id h4so11893729wrt.12 for ; Wed, 14 Apr 2021 12:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xZEy6otIn9QzW4wjt3/PP1uMPlfagWclfQgHLjZeOsE=; b=zseXscq36EwF4lXBD3dfHANJQE25PhNWjeStydoT1OWZyzVJva7uEFh8W06oIiOl9o mlM0Q8Z8Gd0WmT6BkuGmvyb/D5yIbxUYnX55ODESmyog7SuGLL3uoJeIbajxblc5IpiY SCCp19We+AO582HrpBNXgbmznwv5+20+hq01M6tVqjc4B26X3j84LP6IWKa0Jgzqze4K 8AlEdlt1xkZ+yQpYwmYaK8OTPftZXzm56JZk+x2eHeFMS6tKWS0iJjaW8nMzfi3xnfwD 2DI2O8e5Yl1dg07M2hBRIUXNfogTxso0PhDAK3gKwe97sCOj0jOsewQfeBFevzXENVXd YOvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xZEy6otIn9QzW4wjt3/PP1uMPlfagWclfQgHLjZeOsE=; b=MPd4dw8KOqMsX7OAQcOcOOlToZgkt00gEEHQ239m+s3Sqx07yTYOrEb9HPmoP9hmM6 l1JI/zNjXZeyPV1dg3pYMdSPlu3XwkOMpY2KQxC03HfLuaWUtvDf7ZgO1AT+0kx6V0bg JPa1vo4lEhqMvjrNQK/5vnF22Q+fkWUNHJvSVLIKTcliWA9qglvxRhtbIA98wvC4vyIq kbe+zxNYRzaNt0Y7tkQ9IvbOmDcfPaLTiZIjuIujRecMscdIs3kA38kwLNEEgHKOcFmZ MOGFHyTRdHtgB8It61pEsj5kzXuDzGpJk70l6zp5iSC44Y4Soei+ZKAcfcesZS/4Hrwp +3HQ== X-Gm-Message-State: AOAM533by5YCv7MrslMIXeLqtpUj/5bRVsCnLHr9J3BZh8WxTUdZN7/6 wZsoxKZgInHd8enyRcLzbP2/F0OZWc+iuw== X-Google-Smtp-Source: ABdhPJwFrTmTKm5tqYHV4ETv0PEfiobSTMNAkCG7YDl9bw5qQAznpzszPecTd3Qm19pAHaMz5brPQA== X-Received: by 2002:adf:dfc2:: with SMTP id q2mr7831624wrn.128.1618427948150; Wed, 14 Apr 2021 12:19:08 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:07 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 02/10] coresight: syscfg: Add registration and feature loading for cs devices Date: Wed, 14 Apr 2021 20:18:55 +0100 Message-Id: <20210414191903.18349-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121909_617417_B97EE9E6 X-CRM114-Status: GOOD ( 38.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org API for individual devices to register with the syscfg management system is added. Devices register with matching information, and any features or configurations that match will be loaded into the device. The feature and configuration loading is extended so that on load these are loaded into any currently registered devices. This allows configuration loading after devices have been registered. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-config.h | 98 +++++ .../hwtracing/coresight/coresight-syscfg.c | 338 +++++++++++++++++- .../hwtracing/coresight/coresight-syscfg.h | 19 + include/linux/coresight.h | 5 + 4 files changed, 459 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 21aa7464dcdc..685fb46ce893 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -139,4 +139,102 @@ struct cscfg_config_desc { const u64 *presets; /* nr_presets * nr_total_params */ }; +/** + * config register instance - part of a loaded feature. + * maps register values to csdev driver structures + * + * @reg_desc: value to use when setting feature on device / store for + * readback of volatile values. + * @driver_regval: pointer to internal driver element used to set the value + * in hardware. + */ +struct cscfg_regval_csdev { + struct cscfg_regval_desc reg_desc; + void *driver_regval; +}; + +/** + * config parameter instance - part of a loaded feature. + * + * @feat_csdev: parent feature + * @reg_csdev: register value updated by this parameter. + * @current_value: current value of parameter - may be set by user via + * sysfs, or modified during device operation. + * @val64: true if 64 bit value + */ +struct cscfg_parameter_csdev { + struct cscfg_feature_csdev *feat_csdev; + struct cscfg_regval_csdev *reg_csdev; + u64 current_value; + bool val64; +}; + +/** + * Feature instance loaded into a CoreSight device. + * + * When a feature is loaded into a specific device, then this structure holds + * the connections between the register / parameter values used and the + * internal data structures that are written when the feature is enabled. + * + * Since applying a feature modifies internal data structures in the device, + * then we have a reference to the device spinlock to protect access to these + * structures (@drv_spinlock). + * + * @feat_desc: pointer to the static descriptor for this feature. + * @csdev: parent CoreSight device instance. + * @node: list entry into feature list for this device. + * @drv_spinlock: device spinlock for access to driver register data. + * @nr_params: number of parameters. + * @params_csdev: current parameter values on this device + * @nr_regs: number of registers to be programmed. + * @regs_csdev: Programming details for the registers + */ +struct cscfg_feature_csdev { + const struct cscfg_feature_desc *feat_desc; + struct coresight_device *csdev; + struct list_head node; + spinlock_t *drv_spinlock; + int nr_params; + struct cscfg_parameter_csdev *params_csdev; + int nr_regs; + struct cscfg_regval_csdev *regs_csdev; +}; + +/** + * Configuration instance when loaded into a CoreSight device. + * + * The instance contains references to loaded features on this device that are + * used by the configuration. + * + * @config_desc:reference to the descriptor for this configuration + * @csdev: parent coresight device for this configuration instance. + * @enabled: true if configuration is enabled on this device. + * @node: list entry within the coresight device + * @nr_feat: Number of features on this device that are used in the + * configuration. + * @feats_csdev:references to the device features to enable. + */ +struct cscfg_config_csdev { + const struct cscfg_config_desc *config_desc; + struct coresight_device *csdev; + bool enabled; + struct list_head node; + int nr_feat; + struct cscfg_feature_csdev *feats_csdev[0]; +}; + +/** + * Coresight device operations. + * + * Registered coresight devices provide these operations to manage feature + * instances compatible with the device hardware and drivers + * + * @load_feat: Pass a feature descriptor into the device and create the + * loaded feature instance (struct cscfg_feature_csdev). + */ +struct cscfg_csdev_feat_ops { + int (*load_feat)(struct coresight_device *csdev, + struct cscfg_feature_csdev *feat_csdev); +}; + #endif /* _CORESIGHT_CORESIGHT_CONFIG_H */ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 417db3f92c2f..e93e62c1efbb 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -25,6 +25,199 @@ static struct cscfg_manager *cscfg_mgr; /* load features and configuations into the lists */ +/* protect the cfg lists in the csdev instances */ +static DEFINE_MUTEX(cscfg_csdev_mutex); + +/* get name feature instance from a coresight device list of features */ +static struct cscfg_feature_csdev * +cscfg_get_feat_csdev(struct coresight_device *csdev, const char *name) +{ + struct cscfg_feature_csdev *feat_csdev = NULL; + + list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node) { + if (strcmp(feat_csdev->feat_desc->name, name) == 0) + return feat_csdev; + } + return NULL; +} + +/* allocate the device config instance - with max number of used features */ +static struct cscfg_config_csdev * +cscfg_alloc_csdev_cfg(struct coresight_device *csdev, int nr_feats) +{ + struct cscfg_config_csdev *config_csdev = NULL; + struct device *dev = csdev->dev.parent; + + /* this is being allocated using the devm for the coresight device */ + config_csdev = devm_kzalloc(dev, + offsetof(struct cscfg_config_csdev, feats_csdev[nr_feats]), + GFP_KERNEL); + if (!config_csdev) + return NULL; + + config_csdev->csdev = csdev; + return config_csdev; +} + +/* Load a config into a device if there are any feature matches between config and device */ +static int cscfg_add_csdev_cfg(struct coresight_device *csdev, + struct cscfg_config_desc *config_desc) +{ + struct cscfg_config_csdev *config_csdev = NULL; + struct cscfg_feature_csdev *feat_csdev; + int i; + + /* look at each required feature and see if it matches any feature on the device */ + for (i = 0; i < config_desc->nr_feat_refs; i++) { + /* look for a matching name */ + feat_csdev = cscfg_get_feat_csdev(csdev, config_desc->feat_ref_names[i]); + if (feat_csdev) { + /* + * At least one feature on this device matches the config + * add a config instance to the device and a reference to the feature. + */ + if (!config_csdev) { + config_csdev = cscfg_alloc_csdev_cfg(csdev, + config_desc->nr_feat_refs); + if (!config_csdev) + return -ENOMEM; + config_csdev->config_desc = config_desc; + } + config_csdev->feats_csdev[config_csdev->nr_feat++] = feat_csdev; + } + } + /* if matched features, add config to device.*/ + if (config_csdev) { + mutex_lock(&cscfg_csdev_mutex); + list_add(&config_csdev->node, &csdev->config_csdev_list); + mutex_unlock(&cscfg_csdev_mutex); + } + + return 0; +} + +/* + * Add the config to the set of registered devices - call with mutex locked. + * Iterates through devices - any device that matches one or more of the + * configuration features will load it, the others will ignore it. + */ +static int cscfg_add_cfg_to_csdevs(struct cscfg_config_desc *config_desc) +{ + struct cscfg_registered_csdev *csdev_item; + int err; + + list_for_each_entry(csdev_item, &cscfg_mgr->csdev_desc_list, item) { + err = cscfg_add_csdev_cfg(csdev_item->csdev, config_desc); + if (err) + return err; + } + return 0; +} + +/* + * Allocate a feature object for load into a csdev. + * memory allocated using the csdev->dev object using devm managed allocator. + */ +static struct cscfg_feature_csdev * +cscfg_alloc_csdev_feat(struct coresight_device *csdev, struct cscfg_feature_desc *feat_desc) +{ + struct cscfg_feature_csdev *feat_csdev = NULL; + struct device *dev = csdev->dev.parent; + int i; + + feat_csdev = devm_kzalloc(dev, sizeof(struct cscfg_feature_csdev), GFP_KERNEL); + if (!feat_csdev) + return NULL; + + /* parameters are optional - could be 0 */ + feat_csdev->nr_params = feat_desc->nr_params; + + /* + * if we need parameters, zero alloc the space here, the load routine in + * the csdev device driver will fill out some information according to + * feature descriptor. + */ + if (feat_csdev->nr_params) { + feat_csdev->params_csdev = devm_kcalloc(dev, feat_csdev->nr_params, + sizeof(struct cscfg_parameter_csdev), + GFP_KERNEL); + if (!feat_csdev->params_csdev) + return NULL; + + /* + * fill in the feature reference in the param - other fields + * handled by loader in csdev. + */ + for (i = 0; i < feat_csdev->nr_params; i++) + feat_csdev->params_csdev[i].feat_csdev = feat_csdev; + } + + /* + * Always have registers to program - again the load routine in csdev device + * will fill out according to feature descriptor and device requirements. + */ + feat_csdev->nr_regs = feat_desc->nr_regs; + feat_csdev->regs_csdev = devm_kcalloc(dev, feat_csdev->nr_regs, + sizeof(struct cscfg_regval_csdev), + GFP_KERNEL); + if (!feat_csdev->regs_csdev) + return NULL; + + /* load the feature default values */ + feat_csdev->feat_desc = feat_desc; + feat_csdev->csdev = csdev; + + return feat_csdev; +} + +/* load one feature into one coresight device */ +static int cscfg_load_feat_csdev(struct coresight_device *csdev, + struct cscfg_feature_desc *feat_desc, + struct cscfg_csdev_feat_ops *ops) +{ + struct cscfg_feature_csdev *feat_csdev; + int err; + + if (!ops->load_feat) + return -EINVAL; + + feat_csdev = cscfg_alloc_csdev_feat(csdev, feat_desc); + if (!feat_csdev) + return -ENOMEM; + + /* load the feature into the device */ + err = ops->load_feat(csdev, feat_csdev); + if (err) + return err; + + /* add to internal csdev feature list */ + mutex_lock(&cscfg_csdev_mutex); + list_add(&feat_csdev->node, &csdev->feature_csdev_list); + mutex_unlock(&cscfg_csdev_mutex); + + return 0; +} + +/* + * Add feature to any matching devices - call with mutex locked. + * Iterates through devices - any device that matches the feature will be + * called to load it. + */ +static int cscfg_add_feat_to_csdevs(struct cscfg_feature_desc *feat_desc) +{ + struct cscfg_registered_csdev *csdev_item; + int err; + + list_for_each_entry(csdev_item, &cscfg_mgr->csdev_desc_list, item) { + if (csdev_item->match_flags & feat_desc->match_flags) { + err = cscfg_load_feat_csdev(csdev_item->csdev, feat_desc, &csdev_item->ops); + if (err) + return err; + } + } + return 0; +} + /* check feature list for a named feature - call with mutex locked. */ static bool cscfg_match_list_feat(const char *name) { @@ -53,8 +246,14 @@ static int cscfg_check_feat_for_cfg(struct cscfg_config_desc *config_desc) */ static int cscfg_load_feat(struct cscfg_feature_desc *feat_desc) { - list_add(&feat_desc->item, &cscfg_mgr->feat_desc_list); + int err; + /* add feature to any matching registered devices */ + err = cscfg_add_feat_to_csdevs(feat_desc); + if (err) + return err; + + list_add(&feat_desc->item, &cscfg_mgr->feat_desc_list); return 0; } @@ -71,6 +270,11 @@ static int cscfg_load_config(struct cscfg_config_desc *config_desc) if (err) return err; + /* add config to any matching registered device */ + err = cscfg_add_cfg_to_csdevs(config_desc); + if (err) + return err; + list_add(&config_desc->item, &cscfg_mgr->config_desc_list); return 0; } @@ -125,6 +329,138 @@ int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, } EXPORT_SYMBOL_GPL(cscfg_load_config_sets); +/* Handle coresight device registration and add configs and features to devices */ + +/* iterate through config lists and load matching configs to device */ +static int cscfg_add_cfgs_csdev(struct coresight_device *csdev) +{ + struct cscfg_config_desc *config_desc; + int err = 0; + + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { + err = cscfg_add_csdev_cfg(csdev, config_desc); + if (err) + break; + } + return err; +} + +/* iterate through feature lists and load matching features to device */ +static int cscfg_add_feats_csdev(struct coresight_device *csdev, + u32 match_flags, + struct cscfg_csdev_feat_ops *ops) +{ + struct cscfg_feature_desc *feat_desc; + int err = 0; + + if (!ops->load_feat) + return -EINVAL; + + list_for_each_entry(feat_desc, &cscfg_mgr->feat_desc_list, item) { + if (feat_desc->match_flags & match_flags) { + err = cscfg_load_feat_csdev(csdev, feat_desc, ops); + if (err) + break; + } + } + return err; +} + +/* Add coresight device to list and copy its matching info */ +static int cscfg_list_add_csdev(struct coresight_device *csdev, + u32 match_flags, + struct cscfg_csdev_feat_ops *ops) +{ + struct cscfg_registered_csdev *csdev_item; + + /* allocate the list entry structure */ + csdev_item = kzalloc(sizeof(struct cscfg_registered_csdev), GFP_KERNEL); + if (!csdev_item) + return -ENOMEM; + + csdev_item->csdev = csdev; + csdev_item->match_flags = match_flags; + csdev_item->ops.load_feat = ops->load_feat; + list_add(&csdev_item->item, &cscfg_mgr->csdev_desc_list); + + INIT_LIST_HEAD(&csdev->feature_csdev_list); + INIT_LIST_HEAD(&csdev->config_csdev_list); + + return 0; +} + +/* remove a coresight device from the list and free data */ +static void cscfg_list_remove_csdev(struct coresight_device *csdev) +{ + struct cscfg_registered_csdev *csdev_item, *tmp; + + list_for_each_entry_safe(csdev_item, tmp, &cscfg_mgr->csdev_desc_list, item) { + if (csdev_item->csdev == csdev) { + list_del(&csdev_item->item); + kfree(csdev_item); + break; + } + } +} + +/** + * cscfg_register_csdev - register a coresight device with the syscfg manager. + * + * Registers the coresight device with the system. @match_flags used to check + * if the device is a match for registered features. Any currently registered + * configurations and features that match the device will be loaded onto it. + * + * @csdev: The coresight device to register. + * @match_flags: Matching information to load features. + * @ops: Standard operations supported by the device. + */ +int cscfg_register_csdev(struct coresight_device *csdev, + u32 match_flags, + struct cscfg_csdev_feat_ops *ops) +{ + int ret = 0; + + mutex_lock(&cscfg_mutex); + + /* add device to list of registered devices */ + ret = cscfg_list_add_csdev(csdev, match_flags, ops); + if (ret) + goto reg_csdev_unlock; + + /* now load any registered features and configs matching the device. */ + ret = cscfg_add_feats_csdev(csdev, match_flags, ops); + if (ret) { + cscfg_list_remove_csdev(csdev); + goto reg_csdev_unlock; + } + + ret = cscfg_add_cfgs_csdev(csdev); + if (ret) { + cscfg_list_remove_csdev(csdev); + goto reg_csdev_unlock; + } + + pr_info("CSCFG registered %s", dev_name(&csdev->dev)); + +reg_csdev_unlock: + mutex_unlock(&cscfg_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(cscfg_register_csdev); + +/** + * cscfg_unregister_csdev - remove coresight device from syscfg manager. + * + * @csdev: Device to remove. + */ +void cscfg_unregister_csdev(struct coresight_device *csdev) +{ + mutex_lock(&cscfg_mutex); + cscfg_list_remove_csdev(csdev); + mutex_unlock(&cscfg_mutex); +} +EXPORT_SYMBOL_GPL(cscfg_unregister_csdev); + /* Initialise system configuration management device. */ struct device *cscfg_device(void) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index 18be9b58cd0b..5bcae3b374c6 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -35,6 +35,22 @@ struct cscfg_manager { /* get reference to dev in cscfg_manager */ struct device *cscfg_device(void); +/** + * List entry for Coresight devices that are registered as supporting complex + * config operations. + * + * @csdev: The registered device. + * @match_flags: The matching type information for adding features. + * @ops: Operations supported by the registered device. + * @item: list entry. + */ +struct cscfg_registered_csdev { + struct coresight_device *csdev; + u32 match_flags; + struct cscfg_csdev_feat_ops ops; + struct list_head item; +}; + /* internal core operations for cscfg */ int __init cscfg_init(void); void cscfg_exit(void); @@ -42,5 +58,8 @@ void cscfg_exit(void); /* syscfg manager external API */ int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs, struct cscfg_feature_desc **feat_descs); +int cscfg_register_csdev(struct coresight_device *csdev, u32 match_flags, + struct cscfg_csdev_feat_ops *ops); +void cscfg_unregister_csdev(struct coresight_device *csdev); #endif /* CORESIGHT_SYSCFG_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 85008a65e21f..6fb516e1b22e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -220,6 +220,8 @@ struct coresight_sysfs_link { * @nr_links: number of sysfs links created to other components from this * device. These will appear in the "connections" group. * @has_conns_grp: Have added a "connections" group for sysfs links. + * @feature_csdev_list: List of complex feature programming added to the device. + * @config_csdev_list: List of system configurations added to the device. */ struct coresight_device { struct coresight_platform_data *pdata; @@ -241,6 +243,9 @@ struct coresight_device { int nr_links; bool has_conns_grp; bool ect_enabled; /* true only if associated ect device is enabled */ + /* system configuration and feature lists */ + struct list_head feature_csdev_list; + struct list_head config_csdev_list; }; /* From patchwork Wed Apr 14 19:18:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F738C433B4 for ; Wed, 14 Apr 2021 19:22:36 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F1A3861168 for ; Wed, 14 Apr 2021 19:22:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F1A3861168 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=rINXhduhQ7hBK8Y3GlxONcNIbPaRzYNQsyZdK+TX2T0=; b=gZEuk0vjKCyWRr6H4vai+830D6 YZUhMmR5m80qKaLHtQ8oEMyRYhfOtygOtyBgoem6n5BblTPweNiix8uiV3p6sF1uwxyxKUN/BbYy+ N1xsMTs6RVrMLHmSbegpsq8asgKq5095k8maZKHr/eQriN/KUTzfNKp3flIzQhu783+g/AEeKhjvG tSq7ZFY+UZz5/VvhpCzuLhSZIyWF6N64vVmTSe3C9tNrKcXi3vB98a9PsAV3tAcAoOtdlO9iTWct/ yyXSPsBX9As1PO7hBSJ34uko5v8knpSjGdEy2wVHoa1GJVLVyM9izB/qdmvF5TuDDUlCOF+97cQqz tVOgLi8g==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl42-00DXCX-MI; Wed, 14 Apr 2021 19:20:39 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2f-00DX3o-Fx for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=dBcmk8hgXkjZTFcE6yG1vqcpDqUWsuaa6mvE1XbAMsg=; b=ximKq/cbeUc0NmfIiIwpQ3RYpY DzSNXgUNc3x+IM9jeUuV11y0ljhp2dK5LLxBIMZ2UsQDKrmUV/GXg729zUImLYYucU3U3cKXQUcoA oMuRSH9WiF1kOC0Y1pq2mXy19A0doii8fg99E2t9G4xgwZ5PGq4C/KCZgBJ1HLKZaA6dhog9P6Sxs NBLrqCr6NeQv5ilZsumHf1oXSNQ0MZu0uWDDsWbT7qWfGmaisRQKo0sdxh4vGYGKwzcOnFLy0uiPo gpvINXCgCzPLlrf1D6eEo7ih88rfMu304KDMF0wFj1KQI0MtrEf71chgbc/dLN3ZBXl+CKEE4s0Tm S/daAaBg==; Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2c-0082qJ-2H for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:12 +0000 Received: by mail-wr1-x42b.google.com with SMTP id g9so4899122wrx.0 for ; Wed, 14 Apr 2021 12:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dBcmk8hgXkjZTFcE6yG1vqcpDqUWsuaa6mvE1XbAMsg=; b=hJFYE7AHZMZVsvK/43rrwqA/JEyCwQ2+d9VaYGsl6aJ1AISyns1jXnkIsvW6Su4tZM yXoz4/iWHSvnAiX0rC1dXWKNN4dVEfrEnP144wPA1EFAe2piqVtbEWpLVLGRdo/D2qnA X5h2ML67mrORfKQ8FIZxJV1AHQ4SGPORWSmoyuzE+ThVKOMXE3VSUkq/F1Az/FyVgnAj uu8nd5oM+EXPhtErJ4rhNt/J48D7xX5PPsurjJJA1JK6t1l/nCKF7/EWv03VLQbWx2tL VPNb4fktEbcEGvR9GchM5g2z5UQyY518j410PP+Uk63M9brPp5EebYfgqOLrfFuLjIzz 9KBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dBcmk8hgXkjZTFcE6yG1vqcpDqUWsuaa6mvE1XbAMsg=; b=WK3EVsY4JQekdIvYl6IG+u1pYokgKAFyuvCmCeTTsEP2z6LfSzriUZy6HP6z0socqV Qb8/M0rOldnUrGTZhkbQeReGqlThMySifHoElgpGeIBDd/ELzMAcT6iihnIoBLm+UuAR rt2ZLkDp/5NiERg6UXHEJkG9MtiNEfrKcXTfcFCwZYBBv9b1rziLUtMleoxXbQqZ7Buo 4emNcK+E2s7vNW2hykC/s9ZG7+B1Rab9dwVTS7BQoI+oVnz5sHcLPN7xSfQe9oC4Gtgu tCxHXR4vcCOrBoM89PGfEcE5q5eHdPuRlWB7HJKWQfVmFvjHVTj+7kuqNr/GhgQ7F8TV AvJg== X-Gm-Message-State: AOAM530+L/05lWW7zvf7VnHPE7XBGudQZLoN0lvy0C973I0dYPICrqpj zKp2brcQUGkhr74buR+MUmAjT9xWzjdayA== X-Google-Smtp-Source: ABdhPJzTlyQvo6iOA38f9dm1Onz7lgZldJMolr9XI3/B3NtOPKOD5ZfRzfuWUKPoLgOx0mwkR50wSg== X-Received: by 2002:adf:cc89:: with SMTP id p9mr35457681wrj.223.1618427948915; Wed, 14 Apr 2021 12:19:08 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:08 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 03/10] coresight: config: Add configuration and feature generic functions Date: Wed, 14 Apr 2021 20:18:56 +0100 Message-Id: <20210414191903.18349-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121910_232821_057BF7DD X-CRM114-Status: GOOD ( 34.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds a set of generic support functions that allow devices to set and save features values on the device, and enable and disable configurations. Additional functions for other common operations including feature reset. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-config.c | 275 ++++++++++++++++++ .../hwtracing/coresight/coresight-config.h | 9 + .../hwtracing/coresight/coresight-syscfg.c | 3 +- 4 files changed, 287 insertions(+), 2 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config.c diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 3d037f17aade..63ecfc3cf66d 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -4,7 +4,7 @@ # obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ - coresight-sysfs.o coresight-syscfg.o + coresight-sysfs.o coresight-syscfg.o coresight-config.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-config.c b/drivers/hwtracing/coresight/coresight-config.c new file mode 100644 index 000000000000..3c501e027bc0 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-config.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2020 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#include +#include "coresight-config.h" +#include "coresight-priv.h" + +/* + * This provides a set of generic functions that operate on configurations + * and features to manage the handling of parameters, the programming and + * saving of registers used by features on devices. + */ + +/* + * Write the value held in the register structure into the driver internal memory + * location. + */ +static void cscfg_set_reg(struct cscfg_regval_csdev *reg_csdev) +{ + u32 *p_val32 = (u32 *)reg_csdev->driver_regval; + u32 tmp32 = reg_csdev->reg_desc.val32; + + if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) { + *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64; + return; + } + + if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_MASK) { + tmp32 = *p_val32; + tmp32 &= ~reg_csdev->reg_desc.mask32; + tmp32 |= reg_csdev->reg_desc.val32 & reg_csdev->reg_desc.mask32; + } + *p_val32 = tmp32; +} + +/* + * Read the driver value into the reg if this is marked as one we want to save. + */ +static void cscfg_save_reg(struct cscfg_regval_csdev *reg_csdev) +{ + if (!(reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_SAVE)) + return; + if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) + reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval); + else + reg_csdev->reg_desc.val32 = *(u32 *)(reg_csdev->driver_regval); +} + +/* + * Some register values are set from parameters. Initialise these registers + * from the current parameter values. + */ +static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev, + struct cscfg_regval_desc *reg_desc, + struct cscfg_regval_csdev *reg_csdev) +{ + struct cscfg_parameter_csdev *param_csdev; + + /* for param, load routines have validated the index */ + param_csdev = &feat_csdev->params_csdev[reg_desc->param_idx]; + param_csdev->reg_csdev = reg_csdev; + param_csdev->val64 = reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT; + + if (param_csdev->val64) + reg_csdev->reg_desc.val64 = param_csdev->current_value; + else + reg_csdev->reg_desc.val32 = (u32)param_csdev->current_value; +} + +/* set values into the driver locations referenced in cscfg_reg_csdev */ +static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev) +{ + int i; + + spin_lock(feat_csdev->drv_spinlock); + for (i = 0; i < feat_csdev->nr_regs; i++) + cscfg_set_reg(&feat_csdev->regs_csdev[i]); + spin_unlock(feat_csdev->drv_spinlock); + dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", + feat_csdev->feat_desc->name, "set on enable"); + return 0; +} + +/* copy back values from the driver locations referenced in cscfg_reg_csdev */ +static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev) +{ + int i; + + spin_lock(feat_csdev->drv_spinlock); + for (i = 0; i < feat_csdev->nr_regs; i++) + cscfg_save_reg(&feat_csdev->regs_csdev[i]); + spin_unlock(feat_csdev->drv_spinlock); + dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s", + feat_csdev->feat_desc->name, "save on disable"); +} + +/* default reset - restore default values */ +void cscfg_reset_feat(struct cscfg_feature_csdev *feat_csdev) +{ + struct cscfg_regval_desc *reg_desc; + struct cscfg_regval_csdev *reg_csdev; + int i; + + /* + * set the default values for all parameters and regs from the + * relevant static descriptors. + */ + for (i = 0; i < feat_csdev->nr_params; i++) + feat_csdev->params_csdev[i].current_value = + feat_csdev->feat_desc->params_desc[i].value; + + for (i = 0; i < feat_csdev->nr_regs; i++) { + reg_desc = &feat_csdev->feat_desc->regs_desc[i]; + reg_csdev = &feat_csdev->regs_csdev[i]; + reg_csdev->reg_desc.type = reg_desc->type; + + /* check if reg set from a parameter otherwise desc default */ + if (reg_desc->type & CS_CFG_REG_TYPE_VAL_PARAM) + cscfg_init_reg_param(feat_csdev, reg_desc, reg_csdev); + else + /* + * for normal values the union between val64 & val32 + mask32 + * allows us to init using the 64 bit value + */ + reg_csdev->reg_desc.val64 = reg_desc->val64; + } +} + +/* + * For the selected presets, we set the register associated with the parameter, to + * the value of the preset index associated with the parameter. + */ +static int cscfg_update_presets(struct cscfg_config_csdev *config_csdev, int preset) +{ + int i, j, val_idx = 0, nr_cfg_params; + struct cscfg_parameter_csdev *param_csdev; + struct cscfg_feature_csdev *feat_csdev; + const struct cscfg_config_desc *config_desc = config_csdev->config_desc; + const char *name; + const u64 *preset_base; + u64 val; + + /* preset in range 1 to nr_presets */ + if (preset < 1 || preset > config_desc->nr_presets) + return -EINVAL; + /* + * Go through the array of features, assigning preset values to + * feature parameters in the order they appear. + * There should be precisely the same number of preset values as the + * sum of number of parameters over all the features - but we will + * ensure there is no overrun. + */ + nr_cfg_params = config_desc->nr_total_params; + preset_base = &config_desc->presets[(preset - 1) * nr_cfg_params]; + for (i = 0; i < config_csdev->nr_feat; i++) { + feat_csdev = config_csdev->feats_csdev[i]; + if (!feat_csdev->nr_params) + continue; + + for (j = 0; j < feat_csdev->nr_params; j++) { + param_csdev = &feat_csdev->params_csdev[j]; + name = feat_csdev->feat_desc->params_desc[j].name; + val = preset_base[val_idx++]; + if (param_csdev->val64) { + dev_dbg(&config_csdev->csdev->dev, + "set param %s (%lld)", name, val); + param_csdev->reg_csdev->reg_desc.val64 = val; + } else { + param_csdev->reg_csdev->reg_desc.val32 = (u32)val; + dev_dbg(&config_csdev->csdev->dev, + "set param %s (%d)", name, (u32)val); + } + } + + /* exit early if all params filled */ + if (val_idx >= nr_cfg_params) + break; + } + return 0; +} + +/* + * if we are not using a preset, then need to update the feature params + * with current values. This sets the register associated with the parameter + * with the current value of that parameter. + */ +static int cscfg_update_curr_params(struct cscfg_config_csdev *config_csdev) +{ + int i, j; + struct cscfg_feature_csdev *feat_csdev; + struct cscfg_parameter_csdev *param_csdev; + const char *name; + u64 val; + + for (i = 0; i < config_csdev->nr_feat; i++) { + feat_csdev = config_csdev->feats_csdev[i]; + if (!feat_csdev->nr_params) + continue; + for (j = 0; j < feat_csdev->nr_params; j++) { + param_csdev = &feat_csdev->params_csdev[j]; + name = feat_csdev->feat_desc->params_desc[j].name; + val = param_csdev->current_value; + if (param_csdev->val64) { + dev_dbg(&config_csdev->csdev->dev, + "set param %s (%lld)", name, val); + param_csdev->reg_csdev->reg_desc.val64 = val; + } else { + param_csdev->reg_csdev->reg_desc.val32 = (u32)val; + dev_dbg(&config_csdev->csdev->dev, + "set param %s (%d)", name, (u32)val); + } + } + } + return 0; +} + +/* + * Configuration values will be programmed into the driver locations if enabling, or read + * from relevant locations on disable. + */ +static int cscfg_prog_config(struct cscfg_config_csdev *config_csdev, bool enable) +{ + int i, err = 0; + struct cscfg_feature_csdev *feat_csdev; + struct coresight_device *csdev; + + for (i = 0; i < config_csdev->nr_feat; i++) { + feat_csdev = config_csdev->feats_csdev[i]; + csdev = feat_csdev->csdev; + dev_dbg(&csdev->dev, "cfg %s; %s feature:%s", config_csdev->config_desc->name, + enable ? "enable" : "disable", feat_csdev->feat_desc->name); + + if (enable) + err = cscfg_set_on_enable(feat_csdev); + else + cscfg_save_on_disable(feat_csdev); + + if (err) + break; + } + return err; +} + +/* + * Enable configuration for the device. Will result in the internal driver data + * being updated ready for programming into the device. + * + * @config_csdev: config_csdev to set. + * @preset: preset values to use - 0 for default. + */ +int cscfg_csdev_enable_config(struct cscfg_config_csdev *config_csdev, int preset) +{ + int err = 0; + + if (preset) + err = cscfg_update_presets(config_csdev, preset); + else + err = cscfg_update_curr_params(config_csdev); + if (!err) + err = cscfg_prog_config(config_csdev, true); + if (!err) + config_csdev->enabled = true; + return err; +} + +void cscfg_csdev_disable_config(struct cscfg_config_csdev *config_csdev) +{ + if (config_csdev->enabled) { + cscfg_prog_config(config_csdev, false); + config_csdev->enabled = false; + } +} diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 685fb46ce893..5a39cbbc38a4 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -237,4 +237,13 @@ struct cscfg_csdev_feat_ops { struct cscfg_feature_csdev *feat_csdev); }; +/* coresight config helper functions*/ + +/* enable / disable config on a device - called with appropriate locks set.*/ +int cscfg_csdev_enable_config(struct cscfg_config_csdev *config_csdev, int preset); +void cscfg_csdev_disable_config(struct cscfg_config_csdev *config_csdev); + +/* reset a feature to default values */ +void cscfg_reset_feat(struct cscfg_feature_csdev *feat_csdev); + #endif /* _CORESIGHT_CORESIGHT_CONFIG_H */ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index e93e62c1efbb..c7f48d6b48f5 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -190,9 +190,10 @@ static int cscfg_load_feat_csdev(struct coresight_device *csdev, if (err) return err; - /* add to internal csdev feature list */ + /* add to internal csdev feature list & initialise using reset call */ mutex_lock(&cscfg_csdev_mutex); list_add(&feat_csdev->node, &csdev->feature_csdev_list); + cscfg_reset_feat(feat_csdev); mutex_unlock(&cscfg_csdev_mutex); return 0; From patchwork Wed Apr 14 19:18:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A21B9C433B4 for ; Wed, 14 Apr 2021 19:23:53 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D20861168 for ; Wed, 14 Apr 2021 19:23:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D20861168 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UgMzWJSfte4iDhz+X+oG716IRRHaP2UObfk3AcVq/Ws=; b=KT9YmG2c8cA2C0jGUGCi7Gx8gt Sb+cXG74DbzTeklEZ9K56+EWemjmSnQez8rvylBylBO00nEDxpxSsB2u3IvSHK8v6WTRmA8A/USja ziqXoH9MiBcRTCMLlM1xZIFa+U1WwPbSg3eu+EsPvBaji3c8WiHCSJ0YQ/LtRDT0tGaj1PJnGOSOG FGf1mQByrvupnjkl71SM/kFAiIBaipma83bSQERwdaMtXIHfy1gn6IXWJsykcASdHXMVMngPaVf/f n60JcTrBfgA9iHr4dbF1YbwPqJhoRB3fC6SFNvjAXXnEo26f49ct2hjoot63Qj1+O8dwRbxPdg+79 3CDZkEAw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl4n-00DXNS-BO; Wed, 14 Apr 2021 19:21:29 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2g-00DX3y-J8 for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=cs4GEHkfiezMtdApLAhphrqcTCVtFJEwDGdAxOMCXts=; b=ZzOiKl3MgsUkFXQL3w3QtSOMAO dNLgnm7bIXafzgFiEu7Dwp1SclSFb5zeIPGbvRBn++Y1ImFFWC6/wNZd6ufKDP83ucmqzhXkv0fPB 67ylEL3xTr6+4xcLFt2hGEaXjS8T9UEshI54KUPWn5iaVLcPuKwFE1EvuyjGnIaX3PzAwPHuCwLBH LTQBdoyYwqrVH3oi19JRzgIrlPkr54tLr1MTNBp3z5xoaBYLop0uOoS2q5RORnfyTuTx2rVZqbltK bkP6Iphgxg9l372avSSdaSP9t3oRo96XrHlTeDp3IgmTV0abQkceou7j8jfZoOahjawX7Gh1oR68U sv8CU1Wg==; Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2d-0082qX-Dz for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:13 +0000 Received: by mail-wr1-x42d.google.com with SMTP id g9so4899155wrx.0 for ; Wed, 14 Apr 2021 12:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cs4GEHkfiezMtdApLAhphrqcTCVtFJEwDGdAxOMCXts=; b=chFWFyW0cFqh9GdS6EZEpxgoClbgg7VX2mOW5cjB9UUvlCu1CEp82xdhLNGuf3dT/l 9x4el46gzH9vfMl+zG4A3UcORN5bpG9mN+GSH1S/BbI8DVtjrgXhFY7HJhWLU21njMWa AmENShCbMay2MQoqHfbAd5WAi57Nl6nFzqF0HqqGto5UC7sq3KAloRcowIYsp9CFTlxC 2VXD/jjDWmCKDCf71wncwhJGhgnOUSlBwvD6aj/0zF06xMixCp8LYU7F1IH97fq07iXw Pr4Td7++KkqJroOuna5F/uyv6yR7gUiR9W4CLjg6CW1toJIi95qxpxvj1CHWyZvCHfTa LDsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cs4GEHkfiezMtdApLAhphrqcTCVtFJEwDGdAxOMCXts=; b=Rr6pmMJO0GFo0jeVjN8VamQfLdVyHA8Tiu2HbwlIB4HGmAFjaMfgiRR28JTQTvpc1u WwiF0B+7Bnt4721jmeSlUp/CTuDjrmA7c7hJ65KPug1vtghZkdJhH/BQ1Q3iBxRuePMx 5A1ozEV35att0/+Km+H9MmY606v2s0sWgpRqemWyWMNMoXn89MmUvZ8eURDPgLewnAk6 /X5FcoqTdkTAgw2eEQKSoay7Avx1ZJnm+PFF3ze3q1QnhuXqpnw+WkdIhD3J5imlADba x7qKj4WrW1nXqZVQabRORq4VyEPyCQG0NiKNJW0hSAOgH/jxsxspIEXOKSTaGWSfsq4B SI9A== X-Gm-Message-State: AOAM531sEudf4wjP0wI2fQlOm/q6WpeOgrf06802ZLRxuFeqqucc6+Kx Gbql5020MjN4Dh8ZRtjsAUZzT4SxC3S9pg== X-Google-Smtp-Source: ABdhPJyv5E3fQ+sKraWuZr1vcRHRVdCf4gb5HPRGXwABFXbbsVbYPRY6ytvy0J5eU9xgRZTqyypL0A== X-Received: by 2002:a05:6000:178c:: with SMTP id e12mr6253161wrg.42.1618427949649; Wed, 14 Apr 2021 12:19:09 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:09 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 04/10] coresight: etm-perf: update to handle configuration selection Date: Wed, 14 Apr 2021 20:18:57 +0100 Message-Id: <20210414191903.18349-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121911_499143_AB096D4B X-CRM114-Status: GOOD ( 32.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Loaded coresight configurations are registered in the cs_etm\events sub directory. This extends the etm-perf code to handle these registrations, and the cs_syscfg driver to perform the registration on load. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-etm-perf.c | 134 ++++++++++++++---- .../hwtracing/coresight/coresight-etm-perf.h | 8 ++ .../hwtracing/coresight/coresight-syscfg.c | 11 ++ 4 files changed, 127 insertions(+), 28 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 5a39cbbc38a4..0667581822c1 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -126,6 +126,7 @@ struct cscfg_feature_desc { * @nr_presets: Number of sets of presets supplied by this configuration. * @nr_total_params: Sum of all parameters declared by used features * @presets: Array of preset values. + * @event_ea: Extended attribute for perf event value * */ struct cscfg_config_desc { @@ -137,6 +138,7 @@ struct cscfg_config_desc { int nr_presets; int nr_total_params; const u64 *presets; /* nr_presets * nr_total_params */ + struct dev_ext_attribute *event_ea; }; /** diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 15310c72f89f..26b4bca156aa 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -18,8 +18,10 @@ #include #include +#include "coresight-config.h" #include "coresight-etm-perf.h" #include "coresight-priv.h" +#include "coresight-syscfg.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -57,8 +59,13 @@ PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); PMU_FORMAT_ATTR(contextid2, "config:" __stringify(ETM_OPT_CTXTID2)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); +/* preset - if sink ID is used as a configuration selector */ +PMU_FORMAT_ATTR(preset, "config:0-3"); /* Sink ID - same for all ETMs */ PMU_FORMAT_ATTR(sinkid, "config2:0-31"); +/* config ID - set if a system configuration is selected */ +PMU_FORMAT_ATTR(configid, "config2:32-63"); + /* * contextid always traces the "PID". The PID is in CONTEXTIDR_EL1 @@ -88,6 +95,8 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_timestamp.attr, &format_attr_retstack.attr, &format_attr_sinkid.attr, + &format_attr_preset.attr, + &format_attr_configid.attr, NULL, }; @@ -105,9 +114,19 @@ static const struct attribute_group etm_pmu_sinks_group = { .attrs = etm_config_sinks_attr, }; +static struct attribute *etm_config_events_attr[] = { + NULL, +}; + +static const struct attribute_group etm_pmu_events_group = { + .name = "events", + .attrs = etm_config_events_attr, +}; + static const struct attribute_group *etm_pmu_attr_groups[] = { &etm_pmu_format_group, &etm_pmu_sinks_group, + &etm_pmu_events_group, NULL, }; @@ -286,7 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, INIT_WORK(&event_data->work, free_event_data); /* First get the selected sink from user space. */ - if (event->attr.config2) { + if (event->attr.config2 & GENMASK_ULL(31, 0)) { id = (u32)event->attr.config2; sink = user_sink = coresight_get_sink_by_id(id); } @@ -658,68 +677,127 @@ static ssize_t etm_perf_sink_name_show(struct device *dev, return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var)); } -int etm_perf_add_symlink_sink(struct coresight_device *csdev) +static struct dev_ext_attribute * +etm_perf_add_symlink_group(struct device *dev, const char *name, const char *group_name) { - int ret; + struct dev_ext_attribute *ea; unsigned long hash; - const char *name; + int ret; struct device *pmu_dev = etm_pmu.dev; - struct device *dev = &csdev->dev; - struct dev_ext_attribute *ea; - - if (csdev->type != CORESIGHT_DEV_TYPE_SINK && - csdev->type != CORESIGHT_DEV_TYPE_LINKSINK) - return -EINVAL; - - if (csdev->ea != NULL) - return -EINVAL; if (!etm_perf_up) - return -EPROBE_DEFER; + return ERR_PTR(-EPROBE_DEFER); ea = devm_kzalloc(dev, sizeof(*ea), GFP_KERNEL); if (!ea) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - name = dev_name(dev); - /* See function coresight_get_sink_by_id() to know where this is used */ + /* + * If this function is called adding a sink then the hash is used for + * sink selection - see function coresight_get_sink_by_id(). + * If adding a configuration then the hash is used for selection in + * cscfg_activate_config() + */ hash = hashlen_hash(hashlen_string(NULL, name)); sysfs_attr_init(&ea->attr.attr); ea->attr.attr.name = devm_kstrdup(dev, name, GFP_KERNEL); if (!ea->attr.attr.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); ea->attr.attr.mode = 0444; - ea->attr.show = etm_perf_sink_name_show; ea->var = (unsigned long *)hash; ret = sysfs_add_file_to_group(&pmu_dev->kobj, - &ea->attr.attr, "sinks"); + &ea->attr.attr, group_name); - if (!ret) - csdev->ea = ea; + return ret ? ERR_PTR(ret) : ea; +} - return ret; +int etm_perf_add_symlink_sink(struct coresight_device *csdev) +{ + const char *name; + struct device *dev = &csdev->dev; + int err = 0; + + if (csdev->type != CORESIGHT_DEV_TYPE_SINK && + csdev->type != CORESIGHT_DEV_TYPE_LINKSINK) + return -EINVAL; + + if (csdev->ea != NULL) + return -EINVAL; + + name = dev_name(dev); + csdev->ea = etm_perf_add_symlink_group(dev, name, "sinks"); + if (IS_ERR(csdev->ea)) { + err = PTR_ERR(csdev->ea); + csdev->ea = NULL; + } else + csdev->ea->attr.show = etm_perf_sink_name_show; + + return err; } -void etm_perf_del_symlink_sink(struct coresight_device *csdev) +static void etm_perf_del_symlink_group(struct dev_ext_attribute *ea, const char *group_name) { struct device *pmu_dev = etm_pmu.dev; - struct dev_ext_attribute *ea = csdev->ea; + sysfs_remove_file_from_group(&pmu_dev->kobj, + &ea->attr.attr, group_name); +} + +void etm_perf_del_symlink_sink(struct coresight_device *csdev) +{ if (csdev->type != CORESIGHT_DEV_TYPE_SINK && csdev->type != CORESIGHT_DEV_TYPE_LINKSINK) return; - if (!ea) + if (!csdev->ea) return; - sysfs_remove_file_from_group(&pmu_dev->kobj, - &ea->attr.attr, "sinks"); + etm_perf_del_symlink_group(csdev->ea, "sinks"); csdev->ea = NULL; } +static ssize_t etm_perf_cscfg_event_show(struct device *dev, + struct device_attribute *dattr, + char *buf) +{ + struct dev_ext_attribute *ea; + + ea = container_of(dattr, struct dev_ext_attribute, attr); + return scnprintf(buf, PAGE_SIZE, "configid=0x%lx\n", (unsigned long)(ea->var)); +} + +int etm_perf_add_symlink_cscfg(struct device *dev, struct cscfg_config_desc *config_desc) +{ + int err = 0; + + if (config_desc->event_ea != NULL) + return 0; + + config_desc->event_ea = etm_perf_add_symlink_group(dev, config_desc->name, "events"); + + /* set the show function to the custom cscfg event */ + if (!IS_ERR(config_desc->event_ea)) + config_desc->event_ea->attr.show = etm_perf_cscfg_event_show; + else { + err = PTR_ERR(config_desc->event_ea); + config_desc->event_ea = NULL; + } + + return err; +} + +void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc) +{ + if (!config_desc->event_ea) + return; + + etm_perf_del_symlink_group(config_desc->event_ea, "events"); + config_desc->event_ea = NULL; +} + int __init etm_perf_init(void) { int ret; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 29d90dfeba31..ba617fe2217e 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -11,6 +11,7 @@ #include "coresight-priv.h" struct coresight_device; +struct cscfg_config_desc; /* * In both ETMv3 and v4 the maximum number of address comparator implentable @@ -69,6 +70,9 @@ static inline void *etm_perf_sink_config(struct perf_output_handle *handle) return data->snk_config; return NULL; } +int etm_perf_add_symlink_cscfg(struct device *dev, + struct cscfg_config_desc *config_desc); +void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc); #else static inline int etm_perf_symlink(struct coresight_device *csdev, bool link) { return -EINVAL; } @@ -79,6 +83,10 @@ static inline void *etm_perf_sink_config(struct perf_output_handle *handle) { return NULL; } +int etm_perf_add_symlink_cscfg(struct device *dev, + struct cscfg_config_desc *config_desc) +{ return -EINVAL; } +void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc) {} #endif /* CONFIG_CORESIGHT */ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index c7f48d6b48f5..e35f8c0ac2f8 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -7,6 +7,7 @@ #include #include "coresight-config.h" +#include "coresight-etm-perf.h" #include "coresight-syscfg.h" /* @@ -276,6 +277,11 @@ static int cscfg_load_config(struct cscfg_config_desc *config_desc) if (err) return err; + /* add config to perf fs to allow selection */ + err = etm_perf_add_symlink_cscfg(cscfg_device(), config_desc); + if (err) + return err; + list_add(&config_desc->item, &cscfg_mgr->config_desc_list); return 0; } @@ -508,7 +514,12 @@ static int cscfg_create_device(void) static void cscfg_clear_device(void) { + struct cscfg_config_desc *cfg_desc; + mutex_lock(&cscfg_mutex); + list_for_each_entry(cfg_desc, &cscfg_mgr->config_desc_list, item) { + etm_perf_del_symlink_cscfg(cfg_desc); + } device_unregister(cscfg_device()); mutex_unlock(&cscfg_mutex); } From patchwork Wed Apr 14 19:18:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99031C433ED for ; Wed, 14 Apr 2021 19:23:09 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 22E8C6113B for ; Wed, 14 Apr 2021 19:23:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 22E8C6113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CdrKDGL4xyw0CVFkSYObjvi3PER6Boc4updYi96NmUY=; b=AJkUc/SjEd0e5rrTYjaWyTa5b1 BFpW+q/cGuQ7XlkHQWdIF5ACWQ5NEO8PMXyF/fMjVRpd+mV8xb4x1wmY8E9xNomv1OcCPzGJ3OtdC qi17JoG7RD3l7HpOWUF52webTRFBnKlLt3xszmuMo9FLp6EsUjjC1q7uP+kuqrHc4SuMtNPl/Xatg YlnWwp8oN1ovZaWNrSPKVb7SjLA2+NsmXMAu5B8A0r8bTpBatpjG7rcY1xv0yP44Bwr3Mv0sv6sqT qGLLwEomnAcwz3EZBOL7GeknUAOIBqwjWxScjzFY7LUWQ7IDsQR7o6skL0AdYiDn2Z7eFoHiMlCia OeOSNygg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl4a-00DXJP-Sg; Wed, 14 Apr 2021 19:21:13 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2g-00DX40-MM for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=8efoKnLMcNGx9K9jtqD6t1w/9lJFWQwoudidfCPdxNo=; b=W8lEt/RRWa1eVaNH1Ek+ru3QQl fQiIk6Du7X/EtkjcLVtqo5OTMj0Tv5Z/Lp9VqkYjihQADhH7C03d2XIec7qo10bGCLnSALXETwnOR HtV/AZAm/IekSrLYAycpSHklUhcJeIodutKPVTBEN1a11fWaWzubnby5SsYjqDa6wfd7Z56FiIk8D 6D0W7U5uAL7R0He2fXCHXEfSPbR2Q6MgrucNz1Dy8fg464/+uDzWXGyISCFW6Uie88N8lmaBnMZQ9 EiOywDaoU1J+qLXenZJJ8mTe8IV3FVq6VWrGWprP0bP+weGCGgq/E2ZmssB4WjvZqB6V0Gh003I+m O5i5ZnZw==; Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2d-0082qo-Hc for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:13 +0000 Received: by mail-wr1-x42d.google.com with SMTP id 12so20942555wrz.7 for ; Wed, 14 Apr 2021 12:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8efoKnLMcNGx9K9jtqD6t1w/9lJFWQwoudidfCPdxNo=; b=GN82HxL12krNroUk1ioRoQatuVxwYlUHfW0om+/YolkhfUUxVFIXa/F8C+gXWn4guo YefLs5yXOOptwOY8rMTL7T3zOdPCFc5EGJAYyAel/8u9N21QL/KWLaVL5NWfYuZxHOYS X8crZjJA9G1rO5PACpfuRoswjFFORaUAdq8nbGh9QRYYVKyvRsl4Clg7qXeQBqnjGQuL +C/1q9wkfE0etw8AGqXqyaKe6fFLg4KsFSvNXRI3tYuOZGfedA+oTSbwdjfD+huieb0w Wwvqzs8nGLo0QFhALGpm4mPcNxSGcLbPEb0RIVtgXaX4l3hPjwkLTDUikAw65U+4srQd wlvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8efoKnLMcNGx9K9jtqD6t1w/9lJFWQwoudidfCPdxNo=; b=BcXpSeX5basRKxkkfCn/M1E7bO3qdICq263KvutzDISXBYYOUBzhAI3eZ+WTOU6M5Q 8j3sq2Ux8/3TyVMrJdLasmQwZFWreJ1NxeaI2Nu89iURkcx0w8eTdGVewVr4XSVOb31T 338oFw4+cx/drl/KxAKMcX4y90sW/St8Y3y2fC2vXmWhlkxqAilrsxVxvgv8c/UeJs5N jumZE+k82BsAh1TBKVJuU9M+SA8YMwV7dM2T5Rbe2T4rpX58FkDWttRoWNj/rHUinkt5 YtOA1LX9Vo/dHgQyHVgDKZksFWXEQ3GQ2CYK12fJXjJ5Jm65vE8L6NzxN8pkwm4C8i9W ImdQ== X-Gm-Message-State: AOAM532tavLfpb7kKHRM+IINdZ8raO3PQgb1byVS7vrjd6xq3XUhz7U/ THSg5dMUz3Uo4lvAh4nTOaFObFAKcwLniA== X-Google-Smtp-Source: ABdhPJyqtcTuhprYItNy07J6jXpOxNYfTuQMfiRXzjA5KZ2wXr148xF4ASxrEcDv5JYljtWQufXMww== X-Received: by 2002:a5d:678e:: with SMTP id v14mr10193678wru.156.1618427950351; Wed, 14 Apr 2021 12:19:10 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:10 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 05/10] coresight: syscfg: Add API to activate and enable configurations Date: Wed, 14 Apr 2021 20:18:58 +0100 Message-Id: <20210414191903.18349-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121911_619617_1CCCFD99 X-CRM114-Status: GOOD ( 28.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Configurations are first activated, then when any coresight device is enabled, the active configurations are checked and any matching one is enabled. This patch provides the activation / enable API. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-config.h | 2 + .../hwtracing/coresight/coresight-syscfg.c | 172 ++++++++++++++++++ .../hwtracing/coresight/coresight-syscfg.h | 8 + include/linux/coresight.h | 2 + 4 files changed, 184 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h index 0667581822c1..25eb6c632692 100644 --- a/drivers/hwtracing/coresight/coresight-config.h +++ b/drivers/hwtracing/coresight/coresight-config.h @@ -127,6 +127,7 @@ struct cscfg_feature_desc { * @nr_total_params: Sum of all parameters declared by used features * @presets: Array of preset values. * @event_ea: Extended attribute for perf event value + * @active_cnt: ref count for activate on this configuration. * */ struct cscfg_config_desc { @@ -139,6 +140,7 @@ struct cscfg_config_desc { int nr_total_params; const u64 *presets; /* nr_presets * nr_total_params */ struct dev_ext_attribute *event_ea; + atomic_t active_cnt; }; /** diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index e35f8c0ac2f8..b234e45c153f 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -283,6 +283,7 @@ static int cscfg_load_config(struct cscfg_config_desc *config_desc) return err; list_add(&config_desc->item, &cscfg_mgr->config_desc_list); + atomic_set(&config_desc->active_cnt, 0); return 0; } @@ -468,6 +469,176 @@ void cscfg_unregister_csdev(struct coresight_device *csdev) } EXPORT_SYMBOL_GPL(cscfg_unregister_csdev); +/** + * cscfg_csdev_reset_feats - reset features for a CoreSight device. + * + * Resets all parameters and register values for any features loaded + * into @csdev to their default values. + * + * @csdev: The CoreSight device. + */ +void cscfg_csdev_reset_feats(struct coresight_device *csdev) +{ + struct cscfg_feature_csdev *feat_csdev; + + mutex_lock(&cscfg_csdev_mutex); + if (list_empty(&csdev->feature_csdev_list)) + goto unlock_exit; + + list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node) + cscfg_reset_feat(feat_csdev); + +unlock_exit: + mutex_unlock(&cscfg_csdev_mutex); +} +EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats); + +/** + * cscfg_activate_config - Mark a configuration descriptor as active. + * + * This will be seen when csdev devices are enabled in the system. + * Only activated configurations can be enabled on individual devices. + * Activation protects the configuration from alteration or removal while + * active. + * + * Selection by hash value - generated from the configuration name when it + * was loaded and added to the cs_etm/configurations file system for selection + * by perf. + * + * Increments the configuration descriptor active count and the global active + * count. + * + * @cfg_hash: Hash value of the selected configuration name. + */ +int cscfg_activate_config(unsigned long cfg_hash) +{ + struct cscfg_config_desc *config_desc; + int err = -EINVAL; + + mutex_lock(&cscfg_mutex); + + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { + if ((unsigned long)config_desc->event_ea->var == cfg_hash) { + /* + * increment the global active count - control changes to + * active configurations + */ + atomic_inc(&cscfg_mgr->sys_active_cnt); + + /* + * mark the descriptor as active so enable config on a + * device instance will use it + */ + atomic_inc(&config_desc->active_cnt); + + err = 0; + dev_dbg(cscfg_device(), "Activate config %s.\n", config_desc->name); + break; + } + } + mutex_unlock(&cscfg_mutex); + + return err; +} +EXPORT_SYMBOL_GPL(cscfg_activate_config); + +/** + * cscfg_deactivate_config - Mark a config descriptor as inactive. + * + * Decrement the configuration and global active counts. + * + * @cfg_hash: Hash value of the selected configuration name. + */ +void cscfg_deactivate_config(unsigned long cfg_hash) +{ + struct cscfg_config_desc *config_desc; + + mutex_lock(&cscfg_mutex); + + list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { + if ((unsigned long)config_desc->event_ea->var == cfg_hash) { + atomic_dec(&config_desc->active_cnt); + atomic_dec(&cscfg_mgr->sys_active_cnt); + dev_dbg(cscfg_device(), "Deactivate config %s.\n", config_desc->name); + break; + } + } + mutex_unlock(&cscfg_mutex); +} +EXPORT_SYMBOL_GPL(cscfg_deactivate_config); + +/** + * cscfg_csdev_enable_active_config - Enable matching active configuration for device. + * + * Enables the configuration selected by @cfg_hash if the configuration is supported + * on the device and has been activated. + * + * If active and supported the CoreSight device @csdev will be programmed with the + * configuration, using @preset parameters. + * + * Should be called before driver hardware enable for the requested device, prior to + * programming and enabling the physical hardware. + * + * @csdev: CoreSight device to program. + * @cfg_hash: Selector for the configuration. + * @preset: Preset parameter values to use, 0 for current / default values. + */ +int cscfg_csdev_enable_active_config(struct coresight_device *csdev, + unsigned long cfg_hash, int preset) +{ + struct cscfg_config_csdev *config_csdev_active = NULL, *config_csdev_item; + const struct cscfg_config_desc *config_desc; + int err = 0; + + /* quickly check global count */ + if (!atomic_read(&cscfg_mgr->sys_active_cnt)) + return 0; + + mutex_lock(&cscfg_csdev_mutex); + list_for_each_entry(config_csdev_item, &csdev->config_csdev_list, node) { + config_desc = config_csdev_item->config_desc; + if ((atomic_read(&config_desc->active_cnt)) && + ((unsigned long)config_desc->event_ea->var == cfg_hash)) { + config_csdev_active = config_csdev_item; + break; + } + } + if (config_csdev_active) { + err = cscfg_csdev_enable_config(config_csdev_active, preset); + if (!err) + csdev->active_cscfg_ctxt = (void *)config_csdev_active; + } + mutex_unlock(&cscfg_csdev_mutex); + return err; +} +EXPORT_SYMBOL_GPL(cscfg_csdev_enable_active_config); + +/** + * cscfg_csdev_disable_active_config - disable an active config on the device. + * + * Disables the active configuration on the CoreSight device @csdev. + * Disable will save the values of any registers marked in the configurations + * as save on disable. + * + * Should be called after driver hardware disable for the requested device, + * after disabling the physical hardware and reading back registers. + * + * @csdev: The CoreSight device. + */ +void cscfg_csdev_disable_active_config(struct coresight_device *csdev) +{ + struct cscfg_config_csdev *config_csdev; + + mutex_lock(&cscfg_csdev_mutex); + config_csdev = (struct cscfg_config_csdev *)csdev->active_cscfg_ctxt; + if (config_csdev) { + cscfg_csdev_disable_config(config_csdev); + csdev->active_cscfg_ctxt = NULL; + } + mutex_unlock(&cscfg_csdev_mutex); +} +EXPORT_SYMBOL_GPL(cscfg_csdev_disable_active_config); + /* Initialise system configuration management device. */ struct device *cscfg_device(void) @@ -536,6 +707,7 @@ int __init cscfg_init(void) INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); + atomic_set(&cscfg_mgr->sys_active_cnt, 0); dev_info(cscfg_device(), "CoreSight Configuration manager initialised"); return 0; diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index 5bcae3b374c6..a52775890670 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -24,12 +24,14 @@ * @csdev_desc_list: List of coresight devices registered with the configuration manager. * @feat_desc_list: List of feature descriptors to load into registered devices. * @config_desc_list: List of system configuration descriptors to load into registered devices. + * @sys_active_cnt: Total number of active config descriptor references. */ struct cscfg_manager { struct device dev; struct list_head csdev_desc_list; struct list_head feat_desc_list; struct list_head config_desc_list; + atomic_t sys_active_cnt; }; /* get reference to dev in cscfg_manager */ @@ -61,5 +63,11 @@ int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs, int cscfg_register_csdev(struct coresight_device *csdev, u32 match_flags, struct cscfg_csdev_feat_ops *ops); void cscfg_unregister_csdev(struct coresight_device *csdev); +int cscfg_activate_config(unsigned long cfg_hash); +void cscfg_deactivate_config(unsigned long cfg_hash); +void cscfg_csdev_reset_feats(struct coresight_device *csdev); +int cscfg_csdev_enable_active_config(struct coresight_device *csdev, + unsigned long cfg_hash, int preset); +void cscfg_csdev_disable_active_config(struct coresight_device *csdev); #endif /* CORESIGHT_SYSCFG_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6fb516e1b22e..a348049ee08b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -222,6 +222,7 @@ struct coresight_sysfs_link { * @has_conns_grp: Have added a "connections" group for sysfs links. * @feature_csdev_list: List of complex feature programming added to the device. * @config_csdev_list: List of system configurations added to the device. + * @active_cscfg_ctxt: Context information for current active system configuration. */ struct coresight_device { struct coresight_platform_data *pdata; @@ -246,6 +247,7 @@ struct coresight_device { /* system configuration and feature lists */ struct list_head feature_csdev_list; struct list_head config_csdev_list; + void *active_cscfg_ctxt; }; /* From patchwork Wed Apr 14 19:18:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E6ECC43460 for ; Wed, 14 Apr 2021 19:24:10 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B100D6113B for ; Wed, 14 Apr 2021 19:24:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B100D6113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TM3xfUzeZ7mYnBmKuHBM0+xYrN7auUWWoN9k1/3yExA=; b=hNee9m0ZY3XW1LtNDjMdDVhzjy docIXPQ0V6fhJhH2Nm/FkC0A8zA+tpyzN+G+3ZlXHOULadJzAjFUUMQteLD6bIRO4Rj+Uv5dDXKbh nppbJzk+00fvqKsukiFg8wqBjgyR5LTiWjDMq3By95strjGAXRYx1Zvo9p4rqA4jrDLKzXO3gse3T 4tJ2Zp2FxYkTvZSCUOkkvlsHLqBtmuN3b0YdKcg00vheWK4lBBYlNoUvWIw4LoNIdS3zrcUu6wWpU bH3SEWYWBLbeRojuT+xrJDRk3wttGQjjtRq/mppst6qjruaonr3gH25rrQw0LfGDivpco9yqrDGFD QvxKuyEQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl5A-00DXSF-J2; Wed, 14 Apr 2021 19:21:48 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2h-00DX4C-Bt for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Qp1rtf5vTNCYxLgq97ox1ro8HilwNvlQ34tjmWDteno=; b=K6ZM1GN3n0fC+jtdIalDP/Ni97 yEUPQvM4ZDbQTQ8y0IcDbPnzJXTVhe5qF4WQUihxHXSt8ifY5CKqwkBWzq44EeJMnezVuGxyzb+tN tgCfuIrDZMFf89hQtwnPoa+/UjBJLzwcApuE6OM4hUap5Y0tRNYhpPdXKwgBHMm5zLK2lakkpfSOw t73Bvm0Nq31fqwChE3UiSAwlf/ZfzuLyuS1EhWBI9TWTRDgvkQ9rvOGBeJpGAooRFTlyfO7w4vLl+ Z2w9EA4HXdP410szTYXSBMddkWuB6FOO7KM0+BgQz+2qaaSjhnKdeKE5gq23eChf3Xb4LtUzyTTtP oo+6vxvg==; Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2e-0082qv-Qy for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:14 +0000 Received: by mail-wr1-x430.google.com with SMTP id 12so20942585wrz.7 for ; Wed, 14 Apr 2021 12:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Qp1rtf5vTNCYxLgq97ox1ro8HilwNvlQ34tjmWDteno=; b=yz3jNvqKpyMyEfgR81XsaWyGFfxC77h2/q4tnUpvVy1V80bTfLwd6chrspXEkrxvFU VAOBD+Tb27lAvw3ipOMRkbVzSn89z477PTtJhgVFxHDiL3euYLTqOxtXfnn99Fc/NJYT T3RbZHtofcibb2rM3XUqclT5y/yy9LilKmV4ivIx1MvfhYi7NKdMpIE+gOdu1pbDFPAl EfUEMk4tzY7ASCae5ciJAxHNqsMLkDnq9ljXczMr+DH3f7b8ZCstWoDXAzfKTROkMIzH WQLJTGh+GLCiWeH6vngUkiNkB4GpTkStXDJd2eYhlClI5RhFEnwOVdFm8iBEmYHa/4LF KM4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Qp1rtf5vTNCYxLgq97ox1ro8HilwNvlQ34tjmWDteno=; b=rfXxO5sGRCWRlK5R7p4Gwv5nyYx0uBm7A1SpYOn8DFJC5cj6/HGqbVMBnkFL29fbSF RUEKLwun5y7ZW+CmElfiQh5jcz5EIMkEqL2nJ4r7Hcg0kfwUzXe1W7fyAsSaop9sRKnz Fje/WG2ma3Yq6O6lnmRpWCg26+y2auaOI01wYOTbVjGtzyrP5kivygxD6nrAPiwgdQTM aEUqwA1vJ5w4J6ImvFd2OehFSzER66HW1qgyTuFvBCCCHmZnvo30c5mhRgm4jvzh/Whf cHu4bp3D9OrdzK6P3h8QkNdHXtfUsNwzaqZ4HJI0QuNXsS7eP5EsKQHedmAW3pYorFvJ 3FVw== X-Gm-Message-State: AOAM532LRHT61DMzdiwYIvl9jLsjkDtpYt2yAfmzkuiP5lopfoJ8HsPv UZoxEtt86pXjv/ApX/4BEwSbP4TnO1VA8Q== X-Google-Smtp-Source: ABdhPJwq1IQoqE7/mmybFnQ9IpYRleea4gq55kbZKh4LVZhLh5cQ9efS2H/C4DTU95M15AYAxU+IMA== X-Received: by 2002:adf:fdca:: with SMTP id i10mr23520500wrs.55.1618427951061; Wed, 14 Apr 2021 12:19:11 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:10 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 06/10] coresight: etm-perf: Update to activate selected configuration Date: Wed, 14 Apr 2021 20:18:59 +0100 Message-Id: <20210414191903.18349-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121912_891693_178D2A78 X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add calls to activate the selected configuration as perf starts and stops the tracing session. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +++++++++++++- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 26b4bca156aa..560baefdfed8 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -215,6 +215,10 @@ static void free_event_data(struct work_struct *work) /* Free the sink buffers, if there are any */ free_sink_buffer(event_data); + /* clear any configuration we were using */ + if (event_data->cfg_hash) + cscfg_deactivate_config(event_data->cfg_hash); + for_each_cpu(cpu, mask) { struct list_head **ppath; @@ -292,7 +296,7 @@ static bool sinks_compatible(struct coresight_device *a, static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { - u32 id; + u32 id, cfg_hash; int cpu = event->cpu; cpumask_t *mask; struct coresight_device *sink = NULL; @@ -310,6 +314,14 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* check if user wants a coresight configuration selected */ + cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); + if (cfg_hash) { + if (cscfg_activate_config(cfg_hash)) + goto err; + event_data->cfg_hash = cfg_hash; + } + mask = &event_data->mask; /* diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index ba617fe2217e..468f7799ab4f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -49,12 +49,14 @@ struct etm_filters { * @work: Handle to free allocated memory outside IRQ context. * @mask: Hold the CPU(s) this event was set for. * @snk_config: The sink configuration. + * @cfg_hash: The hash id of any coresight config selected. * @path: An array of path, each slot for one CPU. */ struct etm_event_data { struct work_struct work; cpumask_t mask; void *snk_config; + u32 cfg_hash; struct list_head * __percpu *path; }; From patchwork Wed Apr 14 19:19:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CA55C433B4 for ; Wed, 14 Apr 2021 19:24:29 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0A8C6117A for ; Wed, 14 Apr 2021 19:24:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A0A8C6117A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4ozDw+8so4qb7yGXMlErbhtgge+TLQe4AQqXlnAYvys=; b=bVSipj+djyuWRILH5F2wixdBa7 TbtJLMzsJnHNoXP0/8EdwanDmwZV9QZRaOqu3O/1W9i+WMaD3I3+RmstoyEoYm4EYFsEY2TqrM1Kl BpwWb/W+JrXrXbY2Y2eD1VWuJc5V/MiIscxHPkJeTwJ8tbjiwklx0A4fgkFYCErdigbNEkR3byx6n ZXxZfzeTUsNjrvVlnpL9bLKnBrNS9LUxjurReG0GCfKYWRTaYF50+e+E+jhZkgxSblhEXwpd9Sm1M C7CbLcm0CoxwqHbyxzPJ5fPETpqurj+DKSmjepfkSckJa0ULA44ntY6YGjRjrsUVnQ9x4LLhqE5nl Jo3TIfSw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl5V-00DXXH-T8; Wed, 14 Apr 2021 19:22:10 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2i-00DX4E-Va for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Nz7qV+7D3FU9pa/yNNMQNR3tUn+oq/KtVZSsPqWz8+g=; b=Y0ffSjwUEikz0TogiHzYHdCsMl XAqxo4l3R85eobcfzK+BKiozhDNasmJW0SrilZgmJsh/3C9T1ncUmZ4N2z62zeLAYEEiXBSvlc9L7 pKW0Ed66fXoLUIKMrJhKdo8wvFZMgXs9lqL+wAWFMPqfCltcPHQQ97+Ls9dQZZ2ZbZiQz6x8tXW1B /o64fXZ22gvBrIzepDCP94y7i4UP3oewkSKJG6h8cE8oGF7JDAbu83t3hrzDhCrCXJNb8YT59dxCl /OTQK3jJS8pdhdfUf/fxi+Q3o6W+qX5REQdHolPOYe3JXPzXKe6lWkwLxlumGERh64qUXTWrYR7Mv 7jszSiEA==; Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2f-0082rV-M6 for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:15 +0000 Received: by mail-wm1-x32e.google.com with SMTP id o21-20020a1c4d150000b029012e52898006so1468154wmh.0 for ; Wed, 14 Apr 2021 12:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nz7qV+7D3FU9pa/yNNMQNR3tUn+oq/KtVZSsPqWz8+g=; b=XMmdvMxI3iELeIyt4T+/Oyc08P0kCrPcV96Vi2MQM/e9JcU6qS4HNzV0lbUotddkT5 Dx5jr8SHoy35J+CFOwu/Ed79kTGwCsqaBTG/TRW3aeHWtLpK8WRGMRhtr/U8ylmX0Y7k T7/ENBdYMuROYgdoVg6T3kwTyDuzyXHe8QexhUudsoPSTB2DgjCajdRGnDGvNa0cvaEL JeuEj7kTo4wQ74DR45zBzvDlfjB2lwCB5IdqUdDl/3rsQIhPJY9DRkEAIff1Lgds3fib GWHvmFqTI2RiRrEI7Yq7A/CEPMBcIgxusugNGo7vntV+3D+WSqRludWNKC+qMn31PL5J cTTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nz7qV+7D3FU9pa/yNNMQNR3tUn+oq/KtVZSsPqWz8+g=; b=JmxlJbu3kaA2o9JBwHIVLpEnxtfyR/z4OTkPqxb4TmyctIWYmlFuD4GWzb7xgiKcFT iQghZAj8dvSPWQaxWwkaS8bZJIElmtnhgEA2H9FG/XY25CQoAKNPm1VKqOPBNkXHAdr3 eKWFrNz/+Jmd1NxukzPPywYBxKJh2p3Zl1LyxsVlA9frThGTxoIUaVGogCTgLnEdCuXs xsx/YYAfviMHnQUV9tHoaBUp9Ab8MbTitO2IxOZPcmlgJoHHNHo+XRU1m71pOqOqTyFD mTHoOLeBmxRv3s8g193XO/Hrs4OP9N/HXHGBHqNle08C/X6Orlc/HnlYRYzNRQveqY3H QdVQ== X-Gm-Message-State: AOAM531jucnQrtc68eHSMjm9X/wTPJG8nuujr+DGNQmB1eqanyUH1ns2 Jnknt4RQr89M4/7o/AzEzd8+0tHQ2PJuIA== X-Google-Smtp-Source: ABdhPJyNE6Py2D3En7MyINvnieFcUyJtThuziaZ23P+FVX1KkVyUZrNIhNAqJNVvzYKd7sUkP6nYAA== X-Received: by 2002:a7b:c097:: with SMTP id r23mr4365049wmh.40.1618427951819; Wed, 14 Apr 2021 12:19:11 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:11 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 07/10] coresight: etm4x: Add complex configuration handlers to etmv4 Date: Wed, 14 Apr 2021 20:19:00 +0100 Message-Id: <20210414191903.18349-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121913_755726_5E81A015 X-CRM114-Status: GOOD ( 37.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds in handlers to allow the ETMv4 to use the complex configuration support. Features and configurations can be loaded and selected in the device. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 3 +- .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++++++++++++++++++ .../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++ .../coresight/coresight-etm4x-core.c | 38 +++- .../coresight/coresight-etm4x-sysfs.c | 3 + 5 files changed, 238 insertions(+), 3 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 63ecfc3cf66d..9420d33b23ac 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \ coresight-etm3x-sysfs.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o -coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o +coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \ + coresight-etm4x-cfg.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c new file mode 100644 index 000000000000..d2ea903231b2 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2020 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#include "coresight-etm4x.h" +#include "coresight-etm4x-cfg.h" +#include "coresight-priv.h" +#include "coresight-syscfg.h" + +/* defines to associate register IDs with driver data locations */ +#define CHECKREG(cval, elem) \ + { \ + if (offset == cval) { \ + reg_csdev->driver_regval = &drvcfg->elem; \ + err = 0; \ + break; \ + } \ + } + +#define CHECKREGIDX(cval, elem, off_idx, mask) \ + { \ + if (mask == cval) { \ + reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \ + err = 0; \ + break; \ + } \ + } + +/** + * etm4_cfg_map_reg_offset - validate and map the register offset into a + * location in the driver config struct. + * + * Limits the number of registers that can be accessed and programmed in + * features, to those which are used to control the trace capture parameters. + * + * Omits or limits access to those which the driver must use exclusively. + * + * Invalid offsets will result in fail code return and feature load failure. + * + * @drvdata: driver data to map into. + * @reg: register to map. + * @offset: device offset for the register + */ +static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, + struct cscfg_regval_csdev *reg_csdev, u32 offset) +{ + int err = -EINVAL, idx; + struct etmv4_config *drvcfg = &drvdata->config; + u32 off_mask; + + if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || + ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) || + ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { + do { + CHECKREG(TRCEVENTCTL0R, eventctrl0); + CHECKREG(TRCEVENTCTL1R, eventctrl1); + CHECKREG(TRCSTALLCTLR, stall_ctrl); + CHECKREG(TRCTSCTLR, ts_ctrl); + CHECKREG(TRCSYNCPR, syncfreq); + CHECKREG(TRCCCCTLR, ccctlr); + CHECKREG(TRCBBCTLR, bb_ctrl); + CHECKREG(TRCVICTLR, vinst_ctrl); + CHECKREG(TRCVIIECTLR, viiectlr); + CHECKREG(TRCVISSCTLR, vissctlr); + CHECKREG(TRCVIPCSSCTLR, vipcssctlr); + CHECKREG(TRCSEQRSTEVR, seq_rst); + CHECKREG(TRCSEQSTR, seq_state); + CHECKREG(TRCEXTINSELR, ext_inp); + CHECKREG(TRCCIDCCTLR0, ctxid_mask0); + CHECKREG(TRCCIDCCTLR1, ctxid_mask1); + CHECKREG(TRCVMIDCCTLR0, vmid_mask0); + CHECKREG(TRCVMIDCCTLR1, vmid_mask1); + } while (0); + } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { + /* sequencer state control registers */ + idx = (offset & GENMASK(3, 0)) / 4; + if (idx < ETM_MAX_SEQ_STATES) { + reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; + err = 0; + } + } else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { + /* 32 bit, 8 off indexed register sets */ + idx = (offset & GENMASK(4, 0)) / 4; + off_mask = (offset & GENMASK(11, 5)); + do { + CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); + CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); + CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); + } while (0); + } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { + /* 64 bit, 8 off indexed register sets */ + idx = (offset & GENMASK(5, 0)) / 8; + off_mask = (offset & GENMASK(11, 6)); + do { + CHECKREGIDX(TRCCIDCVRn(0), ctxid_pid, idx, off_mask); + CHECKREGIDX(TRCVMIDCVRn(0), vmid_val, idx, off_mask); + } while (0); + } else if ((offset >= TRCRSCTLRn(2)) && + (offset <= TRCRSCTLRn((ETM_MAX_RES_SEL - 1)))) { + /* 32 bit resource selection regs, 32 off, skip fixed 0,1 */ + idx = (offset & GENMASK(6, 0)) / 4; + if (idx < ETM_MAX_RES_SEL) { + reg_csdev->driver_regval = &drvcfg->res_ctrl[idx]; + err = 0; + } + } else if ((offset >= TRCACVRn(0)) && + (offset <= TRCACATRn((ETM_MAX_SINGLE_ADDR_CMP - 1)))) { + /* 64 bit addr cmp regs, 16 off */ + idx = (offset & GENMASK(6, 0)) / 8; + off_mask = offset & GENMASK(11, 7); + do { + CHECKREGIDX(TRCACVRn(0), addr_val, idx, off_mask); + CHECKREGIDX(TRCACATRn(0), addr_acc, idx, off_mask); + } while (0); + } else if ((offset >= TRCCNTRLDVRn(0)) && + (offset <= TRCCNTVRn((ETMv4_MAX_CNTR - 1)))) { + /* 32 bit counter regs, 4 off (ETMv4_MAX_CNTR - 1) */ + idx = (offset & GENMASK(3, 0)) / 4; + off_mask = offset & GENMASK(11, 4); + do { + CHECKREGIDX(TRCCNTRLDVRn(0), cntrldvr, idx, off_mask); + CHECKREGIDX(TRCCNTCTLRn(0), cntr_ctrl, idx, off_mask); + CHECKREGIDX(TRCCNTVRn(0), cntr_val, idx, off_mask); + } while (0); + } + return err; +} + +/** + * etm4_cfg_load_feature - load a feature into a device instance. + * + * @csdev: An ETMv4 CoreSight device. + * @feat: The feature to be loaded. + * + * The function will load a feature instance into the device, checking that + * the register definitions are valid for the device. + * + * Parameter and register definitions will be converted into internal + * structures that are used to set the values in the driver when the + * feature is enabled for the device. + * + * The feature spinlock pointer is initialised to the same spinlock + * that the driver uses to protect the internal register values. + */ +static int etm4_cfg_load_feature(struct coresight_device *csdev, + struct cscfg_feature_csdev *feat_csdev) +{ + struct device *dev = csdev->dev.parent; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); + const struct cscfg_feature_desc *feat_desc = feat_csdev->feat_desc; + u32 offset; + int i = 0, err = 0; + + /* + * essential we set the device spinlock - this is used in the generic + * programming routines when copying values into the drvdata structures + * via the pointers setup in etm4_cfg_map_reg_offset(). + */ + feat_csdev->drv_spinlock = &drvdata->spinlock; + + /* process the register descriptions */ + for (i = 0; i < feat_csdev->nr_regs && !err; i++) { + offset = feat_desc->regs_desc[i].offset; + err = etm4_cfg_map_reg_offset(drvdata, &feat_csdev->regs_csdev[i], offset); + } + return err; +} + +/* match information when loading configurations */ +#define CS_CFG_ETM4_MATCH_FLAGS (CS_CFG_MATCH_CLASS_SRC_ALL | \ + CS_CFG_MATCH_CLASS_SRC_ETM4) + +int etm4_cscfg_register(struct coresight_device *csdev) +{ + struct cscfg_csdev_feat_ops ops; + + ops.load_feat = &etm4_cfg_load_feature; + + return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); +} diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.h b/drivers/hwtracing/coresight/coresight-etm4x-cfg.h new file mode 100644 index 000000000000..a204ad9a4792 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CORESIGHT_ETM4X_CFG_H +#define _CORESIGHT_ETM4X_CFG_H + +#include "coresight-config.h" +#include "coresight-etm4x.h" + +/* ETMv4 specific config functions */ +int etm4_cscfg_register(struct coresight_device *csdev); + +#endif /* CORESIGHT_ETM4X_CFG_H */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index efb84ced83dd..94f10910d20d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -39,6 +39,8 @@ #include "coresight-etm4x.h" #include "coresight-etm-perf.h" +#include "coresight-etm4x-cfg.h" +#include "coresight-syscfg.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -561,12 +563,15 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) return ret; } -static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, +static int etm4_parse_event_config(struct coresight_device *csdev, struct perf_event *event) { int ret = 0; + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etmv4_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; + unsigned long cfg_hash; + int preset; if (!attr) { ret = -EINVAL; @@ -637,6 +642,20 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, /* bit[12], Return stack enable bit */ config->cfg |= BIT(12); + /* + * Set any selected configuration and preset. + * + * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset) + * in the perf attributes defined in coresight-etm-perf.c. + * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config. + * A zero configid means no configuration active, preset = 0 means no preset selected. + */ + if (attr->config2 & GENMASK_ULL(63, 32)) { + cfg_hash = (u32)(attr->config2 >> 32); + preset = attr->config & 0xF; + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); + } + out: return ret; } @@ -653,7 +672,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, } /* Configure the tracer based on the session's specifics */ - ret = etm4_parse_event_config(drvdata, event); + ret = etm4_parse_event_config(csdev, event); if (ret) goto out; /* And enable it */ @@ -799,11 +818,18 @@ static int etm4_disable_perf(struct coresight_device *csdev, u32 control; struct etm_filters *filters = event->hw.addr_filters; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct perf_event_attr *attr = &event->attr; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; etm4_disable_hw(drvdata); + /* + * The config_id occupies bits 63:32 of the config2 perf event attr + * field. If this is non-zero then we will have enabled a config. + */ + if (attr->config2 & GENMASK_ULL(63, 32)) + cscfg_csdev_disable_active_config(csdev); /* * Check if the start/stop logic was active when the unit was stopped. @@ -1944,6 +1970,13 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return ret; } + /* register with config infrastructure & load any current features */ + ret = etm4_cscfg_register(drvdata->csdev); + if (ret) { + coresight_unregister(drvdata->csdev); + return ret; + } + etmdrvdata[drvdata->cpu] = drvdata; dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n", @@ -2030,6 +2063,7 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) cpus_read_unlock(); + cscfg_unregister_csdev(drvdata->csdev); coresight_unregister(drvdata->csdev); return 0; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 007bad9e7ad8..a0640fa5c55b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -9,6 +9,7 @@ #include #include "coresight-etm4x.h" #include "coresight-priv.h" +#include "coresight-syscfg.h" static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude) { @@ -269,6 +270,8 @@ static ssize_t reset_store(struct device *dev, spin_unlock(&drvdata->spinlock); + cscfg_csdev_reset_feats(to_coresight_device(dev)); + return size; } static DEVICE_ATTR_WO(reset); From patchwork Wed Apr 14 19:19:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBCFEC433B4 for ; Wed, 14 Apr 2021 19:24:38 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D7596113B for ; Wed, 14 Apr 2021 19:24:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D7596113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RQtieI47FFGGJPryAC/aCAjofwSh6ZZF+HNRV/uSpNc=; b=A9TyKfzsWYJGcAJjBFbZ6blRZH y3SdiUDs5AJ8JALfY5Vp949KX6wmDyUtl+uW8f0ouzEuvAQ/EE7tGWVWmKszNEUS3GKpS4ZwX4Iwk iJIGbU0xLhTANO1vUdgWGq0W6EO6HfpkhYMN8ngcp4v/mVIt6gUsgQHtFl1iNSI2VtPc/Vycyk4jF f/Eles4IRT4P0sO10etMBoY/yG+Epnnkn4H62X1AbvdckwVqm0kGw2PE0ubK5IV6y+y4GFVcpRkwa m2+lVVNlM7Ex4CfIhRdtUSPI8XCUJLxo2ih23pDmcVfQKpWWwGnT9hs1K+pWpkPS38wng5G68Kr0j JsB9HP+w==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl5u-00DXep-PR; Wed, 14 Apr 2021 19:22:35 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2j-00DX4L-FY for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=CHjjd48PiwJLvff48z0RX7R6EM8TBwQvKJPGwesMVag=; b=ARc8oSVVbLCvKFQadl0+1kQQ6A p6UgSOgS666cJwfuVKjX8un/t6lEGHDImhlmu7cA4LedoFC5llESW5rKYBTwLFV1rwGo+maVuvNVp GFfEohuvZQoeVVneBmUEcV48NfHT44W6CbKmXsjfL62f5rRD0c5o/9eKjwNcHHHwKg2f7IYn2aAEq GdtqpT7wiyx8zuut809PtJhG8XAtIeEW1xDTiglo1B3KhdIiKCMAB6PTlzi4+o8lsfepDrUcZrD4G RTg/YRUrtD3zQZ1hQJmJQPVzRjo0Ips59Uohz2ytsuTy8oqO+GuhnX7q+tVrLKu6vbvUs6AmliW0D 1xFFa0Rg==; Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2g-0082s0-Cv for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:16 +0000 Received: by mail-wm1-x330.google.com with SMTP id y204so9803734wmg.2 for ; Wed, 14 Apr 2021 12:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CHjjd48PiwJLvff48z0RX7R6EM8TBwQvKJPGwesMVag=; b=k1ipE0Bp5uFD3wV2ITFoV57FvVElThDwnxOP2kAEh+oBfaejMT+JTG5y/vyrggIf8b ghgu0g+aBzTXL/hMtvDtHrE9+yA/Qn5s6vfWLR7ZggIKahJmK3D9+9x4VeUA3zAK7JaX 61K14z6mJX8Qy/fzkJ2ro/Hzo25sYYXUEjh8tjHIdXifae7GJREsXaQF51kyEGFJg6+U yYNevmJdSEnEU+Rx+6C5/kbJYodxOHVPaYqxnzJVy1OAvGcUzZGnjG7VEwPWIw5IjBXF tG1sHczgPJQ+ECUr9WBDvNF4KmxVg/+utAZ2YXOJ+f+UnJacDo/hZ5rdYVJIjuDv4+IM IESw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CHjjd48PiwJLvff48z0RX7R6EM8TBwQvKJPGwesMVag=; b=jFbkkWMmSXks0etQGuLXlBNM0Y9G6df3Q2jM/YeTV0UNQQ8TI1lL5HRmldGAQKFRS5 MU6MDAwXxCyIXEVd066i9X1OY0YIRwP7md1WwC4cQmns+pLYjHWdt95m50uiGs/ROWzR zTz8qff1/J6oevy6Eqj1YNWBNy43MyAcY3G6zAm5W+J4s6X9L7mVEP8Db4H5nbpJ/XOg 2I09/V7XN5mg1Jx7ULPYUsUGiA8waPS+gxCuN+KOxC2/TtNP8BhbTBWuBHj0atU9dkPL LMOvtxy/21ewGQX1BJSYyKVjTPT7cmFPaUaxzgIOSAUujyVyCAQL+aCfOp7NbksXydLQ nlVg== X-Gm-Message-State: AOAM530MxE0tLYW9sNckHgpUCwRLru0qXi/ybLtBZ7Sg/GV9ajy0ZJVC c7gD4Q0kfhwZhjMjYOx7IA/EqVP2Ziol2g== X-Google-Smtp-Source: ABdhPJzEYYVQ9ZFYCIE6Qdp+KNuOGdpkw6+13CWjcSD3HNDG+pARBKVs/2Ir21X+ltmefvlgI3Hdcw== X-Received: by 2002:a05:600c:24c:: with SMTP id 12mr4556865wmj.185.1618427952595; Wed, 14 Apr 2021 12:19:12 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:12 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 08/10] coresight: config: Add preloaded configurations Date: Wed, 14 Apr 2021 20:19:01 +0100 Message-Id: <20210414191903.18349-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121914_464200_94E89E95 X-CRM114-Status: GOOD ( 25.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Preload set of configurations. This patch creates a small set of preloaded configurations and features that are available immediately after coresight has been initialised. The current set provides a strobing feature for ETMv4, that creates a periodic sampling of trace by switching trace generation on and off using counters in the ETM. A configuration called "autofdo" is also provided that uses the 'strobing' feature and provides a couple of preset values, selectable on the perf command line. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 3 +- .../hwtracing/coresight/coresight-cfg-afdo.c | 153 ++++++++++++++++++ .../coresight/coresight-cfg-preload.c | 31 ++++ .../coresight/coresight-cfg-preload.h | 13 ++ .../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++ .../hwtracing/coresight/coresight-syscfg.c | 9 ++ .../hwtracing/coresight/coresight-syscfg.h | 1 + 7 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 9420d33b23ac..ad44f0fe3069 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -4,7 +4,8 @@ # obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ - coresight-sysfs.o coresight-syscfg.o coresight-config.o + coresight-sysfs.o coresight-syscfg.o coresight-config.o \ + coresight-cfg-preload.o coresight-cfg-afdo.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c b/drivers/hwtracing/coresight/coresight-cfg-afdo.c new file mode 100644 index 000000000000..84b31184252b --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2020 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#include "coresight-config.h" + +/* ETMv4 includes and features */ +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) +#include "coresight-etm4x-cfg.h" + +/* preload configurations and features */ + +/* preload in features for ETMv4 */ + +/* strobe feature */ +static struct cscfg_parameter_desc strobe_params[] = { + { + .name = "window", + .value = 5000, + }, + { + .name = "period", + .value = 10000, + }, +}; + +static struct cscfg_regval_desc strobe_regs[] = { + /* resource selectors */ + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCRSCTLRn(2), + .hw_info = ETM4_CFG_RES_SEL, + .val32 = 0x20001, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCRSCTLRn(3), + .hw_info = ETM4_CFG_RES_SEQ, + .val32 = 0x20002, + }, + /* strobe window counter 0 - reload from param 0 */ + { + .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, + .offset = TRCCNTVRn(0), + .hw_info = ETM4_CFG_RES_CTR, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, + .offset = TRCCNTRLDVRn(0), + .hw_info = ETM4_CFG_RES_CTR, + .val32 = 0, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCCNTCTLRn(0), + .hw_info = ETM4_CFG_RES_CTR, + .val32 = 0x10001, + }, + /* strobe period counter 1 - reload from param 1 */ + { + .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, + .offset = TRCCNTVRn(1), + .hw_info = ETM4_CFG_RES_CTR, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, + .offset = TRCCNTRLDVRn(1), + .hw_info = ETM4_CFG_RES_CTR, + .val32 = 1, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCCNTCTLRn(1), + .hw_info = ETM4_CFG_RES_CTR, + .val32 = 0x8102, + }, + /* sequencer */ + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCSEQEVRn(0), + .hw_info = ETM4_CFG_RES_SEQ, + .val32 = 0x0081, + }, + { + .type = CS_CFG_REG_TYPE_RESOURCE, + .offset = TRCSEQEVRn(1), + .hw_info = ETM4_CFG_RES_SEQ, + .val32 = 0x0000, + }, + /* view-inst */ + { + .type = CS_CFG_REG_TYPE_STD | CS_CFG_REG_TYPE_VAL_MASK, + .offset = TRCVICTLR, + .val32 = 0x0003, + .mask32 = 0x0003, + }, + /* end of regs */ +}; + +struct cscfg_feature_desc strobe_etm4x = { + .name = "strobing", + .description = "Generate periodic trace capture windows.\n" + "parameter \'window\': a number of CPU cycles (W)\n" + "parameter \'period\': trace enabled for W cycles every period x W cycles\n", + .match_flags = CS_CFG_MATCH_CLASS_SRC_ETM4, + .nr_params = ARRAY_SIZE(strobe_params), + .params_desc = strobe_params, + .nr_regs = ARRAY_SIZE(strobe_regs), + .regs_desc = strobe_regs, +}; + +/* create an autofdo configuration */ + +/* we will provide 9 sets of preset parameter values */ +#define AFDO_NR_PRESETS 9 +/* the total number of parameters in used features */ +#define AFDO_NR_PARAMS ARRAY_SIZE(strobe_params) + +static const char *afdo_ref_names[] = { + "strobing", +}; + +/* + * set of presets leaves strobing window constant while varying period to allow + * experimentation with mark / space ratios for various workloads + */ +static u64 afdo_presets[AFDO_NR_PRESETS][AFDO_NR_PARAMS] = { + { 5000, 2 }, + { 5000, 4 }, + { 5000, 8 }, + { 5000, 16 }, + { 5000, 64 }, + { 5000, 128 }, + { 5000, 512 }, + { 5000, 1024 }, + { 5000, 4096 }, +}; + +struct cscfg_config_desc afdo_etm4x = { + .name = "autofdo", + .description = "Setup ETMs with strobing for autofdo\n" + "Supplied presets allow experimentation with mark-space ratio for various loads\n", + .nr_feat_refs = ARRAY_SIZE(afdo_ref_names), + .feat_ref_names = afdo_ref_names, + .nr_presets = AFDO_NR_PRESETS, + .nr_total_params = AFDO_NR_PARAMS, + .presets = &afdo_presets[0][0], +}; + +/* end of ETM4x configurations */ +#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */ diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/hwtracing/coresight/coresight-cfg-preload.c new file mode 100644 index 000000000000..751af3710d56 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2020 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#include "coresight-cfg-preload.h" +#include "coresight-config.h" +#include "coresight-syscfg.h" + +/* Basic features and configurations pre-loaded on initialisation */ + +static struct cscfg_feature_desc *preload_feats[] = { +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) + &strobe_etm4x, +#endif + NULL +}; + +static struct cscfg_config_desc *preload_cfgs[] = { +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) + &afdo_etm4x, +#endif + NULL +}; + +/* preload called on initialisation */ +int cscfg_preload(void) +{ + return cscfg_load_config_sets(preload_cfgs, preload_feats); +} diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/hwtracing/coresight/coresight-cfg-preload.h new file mode 100644 index 000000000000..21299e175477 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2020 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +/* declare preloaded configurations and features */ + +/* from coresight-cfg-afdo.c - etm 4x features */ +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) +extern struct cscfg_feature_desc strobe_etm4x; +extern struct cscfg_config_desc afdo_etm4x; +#endif diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.h b/drivers/hwtracing/coresight/coresight-etm4x-cfg.h index a204ad9a4792..32dab34c1dac 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.h +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.h @@ -9,6 +9,21 @@ #include "coresight-config.h" #include "coresight-etm4x.h" +/* ETMv4 specific config defines */ + +/* resource IDs */ + +#define ETM4_CFG_RES_CTR 0x001 +#define ETM4_CFG_RES_CMP 0x002 +#define ETM4_CFG_RES_CMP_PAIR0 0x003 +#define ETM4_CFG_RES_CMP_PAIR1 0x004 +#define ETM4_CFG_RES_SEL 0x005 +#define ETM4_CFG_RES_SEL_PAIR0 0x006 +#define ETM4_CFG_RES_SEL_PAIR1 0x007 +#define ETM4_CFG_RES_SEQ 0x008 +#define ETM4_CFG_RES_TS 0x009 +#define ETM4_CFG_RES_MASK 0x00F + /* ETMv4 specific config functions */ int etm4_cscfg_register(struct coresight_device *csdev); diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index b234e45c153f..41f742190639 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -709,8 +709,17 @@ int __init cscfg_init(void) INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); atomic_set(&cscfg_mgr->sys_active_cnt, 0); + /* preload built-in configurations */ + err = cscfg_preload(); + if (err) + goto exit_err; + dev_info(cscfg_device(), "CoreSight Configuration manager initialised"); return 0; + +exit_err: + cscfg_clear_device(); + return err; } void cscfg_exit(void) diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index a52775890670..7bb8c8e497ba 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -56,6 +56,7 @@ struct cscfg_registered_csdev { /* internal core operations for cscfg */ int __init cscfg_init(void); void cscfg_exit(void); +int cscfg_preload(void); /* syscfg manager external API */ int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs, From patchwork Wed Apr 14 19:19:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D74B7C433B4 for ; Wed, 14 Apr 2021 19:25:11 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 351AA6113B for ; Wed, 14 Apr 2021 19:25:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 351AA6113B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SzmFTMYkIasw90H3cTFUh1zWasTDdCH5O6WnACNtODc=; b=PN3qu9U1t7PLnQ0dsffDlL3F8r JUUnOdmv4IjDkInGc2w8rGfx3xAaEO9hwl5ZJgPwZdD8aixXz31GRnP7L4vxK34+aKLoXMSL646am JOUtwFKO1zwEnpU1/cbQuC3aBC024dg2fbJQeMUh8SFX0HhlB72daXEgoLRzeMokzN0nqCDoIwQh2 aQ5Q2kcp3nV4u1xeuQjZnrsgx/3WGdxeYJX7c5V3YI+gWAuq4haI6QQpmt+6kgmADa0H5ZNZYOQSm j4VkhI/zdGfwVHYwQQsDDs01qOTnOa6u6Ggt/Iwo9o+gJ4wKCHkhgUumyyAYTsP53LtfxjjMVGPS9 OuVNJn9g==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl6J-00DXms-Mc; Wed, 14 Apr 2021 19:23:00 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2l-00DX4l-1S for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:19 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=2fs9yzgZefmIkPvtPeZDfAhTO9TS4pRwu9mbuRA3gso=; b=L1Vq81msY7E/DC2gytx6Vj0r/q pNgDYu+XdRbPW9Kh8NowqWO2lOpA+10RIHWkiiysUuMihnkEK2fuFWxxwLYGsujRXFDZ8UTBG8a1b EDwnheGIMgqP8M+S9f0OUBIIIBdimtLnNLIj6Fn9qxmeFJNPCBBjYHTNrAqt27MBDG92ny8hWYGiE 4XZi3ER2OtxHQyuNncDXdj+BjMPfDwge6dCDaYBA0QAJXb6acdcvLl2bgQoGhCQuLkUK4ZJx5NYj3 GaJ/LsDo0hfB+dMtDK7nnX7vprhvJPeqGMEW2tVJ70kR6iXmi/atdebTo5HvSg4JZz4xpkzasKMcb F7+lSKMg==; Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2h-0082sK-6T for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 Received: by mail-wm1-x331.google.com with SMTP id y204so9803744wmg.2 for ; Wed, 14 Apr 2021 12:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2fs9yzgZefmIkPvtPeZDfAhTO9TS4pRwu9mbuRA3gso=; b=xskKtKVs1VVBGxZ1M+P5OObpsddAfevle6FkX7M++GruAtxbUF1WtPSHXGSO9m6XWv GWgk93I2jrmayP8/utJ/lrB30GnT1yGTnO6o4y5gZMwZFsgcIUpQNlE/1ncHcONu4oAv c4JbIor6op5e9kanjPTq1ybBDIPX9g3Zntdt+VvLExPIZpNnG7OxhocEUzGsE6s4I+bE 6D6BvUJvjwJNE4mWoOGGICf7hA15uwY15xVlbhClhlS6zM1fp08oO6DDC05S+AM9BpiR vGlSwiXl1iNhesXxHFbY2LX3vAgnBu0Dl8Xk1ZBxWoFBvcEpdNw7FRbDmKBYx9TCU4JB Ligw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2fs9yzgZefmIkPvtPeZDfAhTO9TS4pRwu9mbuRA3gso=; b=QLenafi1TkN/ZGT84UHkBohmCIgo6EqFv735cuwV5qW5mWF1OfFQRKAZPM1Pd+3pKD +wI1AqlDpvrHjn51jQBz1KGg62jJLxAJQ7hdc8NDgrV1fdCr/r78kEfjTPrVcs3E527d vfwmK0uGx/7zkkpVfeeV8CEA5BEC5aQ0bZjJYpgmcwVu8+EDC59bq7XdlaRw4poAXcuU t9H9q5TxcCFLiD8kBBmjthRH3Ku0HlJxbHrRYaFgnVETWOnhABERoKSw87B8Q5bebDnF Hdmv0a1UaNcnuAkDypI3YY7ZYUMPUryhh30cwUA7HfVqB+EnYGa+6nnvuAURdFgLSQ8E Qjew== X-Gm-Message-State: AOAM5316ip5u1TCMeWexjfzWLyiJBpfQnel7j3F4RfVCxVSBacdM+C2C YMAEhIY6Pb/NrujmVylr6dwMuLrG2wefKA== X-Google-Smtp-Source: ABdhPJx2AaOdj5WpfZvbJav6Jv+ssiRUBQrj9NzjIQ1yDkRH36Kdxe9lOseZXKN04Q08XYfVT3PjmQ== X-Received: by 2002:a7b:c394:: with SMTP id s20mr4496532wmj.4.1618427953346; Wed, 14 Apr 2021 12:19:13 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:13 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 09/10] coresight: syscfg: Add initial configfs support Date: Wed, 14 Apr 2021 20:19:02 +0100 Message-Id: <20210414191903.18349-10-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121915_274449_A025CC35 X-CRM114-Status: GOOD ( 25.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds configfs subsystem and attributes to the configuration manager to enable the listing of loaded configurations and features. The default values of feature parameters can be accessed and altered from these attributes to affect all installed devices using the feature. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 3 +- .../coresight/coresight-syscfg-configfs.c | 396 ++++++++++++++++++ .../coresight/coresight-syscfg-configfs.h | 45 ++ .../hwtracing/coresight/coresight-syscfg.c | 76 ++++ .../hwtracing/coresight/coresight-syscfg.h | 7 + 5 files changed, 526 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index ad44f0fe3069..b6c4a48140ec 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -5,7 +5,8 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ - coresight-cfg-preload.o coresight-cfg-afdo.o + coresight-cfg-preload.o coresight-cfg-afdo.o \ + coresight-syscfg-configfs.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c new file mode 100644 index 000000000000..c547816b9000 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Linaro Limited, All rights reserved. + * Author: Mike Leach + */ + +#include + +#include "coresight-syscfg-configfs.h" + +/* create a default ci_type. */ +static inline struct config_item_type *cscfg_create_ci_type(void) +{ + struct config_item_type *ci_type; + + ci_type = devm_kzalloc(cscfg_device(), sizeof(*ci_type), GFP_KERNEL); + if (ci_type) + ci_type->ct_owner = THIS_MODULE; + + return ci_type; +} + +/* configurations sub-group */ + +/* attributes for the config view group */ +static ssize_t cscfg_cfg_description_show(struct config_item *item, char *page) +{ + struct cscfg_fs_config *fs_config = container_of(to_config_group(item), + struct cscfg_fs_config, group); + + return scnprintf(page, PAGE_SIZE, "%s", fs_config->config_desc->description); +} +CONFIGFS_ATTR_RO(cscfg_cfg_, description); + +static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char *page) +{ + struct cscfg_fs_config *fs_config = container_of(to_config_group(item), + struct cscfg_fs_config, group); + const struct cscfg_config_desc *config_desc = fs_config->config_desc; + ssize_t ch_used = 0; + int i; + + for (i = 0; i < config_desc->nr_feat_refs; i++) + ch_used += scnprintf(page + ch_used, PAGE_SIZE - ch_used, + "%s\n", config_desc->feat_ref_names[i]); + return ch_used; +} +CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs); + +/* list preset values in order of features and params */ +static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page) +{ + const struct cscfg_feature_desc *feat_desc; + const struct cscfg_config_desc *config_desc; + struct cscfg_fs_preset *fs_preset; + int i, j, val_idx, preset_idx; + ssize_t used = 0; + + fs_preset = container_of(to_config_group(item), struct cscfg_fs_preset, group); + config_desc = fs_preset->config_desc; + + if (!config_desc->nr_presets) + return 0; + + preset_idx = fs_preset->preset_num - 1; + + /* start index on the correct array line */ + val_idx = config_desc->nr_total_params * preset_idx; + + /* + * A set of presets is the sum of all params in used features, + * in order of declaration of features and params in the features + */ + for (i = 0; i < config_desc->nr_feat_refs; i++) { + feat_desc = cscfg_get_named_feat_desc(config_desc->feat_ref_names[i]); + for (j = 0; j < feat_desc->nr_params; j++) { + used += scnprintf(page + used, PAGE_SIZE - used, + "%s.%s = 0x%llx ", + feat_desc->name, + feat_desc->params_desc[j].name, + config_desc->presets[val_idx++]); + } + } + used += scnprintf(page + used, PAGE_SIZE - used, "\n"); + + return used; +} +CONFIGFS_ATTR_RO(cscfg_cfg_, values); + +static struct configfs_attribute *cscfg_config_view_attrs[] = { + &cscfg_cfg_attr_description, + &cscfg_cfg_attr_feature_refs, + NULL, +}; + +static struct config_item_type cscfg_config_view_type = { + .ct_owner = THIS_MODULE, + .ct_attrs = cscfg_config_view_attrs, +}; + +static struct configfs_attribute *cscfg_config_preset_attrs[] = { + &cscfg_cfg_attr_values, + NULL, +}; + +static struct config_item_type cscfg_config_preset_type = { + .ct_owner = THIS_MODULE, + .ct_attrs = cscfg_config_preset_attrs, +}; + +static int cscfg_add_preset_groups(struct cscfg_fs_config *cfg_view) +{ + int preset_num; + struct cscfg_fs_preset *cfg_fs_preset; + struct cscfg_config_desc *config_desc = cfg_view->config_desc; + char name[CONFIGFS_ITEM_NAME_LEN]; + + if (!config_desc->nr_presets) + return 0; + + for (preset_num = 1; preset_num <= config_desc->nr_presets; preset_num++) { + cfg_fs_preset = devm_kzalloc(cscfg_device(), + sizeof(struct cscfg_fs_preset), GFP_KERNEL); + + if (!cfg_fs_preset) + return -ENOMEM; + + snprintf(name, CONFIGFS_ITEM_NAME_LEN, "preset%d", preset_num); + cfg_fs_preset->preset_num = preset_num; + cfg_fs_preset->config_desc = cfg_view->config_desc; + config_group_init_type_name(&cfg_fs_preset->group, name, + &cscfg_config_preset_type); + configfs_add_default_group(&cfg_fs_preset->group, &cfg_view->group); + } + return 0; +} + +static struct config_group *cscfg_create_config_group(struct cscfg_config_desc *config_desc) +{ + struct cscfg_fs_config *cfg_view; + struct device *dev = cscfg_device(); + int err; + + if (!dev) + return ERR_PTR(-EINVAL); + + cfg_view = devm_kzalloc(dev, sizeof(struct cscfg_fs_config), GFP_KERNEL); + if (!cfg_view) + return ERR_PTR(-ENOMEM); + + cfg_view->config_desc = config_desc; + config_group_init_type_name(&cfg_view->group, config_desc->name, &cscfg_config_view_type); + + /* add in a preset dir for each preset */ + err = cscfg_add_preset_groups(cfg_view); + if (err) + return ERR_PTR(err); + + return &cfg_view->group; +} + +/* attributes for features view */ + +static ssize_t cscfg_feat_description_show(struct config_item *item, char *page) +{ + struct cscfg_fs_feature *fs_feat = container_of(to_config_group(item), + struct cscfg_fs_feature, group); + + return scnprintf(page, PAGE_SIZE, "%s", fs_feat->feat_desc->description); +} +CONFIGFS_ATTR_RO(cscfg_feat_, description); + +static ssize_t cscfg_feat_matches_show(struct config_item *item, char *page) +{ + struct cscfg_fs_feature *fs_feat = container_of(to_config_group(item), + struct cscfg_fs_feature, group); + u32 match_flags = fs_feat->feat_desc->match_flags; + int used = 0; + + if (match_flags & CS_CFG_MATCH_CLASS_SRC_ALL) + used = scnprintf(page, PAGE_SIZE, "SRC_ALL "); + + if (match_flags & CS_CFG_MATCH_CLASS_SRC_ETM4) + used += scnprintf(page + used, PAGE_SIZE - used, "SRC_ETMV4 "); + + used += scnprintf(page + used, PAGE_SIZE - used, "\n"); + return used; +} +CONFIGFS_ATTR_RO(cscfg_feat_, matches); + +static ssize_t cscfg_feat_nr_params_show(struct config_item *item, char *page) +{ + struct cscfg_fs_feature *fs_feat = container_of(to_config_group(item), + struct cscfg_fs_feature, group); + + return scnprintf(page, PAGE_SIZE, "%d\n", fs_feat->feat_desc->nr_params); +} +CONFIGFS_ATTR_RO(cscfg_feat_, nr_params); + +/* base feature desc attrib structures */ +static struct configfs_attribute *cscfg_feature_view_attrs[] = { + &cscfg_feat_attr_description, + &cscfg_feat_attr_matches, + &cscfg_feat_attr_nr_params, + NULL, +}; + +static struct config_item_type cscfg_feature_view_type = { + .ct_owner = THIS_MODULE, + .ct_attrs = cscfg_feature_view_attrs, +}; + +static ssize_t cscfg_param_value_show(struct config_item *item, char *page) +{ + struct cscfg_fs_param *param_item = container_of(to_config_group(item), + struct cscfg_fs_param, group); + u64 value = param_item->feat_desc->params_desc[param_item->param_idx].value; + + return scnprintf(page, PAGE_SIZE, "0x%llx\n", value); +} + +static ssize_t cscfg_param_value_store(struct config_item *item, + const char *page, size_t size) +{ + struct cscfg_fs_param *param_item = container_of(to_config_group(item), + struct cscfg_fs_param, group); + struct cscfg_feature_desc *feat_desc = param_item->feat_desc; + int param_idx = param_item->param_idx; + u64 value; + int err; + + err = kstrtoull(page, 0, &value); + if (!err) + err = cscfg_update_feat_param_val(feat_desc, param_idx, value); + + return err ? err : size; +} +CONFIGFS_ATTR(cscfg_param_, value); + +static struct configfs_attribute *cscfg_param_view_attrs[] = { + &cscfg_param_attr_value, + NULL, +}; + +static struct config_item_type cscfg_param_view_type = { + .ct_owner = THIS_MODULE, + .ct_attrs = cscfg_param_view_attrs, +}; + +/* + * configfs has far less functionality provided to add attributes dynamically than sysfs, + * and the show and store fns pass the enclosing config_item so the actual attribute cannot + * be determined. Therefore we add each item as a group directory, with a value attribute. + */ +static int cscfg_create_params_group_items(struct cscfg_feature_desc *feat_desc, + struct config_group *params_group) +{ + struct device *dev = cscfg_device(); + struct cscfg_fs_param *param_item; + int i; + + /* parameter items - as groups with default_value attribute */ + for (i = 0; i < feat_desc->nr_params; i++) { + param_item = devm_kzalloc(dev, sizeof(struct cscfg_fs_param), GFP_KERNEL); + if (!param_item) + return -ENOMEM; + param_item->feat_desc = feat_desc; + param_item->param_idx = i; + config_group_init_type_name(¶m_item->group, + feat_desc->params_desc[i].name, + &cscfg_param_view_type); + configfs_add_default_group(¶m_item->group, params_group); + } + return 0; +} + +static struct config_group *cscfg_create_feature_group(struct cscfg_feature_desc *feat_desc) +{ + struct cscfg_fs_feature *feat_view; + struct config_item_type *params_group_type; + struct config_group *params_group = NULL; + struct device *dev = cscfg_device(); + int item_err; + + if (!dev) + return ERR_PTR(-EINVAL); + + feat_view = devm_kzalloc(dev, sizeof(struct cscfg_fs_feature), GFP_KERNEL); + if (!feat_view) + return ERR_PTR(-ENOMEM); + + if (feat_desc->nr_params) { + params_group = devm_kzalloc(dev, sizeof(struct config_group), GFP_KERNEL); + if (!params_group) + return ERR_PTR(-ENOMEM); + + params_group_type = cscfg_create_ci_type(); + if (!params_group_type) + return ERR_PTR(-ENOMEM); + } + + feat_view->feat_desc = feat_desc; + config_group_init_type_name(&feat_view->group, + feat_desc->name, + &cscfg_feature_view_type); + if (params_group) { + config_group_init_type_name(params_group, "params", params_group_type); + configfs_add_default_group(params_group, &feat_view->group); + item_err = cscfg_create_params_group_items(feat_desc, params_group); + if (item_err) + return ERR_PTR(item_err); + } + return &feat_view->group; +} + +static struct config_item_type cscfg_configs_type = { + .ct_owner = THIS_MODULE, +}; + +static struct config_group cscfg_configs_grp = { + .cg_item = { + .ci_namebuf = "configurations", + .ci_type = &cscfg_configs_type, + }, +}; + +/* add configuration to configurations group */ +int cscfg_configfs_add_config(struct cscfg_config_desc *config_desc) +{ + struct config_group *new_group; + int err; + + new_group = cscfg_create_config_group(config_desc); + if (IS_ERR(new_group)) + return PTR_ERR(new_group); + err = configfs_register_group(&cscfg_configs_grp, new_group); + return err; +} + +static struct config_item_type cscfg_features_type = { + .ct_owner = THIS_MODULE, +}; + +static struct config_group cscfg_features_grp = { + .cg_item = { + .ci_namebuf = "features", + .ci_type = &cscfg_features_type, + }, +}; + +/* add feature to features group */ +int cscfg_configfs_add_feature(struct cscfg_feature_desc *feat_desc) +{ + struct config_group *new_group; + int err; + + new_group = cscfg_create_feature_group(feat_desc); + if (IS_ERR(new_group)) + return PTR_ERR(new_group); + err = configfs_register_group(&cscfg_features_grp, new_group); + return err; +} + +int cscfg_configfs_init(struct cscfg_manager *cscfg_mgr) +{ + struct configfs_subsystem *subsys; + struct config_item_type *ci_type; + + if (!cscfg_mgr) + return -EINVAL; + + ci_type = cscfg_create_ci_type(); + if (!ci_type) + return -ENOMEM; + + subsys = &cscfg_mgr->cfgfs_subsys; + config_item_set_name(&subsys->su_group.cg_item, CSCFG_FS_SUBSYS_NAME); + subsys->su_group.cg_item.ci_type = ci_type; + + config_group_init(&subsys->su_group); + mutex_init(&subsys->su_mutex); + + /* Add default groups to subsystem */ + config_group_init(&cscfg_configs_grp); + configfs_add_default_group(&cscfg_configs_grp, &subsys->su_group); + + config_group_init(&cscfg_features_grp); + configfs_add_default_group(&cscfg_features_grp, &subsys->su_group); + + return configfs_register_subsystem(subsys); +} + +void cscfg_configfs_release(struct cscfg_manager *cscfg_mgr) +{ + configfs_unregister_subsystem(&cscfg_mgr->cfgfs_subsys); +} diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.h b/drivers/hwtracing/coresight/coresight-syscfg-configfs.h new file mode 100644 index 000000000000..7d6ffe35ca4c --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Coresight system configuration driver - support for configfs. + */ + +#ifndef CORESIGHT_SYSCFG_CONFIGFS_H +#define CORESIGHT_SYSCFG_CONFIGFS_H + +#include +#include "coresight-syscfg.h" + +#define CSCFG_FS_SUBSYS_NAME "cs-syscfg" + +/* container for configuration view */ +struct cscfg_fs_config { + struct cscfg_config_desc *config_desc; + struct config_group group; +}; + +/* container for feature view */ +struct cscfg_fs_feature { + struct cscfg_feature_desc *feat_desc; + struct config_group group; +}; + +/* container for parameter view */ +struct cscfg_fs_param { + int param_idx; + struct cscfg_feature_desc *feat_desc; + struct config_group group; +}; + +/* container for preset view */ +struct cscfg_fs_preset { + int preset_num; + struct cscfg_config_desc *config_desc; + struct config_group group; +}; + +int cscfg_configfs_init(struct cscfg_manager *cscfg_mgr); +void cscfg_configfs_release(struct cscfg_manager *cscfg_mgr); +int cscfg_configfs_add_config(struct cscfg_config_desc *config_desc); +int cscfg_configfs_add_feature(struct cscfg_feature_desc *feat_desc); + +#endif /* CORESIGHT_SYSCFG_CONFIGFS_H */ diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c index 41f742190639..180202402eb5 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.c +++ b/drivers/hwtracing/coresight/coresight-syscfg.c @@ -9,6 +9,7 @@ #include "coresight-config.h" #include "coresight-etm-perf.h" #include "coresight-syscfg.h" +#include "coresight-syscfg-configfs.h" /* * cscfg_ API manages configurations and features for the entire coresight @@ -287,6 +288,72 @@ static int cscfg_load_config(struct cscfg_config_desc *config_desc) return 0; } +/* get a feature descriptor by name */ +const struct cscfg_feature_desc *cscfg_get_named_feat_desc(const char *name) +{ + const struct cscfg_feature_desc *feat_desc = NULL, *feat_desc_item; + + mutex_lock(&cscfg_mutex); + + list_for_each_entry(feat_desc_item, &cscfg_mgr->feat_desc_list, item) { + if (strcmp(feat_desc_item->name, name) == 0) { + feat_desc = feat_desc_item; + break; + } + } + + mutex_unlock(&cscfg_mutex); + return feat_desc; +} + +/* called with cscfg_mutex held */ +static struct cscfg_feature_csdev * +cscfg_csdev_get_feat_from_desc(struct coresight_device *csdev, + struct cscfg_feature_desc *feat_desc) +{ + struct cscfg_feature_csdev *feat_csdev; + + list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node) { + if (feat_csdev->feat_desc == feat_desc) + return feat_csdev; + } + return NULL; +} + +int cscfg_update_feat_param_val(struct cscfg_feature_desc *feat_desc, + int param_idx, u64 value) +{ + int err = 0; + struct cscfg_feature_csdev *feat_csdev; + struct cscfg_registered_csdev *csdev_item; + + mutex_lock(&cscfg_mutex); + + /* check if any config active & return busy */ + if (atomic_read(&cscfg_mgr->sys_active_cnt)) { + err = -EBUSY; + goto unlock_exit; + } + + /* set the value */ + if ((param_idx < 0) || (param_idx >= feat_desc->nr_params)) { + err = -EINVAL; + goto unlock_exit; + } + feat_desc->params_desc[param_idx].value = value; + + /* update loaded instances.*/ + list_for_each_entry(csdev_item, &cscfg_mgr->csdev_desc_list, item) { + feat_csdev = cscfg_csdev_get_feat_from_desc(csdev_item->csdev, feat_desc); + if (feat_csdev) + feat_csdev->params_csdev[param_idx].current_value = value; + } + +unlock_exit: + mutex_unlock(&cscfg_mutex); + return err; +} + /** * cscfg_load_config_sets - API function to load feature and config sets. * @@ -308,6 +375,8 @@ int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, if (feat_descs) { while (feat_descs[i]) { err = cscfg_load_feat(feat_descs[i]); + if (!err) + err = cscfg_configfs_add_feature(feat_descs[i]); if (err) { pr_err("coresight-syscfg: Failed to load feature %s\n", feat_descs[i]->name); @@ -322,6 +391,8 @@ int cscfg_load_config_sets(struct cscfg_config_desc **config_descs, if (config_descs) { while (config_descs[i]) { err = cscfg_load_config(config_descs[i]); + if (!err) + err = cscfg_configfs_add_config(config_descs[i]); if (err) { pr_err("coresight-syscfg: Failed to load configuration %s\n", config_descs[i]->name); @@ -691,6 +762,7 @@ static void cscfg_clear_device(void) list_for_each_entry(cfg_desc, &cscfg_mgr->config_desc_list, item) { etm_perf_del_symlink_cscfg(cfg_desc); } + cscfg_configfs_release(cscfg_mgr); device_unregister(cscfg_device()); mutex_unlock(&cscfg_mutex); } @@ -704,6 +776,10 @@ int __init cscfg_init(void) if (err) return err; + err = cscfg_configfs_init(cscfg_mgr); + if (err) + goto exit_err; + INIT_LIST_HEAD(&cscfg_mgr->csdev_desc_list); INIT_LIST_HEAD(&cscfg_mgr->feat_desc_list); INIT_LIST_HEAD(&cscfg_mgr->config_desc_list); diff --git a/drivers/hwtracing/coresight/coresight-syscfg.h b/drivers/hwtracing/coresight/coresight-syscfg.h index 7bb8c8e497ba..8d018efd6ead 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg.h +++ b/drivers/hwtracing/coresight/coresight-syscfg.h @@ -6,6 +6,7 @@ #ifndef CORESIGHT_SYSCFG_H #define CORESIGHT_SYSCFG_H +#include #include #include @@ -25,6 +26,7 @@ * @feat_desc_list: List of feature descriptors to load into registered devices. * @config_desc_list: List of system configuration descriptors to load into registered devices. * @sys_active_cnt: Total number of active config descriptor references. + * @cfgfs_subsys: configfs subsystem used to manage configurations. */ struct cscfg_manager { struct device dev; @@ -32,6 +34,7 @@ struct cscfg_manager { struct list_head feat_desc_list; struct list_head config_desc_list; atomic_t sys_active_cnt; + struct configfs_subsystem cfgfs_subsys; }; /* get reference to dev in cscfg_manager */ @@ -57,6 +60,10 @@ struct cscfg_registered_csdev { int __init cscfg_init(void); void cscfg_exit(void); int cscfg_preload(void); +const struct cscfg_feature_desc *cscfg_get_named_feat_desc(const char *name); +int cscfg_update_feat_param_val(struct cscfg_feature_desc *feat_desc, + int param_idx, u64 value); + /* syscfg manager external API */ int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs, From patchwork Wed Apr 14 19:19:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 12203631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96FF4C433B4 for ; Wed, 14 Apr 2021 19:25:36 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B62661168 for ; Wed, 14 Apr 2021 19:25:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B62661168 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZrjEWvNkmM3NwmhK1mkhs6N37ltFXwobRMQ62AR5qL8=; b=d8Qi6U1eNYAtILSuBtOleNLyaa FK9u9PeUsXxq5n0Tr6bEympm4hzTWVcAE3gMGEls2JucMgs+PnJaVMhsSzVc1vyQqeq61TQUeg7w+ mckFp/jKduN4QwH+kWc+NVxY0LTGgndHfwvd0loMrKqOwK9NuxXC9QMbseEGuXqJiiLVEOOw5VwEg AZ7VUsDtQUHwR9m6tWrlozLvLtg34t3D4DafyPunr2lORnL8tvWfobeavF1SOPHHEd7cpM1H5/PMv KNwYFy6JDnyDkb/tOQ2k7KJ7+vwzTAjlapeHFz+/tKMUPAJXxyyABeigm+fAXnOaQA3X7P8Z3Mc+I bczxuZMw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lWl6m-00DXys-Je; Wed, 14 Apr 2021 19:23:29 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2l-00DX4n-5A for linux-arm-kernel@desiato.infradead.org; Wed, 14 Apr 2021 19:19:19 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=References:In-Reply-To:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=kWBYmHFzVaAtr0q3DL3loxqYVHyccUJehxRYe/jfvbg=; b=X/dUqj6Xa9phRCWR9D4MlJfRNt XRmFF+FM5vN7HYrnm7G9/C6I5xo3r2d/WRfFPRu0be3GomC1TVF0HBzr8DJWrfkA/4S5kFabsc5lc NA0Uv4XN6j/dw0CWTUOa87i/FjEOkDK6AnDPL1P5mI5kUUP/kXu38xg3Vw29/ltlOONJ9kzJNITqD lePMFgaiBA9YefLxGBDtZPsRGIf6EEWEe8K3JRxGPRv22Kvq5E1tNyPIOVazNeX3zc12ZrqgFvFbu jBoWm+m4wvtNmG6f6+cXistyKiJK7LI3coT2PgTO3fwCg6oCbad8b/tkMGxjdGpx2TI3H8b6aC6+U 5/m7ncdQ==; Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lWl2h-0082sh-Cn for linux-arm-kernel@lists.infradead.org; Wed, 14 Apr 2021 19:19:17 +0000 Received: by mail-wm1-x330.google.com with SMTP id z24-20020a1cf4180000b029012463a9027fso11099243wma.5 for ; Wed, 14 Apr 2021 12:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kWBYmHFzVaAtr0q3DL3loxqYVHyccUJehxRYe/jfvbg=; b=sr4y3Z6Pw8TKurOZzxC55ZM+iTr/0/GOOCxvdvPqLBKHtQoqDlIxtv5mgv72k/1xHb nLXen8CmSxbqkY5rFhUuj+CkjNzVxtb32AwXRWU0MHIX4Chyay5Ja8i5KSkDfwYhJvyy kvTLWWjov5nrUO9nLRHRLP65w4LtdCQarSx+1v1RVEbzq9+k8wrs2Bmu6/hbfiXh2G3P nkjmZbxk3fcusHl+/tmsX7X15pwiRCA2LJqzdYgxZx6LZrrPy1bCTUlCeClMI9P6pVh8 rn5nvDOK3YlYAvViwF7TzO38vzxyOHRtb601R3wu5fI2GNjDfRqz/ITwVpDg4lIMqWNj cGxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kWBYmHFzVaAtr0q3DL3loxqYVHyccUJehxRYe/jfvbg=; b=IlA01sZRveQMjMMeksQ77LoOIoyrzu/xmFJnXqgc+m1Z1Q1CLa4CoHV1uCRwP/1jPn IMOr20iJOn+bkExgSptO0xt6lG4EgXbw5/e1q9m0WqAYBbCGa8J+CI80mgoS57RgLqCK 7XpmHhZw/a6S6vAjf77OizAGnnuGjD06E62WaR5SjLnFqMzsUweQgYVsykRBavk0Bv4y qlgXDmz85Zb0kBWyp7dQauAcSEGDCos2hC7tCSiIrRYThiDupmY4PAE9t1+C6TfhnNFj 4P9EP7vLuICJBdLl1rq6lZMq8v1yTAR6VfqyS2Jy3IKaE6Yu3kvZpH1S1DQRd/uDNthT sHhA== X-Gm-Message-State: AOAM530e8cCkkMPhgbj+bqDz0YqCmYa7BgK1nvvtHxO28Tql3pFBBo6v fqSwd8nhMz8HGtVd2jWmEVliKLMkS7xrbw== X-Google-Smtp-Source: ABdhPJwBecVNRTPgiuCqfmZYOcEX+yitgpPPOVZbFO1CUs+HPxXpHMUAr0IUNVZI+1JVn8cwqFw23w== X-Received: by 2002:a1c:e3c3:: with SMTP id a186mr4311506wmh.81.1618427954154; Wed, 14 Apr 2021 12:19:14 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:13 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 10/10] Documentation: coresight: Add documentation for CoreSight config Date: Wed, 14 Apr 2021 20:19:03 +0100 Message-Id: <20210414191903.18349-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121915_483901_F19BC7C3 X-CRM114-Status: GOOD ( 35.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds documentation for the CoreSight System configuration manager. Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../trace/coresight/coresight-config.rst | 244 ++++++++++++++++++ Documentation/trace/coresight/coresight.rst | 16 ++ 2 files changed, 260 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-config.rst diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst new file mode 100644 index 000000000000..a4e3ef295240 --- /dev/null +++ b/Documentation/trace/coresight/coresight-config.rst @@ -0,0 +1,244 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +CoreSight System Configuration Manager +====================================== + + :Author: Mike Leach + :Date: October 2020 + +Introduction +============ + +The CoreSight System Configuration manager is an API that allows the +programming of the CoreSight system with pre-defined configurations that +can then be easily enabled from sysfs or perf. + +Many CoreSight components can be programmed in complex ways - especially ETMs. +In addition, components can interact across the CoreSight system, often via +the cross trigger components such as CTI and CTM. These system settings can +be defined and enabled as named configurations. + + +Basic Concepts +============== + +This section introduces the basic concepts of a CoreSight system configuration. + + +Features +-------- + +A feature is a named set of programming for a CoreSight device. The programming +is device dependent, and can be defined in terms of absolute register values, +resource usage and parameter values. + +The feature is defined using a descriptor. This descriptor is used to load onto +a matching device, either when the feature is loaded into the system, or when the +CoreSight device is registered with the configuration manager. + +The load process involves interpreting the descriptor into a set of register +accesses in the driver - the resource usage and parameter descriptions +translated into appropriate register accesses. This interpretation makes it easy +and efficient for the feature to be programmed onto the device when required. + +The feature will not be active on the device until the feature is enabled, and +the device itself is enabled. When the device is enabled then enabled features +will be programmed into the device hardware. + +A feature is enabled as part of a configuration being enabled on the system. + + +Parameter Value +~~~~~~~~~~~~~~~ + +A parameter value is a named value that may be set by the user prior to the +feature being enabled that can adjust the behaviour of the operation programmed +by the feature. + +For example, this could be a count value in a programmed operation that repeats +at a given rate. When the feature is enabled then the current value of the +parameter is used in programming the device. + +The feature descriptor defines a default value for a parameter, which is used +if the user does not supply a new value. + +Users can update parameter values using the configfs API for the CoreSight +system - which is described below. + +The current value of the parameter is loaded into the device when the feature +is enabled on that device. + + +Configurations +-------------- + +A configuration defines a set of features that are to be used in a trace +session where the configuration is selected. For any trace session only one +configuration may be selected. + +The features defined may be on any type of device that is registered +to support system configuration. A configuration may select features to be +enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a +specific CTI on the system. + +As with the feature, a descriptor is used to define the configuration. +This will define the features that must be enabled as part of the configuration +as well as any preset values that can be used to override default parameter +values. + + +Preset Values +~~~~~~~~~~~~~ + +Preset values are easily selectable sets of parameter values for the features +that the configuration uses. The number of values in a single preset set, equals +the sum of parameter values in the features used by the configuration. + +e.g. a configuration consists of 3 features, one has 2 parameters, one has +a single parameter, and another has no parameters. A single preset set will +therefore have 3 values. + +Presets are optionally defined by the configuration, up to 15 can be defined. +If no preset is selected, then the parameter values defined in the feature +are used as normal. + + +Operation +~~~~~~~~~ + +The following steps take place in the operation of a configuration. + +1) In this example, the configuration is 'autofdo', which has an + associated feature 'strobing' that works on ETMv4 CoreSight Devices. + +2) The configuration is enabled. For example 'perf' may select the + configuration as part of its command line:: + + perf record -e cs_etm/autofdo/ myapp + + which will enable the 'autofdo' configuration. + +3) perf starts tracing on the system. As each ETMv4 that perf uses for + trace is enabled, the configuration manager will check if the ETMv4 + has a feature that relates to the currently active configuration. + In this case 'strobing' is enabled & programmed into the ETMv4. + +4) When the ETMv4 is disabled, any registers marked as needing to be + saved will be read back. + +5) At the end of the perf session, the configuration will be disabled. + + +Viewing Configurations and Features +=================================== + +The set of configurations and features that are currently loaded into the +system can be viewed using the configfs API. + +Mount configfs as normal and the 'cs-syscfg' subsystem will appear:: + + $ ls /config + cs-syscfg stp-policy + +This has two sub-directories:: + + $ cd cs-syscfg/ + $ ls + configurations features + +The system has the configuration 'autofdo' built in. It may be examined as +follows:: + + $ cd configurations/ + $ ls + autofdo + $ cd autofdo/ + $ ls + description preset1 preset3 preset5 preset7 preset9 + feature_refs preset2 preset4 preset6 preset8 + $ cat description + Setup ETMs with strobing for autofdo + $ cat feature_refs + strobing + +Each preset declared has a preset subdirectory declared. The values for +the preset can be examined:: + + $ cat preset1/values + strobing.window = 0x1388 strobing.period = 0x2 + $ cat preset2/values + strobing.window = 0x1388 strobing.period = 0x4 + +The features referenced by the configuration can be examined in the features +directory:: + + $ cd ../../features/strobing/ + $ ls + description matches nr_params params + $ cat description + Generate periodic trace capture windows. + parameter 'window': a number of CPU cycles (W) + parameter 'period': trace enabled for W cycles every period x W cycles + $ cat matches + SRC_ETMV4 + $ cat nr_params + 2 + +Move to the params directory to examine and adjust parameters:: + + cd params + $ ls + period window + $ cd period + $ ls + value + $ cat value + 0x2710 + # echo 15000 > value + # cat value + 0x3a98 + +Parameters adjusted in this way are reflected in all device instances that have +loaded the feature. + + +Using Configurations in perf +============================ + +The configurations loaded into the CoreSight configuration management are +also declared in the perf 'cs_etm' event infrastructure so that they can +be selected when running trace under perf:: + + $ ls /sys/devices/cs_etm + configurations format perf_event_mux_interval_ms sinks type + events nr_addr_filters power + +Key directories here are 'configurations' - which lists the loaded +configurations, and 'events' - a generic perf directory which allows +selection on the perf command line.:: + + $ ls configurations/ + autofdo + $ cat configurations/autofdo + 0xa7c3dddd + +As with the sinks entries, this provides a hash of the configuration name. +The entry in the 'events' directory uses perfs built in syntax generator +to substitute the syntax for the name when evaluating the command:: + + $ ls events/ + autofdo + $ cat events/autofdo + configid=0xa7c3dddd + +The 'autofdo' configuration may be selected on the perf command line:: + + $ perf record -e cs_etm/autofdo/u --per-thread + +A preset to override the current parameter values can also be selected:: + + $ perf record -e cs_etm/autofdo,preset=1/u --per-thread + +When configurations are selected in this way, then the trace sink used is +automatically selected. diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 169749efd8d1..7ec656c9f0dc 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -619,6 +619,20 @@ A separate documentation file is provided to explain the use of these devices. (:doc:`coresight-ect`) [#fourth]_. +CoreSight System Configuration +------------------------------ + +CoreSight components can be complex devices with many programming options. +Furthermore, components can be programmed to interact with each other across the +complete system. + +A CoreSight System Configuration manager is provided to allow these complex programming +configurations to be selected and used easily from perf and sysfs. + +See the separate document for further information. +(:doc:`coresight-config`) [#fifth]_. + + .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm .. [#second] Documentation/trace/stm.rst @@ -626,3 +640,5 @@ A separate documentation file is provided to explain the use of these devices. .. [#third] https://github.com/Linaro/perf-opencsd .. [#fourth] Documentation/trace/coresight/coresight-ect.rst + +.. [#fifth] Documentation/trace/coresight/coresight-config.rst