From patchwork Fri Nov 23 09:44:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 10695443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FCF0175A for ; Fri, 23 Nov 2018 09:44:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4AC6E2C2C6 for ; Fri, 23 Nov 2018 09:44:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D5512C2D4; Fri, 23 Nov 2018 09:44:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BEEA22C2C6 for ; Fri, 23 Nov 2018 09:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388048AbeKWU2J (ORCPT ); Fri, 23 Nov 2018 15:28:09 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:42334 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732043AbeKWU2I (ORCPT ); Fri, 23 Nov 2018 15:28:08 -0500 Received: by mail-pf1-f195.google.com with SMTP id 64so3117808pfr.9; Fri, 23 Nov 2018 01:44:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Kr93T5nijBQ3GQq5BgtND5H6Q0KuJDUwRY2zFzNeJZo=; b=gH5zI3W2RVqR1eFdTwQbRiw1P5GEipXZI+WM3CXc5z9tpEZFKNxtJct0QUCURiP+g8 X0uvYvYA3E61at48BPuMOaO+iLTaD822y17zzuTRLsa0b2om03fk1NIidtb8NYuUx29c XB2/28vXMNI1bSUHe6pr72KVbQ6UYhaMT4h2xERGgC3tiAyuYxKFsJQ21VyYV/YCBuWW cT22VQpSDU7biVTwFY+eXavzzch9GdGxGG0sBeE6/1tT38Z52n5+C9C6xmw3Tz0GfwzJ Y1XIqxYLbm0TGmjw/sUfZPFzrG53sTZ82yAxO/LwDEJD8uGBLrI/zeO/jnCOl4Fbgjwe 0bXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Kr93T5nijBQ3GQq5BgtND5H6Q0KuJDUwRY2zFzNeJZo=; b=ii8wKfwtYZUC0wdGYXpxV4m5g+Xk9GXNPYLV1eJ1L47UkrPZNiaarkEoeo+xN4EkW7 3I4A9M0NQf9syT03vFW9AoEaWNyiHx6hJbBBHJ8eJy56KUGulNBlQVcw3j6mfAYqvmDW 6+UbMLjY8BYtozdvtsqVW7/yALVxR34JurWNYIf5I+QUQ6JlijbmRKg8UwPCWD+w4X+J xT71KBDUy0/LssRHkfYbqY/2cI6Ps0E7k351y4kqC1Yg0uqqJwpBMvf0exnKvWBUnZIq ZDKWJvOyIdO0FuXcTO9vhwDpKaunKoMYGAhbPrQdeczXs6sPKdK2eeHVrEaLN+Xot3Mt +RFQ== X-Gm-Message-State: AGRZ1gLdOx9HgELoct4PLDA8Bu/yGfgwYQz216KQmnLK1909FphT9+7i 1TTFdm35bTirHS+1BTfK49k= X-Google-Smtp-Source: AJdET5eYspqJqqS/A2X+B0VFYYv0OT9wVJN7/CFWTfHeTrYGqNuFAzFZK85HWCcb15VSpnLVOmIY8A== X-Received: by 2002:a62:b9a:: with SMTP id 26mr15372771pfl.196.1542966276926; Fri, 23 Nov 2018 01:44:36 -0800 (PST) Received: from localhost.localdomain ([103.51.74.164]) by smtp.gmail.com with ESMTPSA id o189sm34059848pfg.117.2018.11.23.01.44.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 01:44:36 -0800 (PST) From: Anand Moon To: Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Andrzej Hajda , Marian Mihailescu Subject: [PATCH 1/3] clk: samsung: exynos5420: add VPLL rate table for g3d clock Date: Fri, 23 Nov 2018 09:44:11 +0000 Message-Id: <20181123094413.1108-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marian Mihailescu A specific clock rate table is added for VPLL so it is possible to set frequency of the VPLL output clock that used by the g3d clock. Cc: Andrzej Hajda Cc: Chanwoo Choi Signed-off-by: Marian Mihailescu Signed-off-by: Anand Moon --- drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c5898f..34156bdfd0d2 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2), + PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2), + PLL_35XX_RATE(24 * MHZ, 480000000U, 320, 4, 2), + PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2), + PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2), + PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3), + PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3), + PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), +}; + static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), @@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), From patchwork Fri Nov 23 09:44:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 10695461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 565035A4 for ; Fri, 23 Nov 2018 09:44:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4525E2C2D0 for ; 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Fri, 23 Nov 2018 01:44:41 -0800 (PST) Received: from localhost.localdomain ([103.51.74.164]) by smtp.gmail.com with ESMTPSA id o189sm34059848pfg.117.2018.11.23.01.44.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 01:44:41 -0800 (PST) From: Anand Moon To: Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Andrzej Hajda Subject: [PATCH 2/3] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_sclk_vpll Date: Fri, 23 Nov 2018 09:44:12 +0000 Message-Id: <20181123094413.1108-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181123094413.1108-1-linux.amoon@gmail.com> References: <20181123094413.1108-1-linux.amoon@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows changing the VPLL output frequency through the g3d subsystem clock tree leaf clocks. Cc: Andrzej Hajda Cc: Chanwoo Choi Signed-off-by: Anand Moon --- drivers/clk/samsung/clk-exynos5420.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34156bdfd0d2..6bf1b2e89106 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -647,7 +647,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), - MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), + MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), From patchwork Fri Nov 23 09:44:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 10695445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B52A5A4 for ; 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Fri, 23 Nov 2018 01:44:45 -0800 (PST) Received: from localhost.localdomain ([103.51.74.164]) by smtp.gmail.com with ESMTPSA id o189sm34059848pfg.117.2018.11.23.01.44.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 01:44:45 -0800 (PST) From: Anand Moon To: Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Rob Herring Subject: [PATCH 3/3] ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC Date: Fri, 23 Nov 2018 09:44:13 +0000 Message-Id: <20181123094413.1108-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181123094413.1108-1-linux.amoon@gmail.com> References: <20181123094413.1108-1-linux.amoon@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add missing Netwwork on chip for g3d bus node using VDD_INI for Exynos542x SoC. - CLK_DOUT_ACLK_G3D for G3D's AXI Cc: Chanwoo Choi Signed-off-by: Anand Moon --- arch/arm/boot/dts/exynos5420.dtsi | 57 +++++++++++++++++-- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 ++ 2 files changed, 56 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff15880761..bc7203bb1282 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1047,6 +1047,14 @@ status = "disabled"; }; + bus_g3d: bus_g3d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK_G3D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g3d_opp_table>; + status = "disabled"; + }; + bus_jpeg: bus_jpeg { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_JPEG>; @@ -1245,7 +1253,44 @@ }; }; - bus_jpeg_opp_table: opp_table11 { + bus_g3d_opp_table: opp_table11 { + compatible = "operating-points-v2"; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1025000>; + }; + opp@543000000 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <987500>; + }; + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <950000>; + }; + opp@420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <937500>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <900000>; + }; + opp@266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <862500>; + }; + opp@177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = <862500>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <862500>; + }; + }; + + bus_jpeg_opp_table: opp_table12 { compatible = "operating-points-v2"; opp00 { @@ -1262,7 +1307,7 @@ }; }; - bus_jpeg_apb_opp_table: opp_table12 { + bus_jpeg_apb_opp_table: opp_table13 { compatible = "operating-points-v2"; opp00 { @@ -1279,7 +1324,7 @@ }; }; - bus_disp1_fimd_opp_table: opp_table13 { + bus_disp1_fimd_opp_table: opp_table14 { compatible = "operating-points-v2"; opp00 { @@ -1290,7 +1335,7 @@ }; }; - bus_disp1_opp_table: opp_table14 { + bus_disp1_opp_table: opp_table15 { compatible = "operating-points-v2"; opp00 { @@ -1304,7 +1349,7 @@ }; }; - bus_gscl_opp_table: opp_table15 { + bus_gscl_opp_table: opp_table16 { compatible = "operating-points-v2"; opp00 { @@ -1318,7 +1363,7 @@ }; }; - bus_mscl_opp_table: opp_table16 { + bus_mscl_opp_table: opp_table17 { compatible = "operating-points-v2"; opp00 { diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2fac4baf1eb4..6e39e4594502 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -89,6 +89,11 @@ status = "okay"; }; +&bus_g3d { + devfreq = <&bus_wcore>; + status = "okay"; +}; + &bus_jpeg { devfreq = <&bus_wcore>; status = "okay";