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Mon, 19 Apr 2021 00:33:00 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:90c:e290:2e82:31e6:67f1:4f33]) by smtp.gmail.com with ESMTPSA id y125sm5492311wmy.34.2021.04.19.00.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 00:32:59 -0700 (PDT) From: Neil Armstrong To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, devicetree@vger.kernel.org Subject: [PATCH v3 1/5] dt-bindings: display: mediatek, hdmi: Convert to use graph schema Date: Mon, 19 Apr 2021 09:32:40 +0200 Message-Id: <20210419073244.2678688-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419073244.2678688-1-narmstrong@baylibre.com> References: <20210419073244.2678688-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Patch-Hashes: v=1; h=sha256; i=76lew5EeaRRhsAki7YLcUNiHeBtoR+DlILtleRFF7fM=; m=nn8XzvbbItXNlk7a/2M6U3KbnSIqLoOqQ26l1yCYhrQ=; p=y6Xf5rjieTHDTy2Ro4habUke5zB6c71HJAuGrU2DG3k=; g=50686022c2e5549f28b159c238abb8963aacaa81 X-Patch-Sig: m=pgp; i=narmstrong@baylibre.com; s=0xA4CFF8AE; b=iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmB9MgwACgkQd9zb2sjISdGVEBAAxlf VrxJ6XBb2HsruF9PwMuTazSU8NKQ5+nQh3eMLexzYd5hMI+HGG0l9WpjsWvx1+heBxfWdACgg4aNB /hzm4wHrDp417iXI8XaoH2Wuj9SBppkg9ELvGJinkVDj3v2jrXpuSGw7B2wAtQ7cB6UmQcGG7+eQv HRz19m3V8U/yHs6Qi+yKWT3H+6NsWhuVICJsKLXE2uFTwsnGudjbc/MG1jzAz6bTWJu7EiJdxTDCv +SWqeCWBjwt8XyMROjISwLbtaM1Jv6p5RnrqDLKffKJXadg7yemYU1UzLlxoK3mw1Lw6XFNy4erV4 J7//8sqWMW616ChPaTiMFixLsnZsWoTR27/aTmctgwJxai7K5XBSV8kUDep9zGysdD21efDqvWJyp olaWOZdYd0Vc6PCdiGAoedv2xR7ZSVAbtyyJfDK9yJBJ2EDsB+mLQb04elpdDEnWsgtUF0tBUMw6E rvijjdcPCkRB9oLNfObx4UnRsPkTk0K3QLUZIdfCvjEFy2ZN85lYxhhK8heM3hN7pE+APDaDwtIO4 eAHQB+TalqsjxEnD6XEJDmBHTtP1e6AS0zHo49Y1welkOcbzn9FwMcKFCrMu8qPoczHXtA982MRXH 5Lie9Vcd1lG3rqkrxloCzFIY970+nMxVSMQ/x7MLdeAQJyznorrMSlgZn8BPE4EU= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update the mediatek,dpi binding to use the graph schema. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../display/mediatek/mediatek,cec.yaml | 51 +++++++ .../display/mediatek/mediatek,hdmi-ddc.yaml | 57 ++++++++ .../display/mediatek/mediatek,hdmi.txt | 136 ------------------ .../display/mediatek/mediatek,hdmi.yaml | 132 +++++++++++++++++ 4 files changed, 240 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml new file mode 100644 index 000000000000..b38d8732d7e0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI CEC Controller Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI CEC controller handles hotplug detection and CEC communication. + +properties: + compatible: + enum: + - mediatek,mt7623-cec + - mediatek,mt8173-cec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + cec: cec@10013000 { + compatible = "mediatek,mt8173-cec"; + reg = <0x10013000 0xbc>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml new file mode 100644 index 000000000000..c8ba94d6908b --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt7623-hdmi-ddc + - mediatek,mt8173-hdmi-ddc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi_ddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + reg = <0x11012000 0x1c>; + interrupts = ; + clocks = <&pericfg CLK_PERI_I2C5>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt deleted file mode 100644 index b284ca51b913..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ /dev/null @@ -1,136 +0,0 @@ -Mediatek HDMI Encoder -===================== - -The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from -its parallel input. - -Required properties: -- compatible: Should be "mediatek,-hdmi". -- the supported chips are mt2701, mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "pixel", "pll", "bclk", and "spdif". -- phys: phandle link to the HDMI PHY node. - See Documentation/devicetree/bindings/phy/phy-bindings.txt for details. -- phy-names: must contain "hdmi" -- mediatek,syscon-hdmi: phandle link and register offset to the system - configuration registers. For mt8173 this must be offset 0x900 into the - MMSYS_CONFIG region: <&mmsys 0x900>. -- ports: A node containing input and output port nodes with endpoint - definitions as documented in Documentation/devicetree/bindings/graph.txt. -- port@0: The input port in the ports node should be connected to a DPI output - port. -- port@1: The output port in the ports node should be connected to the input - port of a connector node that contains a ddc-i2c-bus property, or to the - input port of an attached bridge chip, such as a SlimPort transmitter. - -HDMI CEC -======== - -The HDMI CEC controller handles hotplug detection and CEC communication. - -Required properties: -- compatible: Should be "mediatek,-cec" -- the supported chips are mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clock - -HDMI DDC -======== - -The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. -The Mediatek's I2C controller is used to interface with I2C devices. - -Required properties: -- compatible: Should be "mediatek,-hdmi-ddc" -- the supported chips are mt7623 and mt8173 -- reg: Physical base address and length of the controller's registers -- clocks: device clock -- clock-names: Should be "ddc-i2c". - -HDMI PHY -======== -See phy/mediatek,hdmi-phy.yaml - -Example: - -cec: cec@10013000 { - compatible = "mediatek,mt8173-cec"; - reg = <0 0x10013000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; -}; - -hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt8173-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - #clock-cells = <0>; - #phy-cells = <0>; -}; - -hdmi_ddc0: i2c@11012000 { - compatible = "mediatek,mt8173-hdmi-ddc"; - reg = <0 0x11012000 0 0x1c>; - interrupts = ; - clocks = <&pericfg CLK_PERI_I2C5>; - clock-names = "ddc-i2c"; -}; - -hdmi0: hdmi@14025000 { - compatible = "mediatek,mt8173-hdmi"; - reg = <0 0x14025000 0 0x400>; - interrupts = ; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLLCK>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pin>; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; - assigned-clock-parents = <&hdmi_phy>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml new file mode 100644 index 000000000000..6a144faed682 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt2701-hdmi + - mediatek,mt7623-hdmi + - mediatek,mt8173-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Pixel Clock + - description: HDMI PLL + - description: Bit Clock + - description: S/PDIF Clock + + clock-names: + items: + - const: pixel + - const: pll + - const: bclk + - const: spdif + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + + mediatek,syscon-hdmi: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: | + phandle link and register offset to the system configuration registers. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: | + Input port node. This port should be connected to a DPI output port. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + Output port node. This port should be connected to the input port of a connector + node that contains a ddc-i2c-bus property, or to the input port of an attached + bridge chip, such as a SlimPort transmitter. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + - mediatek,syscon-hdmi + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0x14025000 0x400>; + interrupts = ; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + +... 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Mon, 19 Apr 2021 00:33:01 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:90c:e290:2e82:31e6:67f1:4f33]) by smtp.gmail.com with ESMTPSA id y125sm5492311wmy.34.2021.04.19.00.33.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 00:33:01 -0700 (PDT) From: Neil Armstrong To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, devicetree@vger.kernel.org Subject: [PATCH v3 2/5] dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings Date: Mon, 19 Apr 2021 09:32:41 +0200 Message-Id: <20210419073244.2678688-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419073244.2678688-1-narmstrong@baylibre.com> References: <20210419073244.2678688-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Patch-Hashes: v=1; h=sha256; i=weRuGrIrSCS/7E0z7zGXTfkieqKmo2b9b3zEqPhglEk=; m=4OhWpDRl3EWsKo2xAbHezHdcGoUrsEeovaOubbEbqC4=; p=zKmvMzMsvi/UJaeb54phx7cTaLZasyaFc1SoAWluN64=; g=bc9c5611c788292574b503426cd53c1df4c9afa2 X-Patch-Sig: m=pgp; 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Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,cec.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,hdmi.yaml | 1 + 3 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml index b38d8732d7e0..66288b9f0aa6 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-cec + - mediatek,mt8167-cec - mediatek,mt8173-cec reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml index c8ba94d6908b..b6fcdfb99ab2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - mediatek,mt7623-hdmi-ddc + - mediatek,mt8167-hdmi-ddc - mediatek,mt8173-hdmi-ddc reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml index 6a144faed682..111967efa999 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -19,6 +19,7 @@ properties: enum: - mediatek,mt2701-hdmi - mediatek,mt7623-hdmi + - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: From patchwork Mon Apr 19 07:32:42 2021 Content-Type: text/plain; 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Mon, 19 Apr 2021 00:33:02 -0700 (PDT) From: Neil Armstrong To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com Subject: [PATCH v3 3/5] gpu/drm: mediatek: hdmi: add check for CEA modes only Date: Mon, 19 Apr 2021 09:32:42 +0200 Message-Id: <20210419073244.2678688-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419073244.2678688-1-narmstrong@baylibre.com> References: <20210419073244.2678688-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Patch-Hashes: v=1; h=sha256; i=8hZCU8l60f4io5DjF0ScarfKg+RXuxNEKXbnKgyzEvU=; m=p9m3qQg9ro9SNdO45JuikwvmDNAXyAV1Ql4r4DZfEGY=; p=3uqgx9h0NLat9GhpnH/7lHx4Omxj//rcVoYK6CVuKP0=; g=19421281216f8c01edb5b08ac035741d73dddc53 X-Patch-Sig: m=pgp; i=narmstrong@baylibre.com; s=0xA4CFF8AE; b=iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmB9MgwACgkQd9zb2sjISdFStg/7Bfk iMsl/JsD8ylGFg39AeUNYyCs6C4eUkyDyeEhc22g66p2B11Zff/gIQ24FSdUu38vmW6pQm0zlw8h6 bUoAA45N3tGtxKBJbsJg3rj8tU9AyajQjTbHTMXslGiMEk/8T6WOti7jedTAv1yB2jKbwEyMyGqfD vB6gC6m8TBs877WfOIbnGq/z7Kj+JY9TrIsPu/4CoidUSDGXSvewYpfO01CtNDRqHPnxO03ep7Wgl XcvVp4y7+BnxpiD06evJzQEmoBGpITlAnJQVKWePqM0qB9jCGet2rLlrpe+QMX38kSMmnVRkT2FLd vVcO3cr2DyiHTugOcFZGdY4Prf/Mwd+fZ5F73EEGFH9KGBwm8b5PnmhlzX40/OROWEVZjpJUQtcl9 nbwb80rprYYQbo84X9gLJMn1ZeafTScj+nkzVkZc9IFFRiEKHovgoRcAM9sawmJ6fbIh+w29XTZ3X LNABEzq4WsLoT5tDsp5zJ6elpRgj2qzPwLrgZTAtH5CwPYMEVBYZBTgeFPBl/r/qaecngE5hyNq2b ovTVqV5d0ip55pZGxXINUGt1WAG4W5yqCKHeOl5V+Qw5L284AlhBykZCwCgbH2jid4gEvfIRLEeJk o28EAt6n9FDaUxCv3hXXaLCpRwdaBcER8KtE0hORVvjcpEEGbx+47CNddJ9S9YJM= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some SoCs like the MT8167 are not validated and supported for HDMI modes out of HDMI CEA modes, so add a configuration boolean to filter out non-CEA modes. Signed-off-by: Fabien Parent Signed-off-by: Neil Armstrong Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index dea46d66e712..0539262e69d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -148,6 +148,7 @@ struct hdmi_audio_param { struct mtk_hdmi_conf { bool tz_disabled; + bool cea_modes_only; }; struct mtk_hdmi { @@ -1222,6 +1223,9 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge, return MODE_BAD; } + if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode)) + return MODE_BAD; + if (mode->clock < 27000) return MODE_CLOCK_LOW; if (mode->clock > 297000) From patchwork Mon Apr 19 07:32:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12210955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C55AAC43460 for ; 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Mon, 19 Apr 2021 00:33:04 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:90c:e290:2e82:31e6:67f1:4f33]) by smtp.gmail.com with ESMTPSA id y125sm5492311wmy.34.2021.04.19.00.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 00:33:03 -0700 (PDT) From: Neil Armstrong To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com Subject: [PATCH v3 4/5] gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock Date: Mon, 19 Apr 2021 09:32:43 +0200 Message-Id: <20210419073244.2678688-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419073244.2678688-1-narmstrong@baylibre.com> References: <20210419073244.2678688-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Patch-Hashes: v=1; h=sha256; i=fmerdT5sHqIGuoUTZDrccRl/0zoMQFtVjUuTCnM2Nu4=; m=kS8rkVG4drN6qA/sYwEi96Os3BdhRRg85LscWfEOz9U=; p=XzRamrwQ2kdOF7GfyCvXP4CcM6GKIYyeek0NDT5Wv0U=; g=cc05bb87977587a07030f409f3d9b83309a9f1c7 X-Patch-Sig: m=pgp; i=narmstrong@baylibre.com; s=0xA4CFF8AE; b=iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmB9MgwACgkQd9zb2sjISdGlFg//d/P CVZrkoJp/X4KUj/7Z+BhPfopOjq0Wiun0RiLoVicfOFVE23BrE2jif6szo9bLnddyzHnqRC/LOmDG sQEiX89TVIsnsasXsRPGFbHqMgpdzHdZeg0JVUEkacKc7WObdzdorYa7E1Sy85lkLQQFZERYRxIYs x7l8Rfn+fYO0g/2bM5Xo39BN+vjktqt2Z6+jf8PMaNHdWHbZ/Sibggehilqv1gvbNGzArviBVbogb CzbuFkm4caJlGpyuOh9lzqb5oX1dS1b4sJOKlV0vab8riyRDSWIrvSve6lIJKS5Zy2nnePFJDRIdo KXCX8tTjJ3oR9eFt0I6uDo1tPnQNUN+I+YPiwH1ADYzFZe/l6jgrmJ8vmD3sEPsqu8StxA2C97stl kPJjY6S3CSQAwoWUiXOY06ExKPKQdzJlilfy0bwmBllmpHeaV2AgOUw/SUVZQKFLQ8gy0dHTgCuhJ xtYcQKSob+AoJUPLuKlkJ5rWm7DvsLQ59ZkIVczynpm5b+fxtQtAwgFXqqcVrOe/BwQGzcTkG+w69 g3JFk9Jgf3DMbQ9SL1gKIdDr+DqyBPjvgu2XxQk+4d8A8MV36AQpEUTrF5WKJnf6aM9l7TIUr8hOw vDn318ylmunNTWomQl7CBbWMUxB26/KBGzy/HJ/rlIaRskMmDaGmzSMMQQD2KUYs= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some SoCs like the MT8167 have a hard limit on the maximal supported HDMI TMDS clock, so add a configuration value to filter out those modes. Signed-off-by: Fabien Parent Signed-off-by: Neil Armstrong Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 0539262e69d3..bc50d97f2553 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -149,6 +149,7 @@ struct hdmi_audio_param { struct mtk_hdmi_conf { bool tz_disabled; bool cea_modes_only; + unsigned long max_mode_clock; }; struct mtk_hdmi { @@ -1226,6 +1227,10 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge, if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode)) return MODE_BAD; + if (hdmi->conf->max_mode_clock && + mode->clock > hdmi->conf->max_mode_clock) + return MODE_CLOCK_HIGH; + if (mode->clock < 27000) return MODE_CLOCK_LOW; if (mode->clock > 297000) From patchwork Mon Apr 19 07:32:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12210957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B82EEC43462 for ; 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Mon, 19 Apr 2021 00:33:05 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:90c:e290:2e82:31e6:67f1:4f33]) by smtp.gmail.com with ESMTPSA id y125sm5492311wmy.34.2021.04.19.00.33.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 00:33:05 -0700 (PDT) From: Neil Armstrong To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com Subject: [PATCH v3 5/5] gpu/drm: mediatek: hdmi: add MT8167 configuration Date: Mon, 19 Apr 2021 09:32:44 +0200 Message-Id: <20210419073244.2678688-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419073244.2678688-1-narmstrong@baylibre.com> References: <20210419073244.2678688-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Patch-Hashes: v=1; h=sha256; i=1cCt+CaaWnX35LcUAeqH/AEy6pDlaztP4tTWRAOEW/o=; m=teArBpVk0i7hN2a9Z6e7zXDAZkWNF5zds9OXrfPJoB0=; p=K8BqlJdCG5wZ6jJdNp1bjexbIQG0ke7ZpzDma32UUOk=; g=6cc1cbbc495832f0509ff603f4cf0aef4bc07664 X-Patch-Sig: m=pgp; i=narmstrong@baylibre.com; s=0xA4CFF8AE; b=iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmB9MgwACgkQd9zb2sjISdEMxxAAwQG a+P54dAPqlMY8zUbqvNt5ka/vcf7mcAprjgN/KlWL1AGezCSgcDrg14v3AenQoy0qGmKNTOWWXNgy KUDxzxqqLMN8026Rbu9qA7UYiXBATnDffnboSbdDIp1pq9BNmPxcXh3TxJaY4hhellGfM/mayJOEM ShU8TTCZNqloDOMVg70ASdsuanBjdHAvdnuej0NkHyzRyExEXen3COBwjIR3XfxQOeTk2a1SKk1ZI ODSa0Z/WrffKry0RNauAowcFc1HEMWJOA/WOzpy5XhkNhYUgXOGUkE9mP46T0FBqk/rPEPlNLRm8g tngkf1Q0yr7pnW6EIsO5n7UeYMDz8d2oxXzjyu96SVYyhyu9FvA616lLwSuSRNj3WcS49t/aEYXe0 yLcdRpQrsYCcEJXv4CmL+2DM6CG9CvIcfDkB8BomaihadIG9o71Y623796hJw/N5QzCli31vz3+xO HmARnkiHXlLrCHCuEhgHauJcbR2qtsrUPB7uagYIR5GjSFDfr9MOfTohL6/sPjWEUFHznhilRdd+1 j2LapJBSbUHjoIiGiPDw5xfzhYeZP/MFKaFQqb4Zyk/OBgeAJTTgLYByTyez5xIcTTc0SJ7m1mQYt jbm09ErtlMy9clPUBh0c9ZiMu/j/oo6Z0LH9Rfu5P27shuGK4WybCEhfHVkBAU24= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock, and is not validated and supported for HDMI modes out of HDMI CEA modes, so add a configuration entry linked to the MT8167 compatible. Signed-off-by: Fabien Parent Signed-off-by: Neil Armstrong Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index bc50d97f2553..c1651a83700d 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1787,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { .tz_disabled = true, }; +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = { + .max_mode_clock = 148500, + .cea_modes_only = true, +}; + static const struct of_device_id mtk_drm_hdmi_of_ids[] = { { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701, }, + { .compatible = "mediatek,mt8167-hdmi", + .data = &mtk_hdmi_conf_mt8167, + }, { .compatible = "mediatek,mt8173-hdmi", }, {}