From patchwork Wed Apr 21 08:46:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ong Boon Leong X-Patchwork-Id: 12215677 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF6F7C433ED for ; Wed, 21 Apr 2021 08:41:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A91D561426 for ; Wed, 21 Apr 2021 08:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236233AbhDUImQ (ORCPT ); Wed, 21 Apr 2021 04:42:16 -0400 Received: from mga02.intel.com ([134.134.136.20]:28332 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231354AbhDUImO (ORCPT ); Wed, 21 Apr 2021 04:42:14 -0400 IronPort-SDR: f+l9Wj78NpD/RQTmAVr2CkDG/2k+HCYx1LEmFVCou8yLBQbS/OzgKf2DCZeC9WDfdBP0dqbw82 qiq9AUj+iVOQ== X-IronPort-AV: E=McAfee;i="6200,9189,9960"; a="182793781" X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="182793781" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 01:41:41 -0700 IronPort-SDR: /fwMw7Aaz+8j1L6wYxFmScfEReB1nmgpeJCTWfKvGnnbkI3h1qiIYaZADDhsfvqJp/tpUFEtIi rdWm/MvFW9ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="455249802" Received: from glass.png.intel.com ([10.158.65.59]) by fmsmga002.fm.intel.com with ESMTP; 21 Apr 2021 01:41:38 -0700 From: Ong Boon Leong To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Jakub Kicinski Cc: Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ong Boon Leong Subject: [PATCH net-next 1/1] stmmac: intel: set TSO/TBS TX Queues default settings Date: Wed, 21 Apr 2021 16:46:06 +0800 Message-Id: <20210421084606.20851-1-boon.leong.ong@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org TSO and TBS cannot coexist, for now we set Intel mGbE controller to use below TX Queue mapping: TxQ0 uses TSO and the rest of TXQs supports TBS. Signed-off-by: Ong Boon Leong --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index ec140fc4a0f5..844332a2c2e0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -446,6 +446,9 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, /* Disable Priority config by default */ plat->tx_queues_cfg[i].use_prio = false; + /* Default TX Q0 to use TSO and rest TXQ for TBS */ + if (i > 0) + plat->tx_queues_cfg[i].tbs_en = 1; } /* FIFO size is 4096 bytes for 1 tx/rx queue */