From patchwork Thu Apr 29 09:12:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A276C433B4 for ; Thu, 29 Apr 2021 09:13:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D25016140C for ; Thu, 29 Apr 2021 09:13:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D25016140C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E49CD6EDBF; Thu, 29 Apr 2021 09:13:06 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD3B26E1BC; Thu, 29 Apr 2021 09:13:02 +0000 (UTC) IronPort-SDR: a0Pw7P+worA2acKg/fQKfOOwBGiL0Iy4d0NZD/kBy9hRe1bVZHG96Y+vA9Ym/uY92O8sP/ZBym 6DegUxRA6dAg== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011294" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011294" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:02 -0700 IronPort-SDR: 3IzzdWQhZAY1OE8IdMXeeE/foS1iv46qNYrV0EwwT9ykqGxIxcRuA1IjweAVPEHn/YpUz5lBgk rB9IDHOEgYJQ== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298794" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:01 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 1/6] drm/i915: Drop duplicate WaDisable4x2SubspanOptimization:hsw Date: Thu, 29 Apr 2021 10:12:49 +0100 Message-Id: <20210429091254.855248-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Same workaround was listed two times - once under the Gen7 block and once under the Haswell section. Signed-off-by: Tvrtko Ursulin Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a03a76bb9e2..62cb9ee5bfc3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1859,9 +1859,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) CACHE_MODE_0_GEN7, /* enable HiZ Raw Stall Optimization */ HIZ_RAW_STALL_OPT_DISABLE); - - /* WaDisable4x2SubspanOptimization:hsw */ - wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); } if (IS_VALLEYVIEW(i915)) { From patchwork Thu Apr 29 09:12:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D3D8C433B4 for ; Thu, 29 Apr 2021 09:13:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06C0861441 for ; Thu, 29 Apr 2021 09:13:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 06C0861441 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 997E96EDC1; Thu, 29 Apr 2021 09:13:06 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CB7E6EDC6; Thu, 29 Apr 2021 09:13:04 +0000 (UTC) IronPort-SDR: McAqpJm08l6ynbO8BQJBPC3tkcUtALb5in3XMO72iHz+On13OdieXUm76K3zPyI1Zc49X+sQ6e +d7bAbNAB5ag== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011300" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011300" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:04 -0700 IronPort-SDR: 0KcNisBkZuRp8Krk6VEh6HMHb3wApNVj0RPW6xdcoFEzhOckCg3biSosmmpv4Dv6sX0cMXPkjE 2Oy+JRZ82VIA== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298800" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:02 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 2/6] drm/i915/debugfs: Expose read mask in i915_wa_registers Date: Thu, 29 Apr 2021 10:12:50 +0100 Message-Id: <20210429091254.855248-3-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin In order to stop conflating the validation via readback with the workaround mask I need to expose the read mask separately so gem_workarounds IGT can continue operating correctly. Signed-off-by: Tvrtko Ursulin Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..b9c81376a413 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -757,9 +757,9 @@ static int i915_wa_registers(struct seq_file *m, void *unused) engine->name, count); for (wa = wal->list; count--; wa++) - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08X\n", i915_mmio_reg_offset(wa->reg), - wa->set, wa->clr); + wa->set, wa->clr, wa->read); seq_printf(m, "\n"); } From patchwork Thu Apr 29 09:12:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07180C433ED for ; Thu, 29 Apr 2021 09:13:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A454A6143E for ; Thu, 29 Apr 2021 09:13:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A454A6143E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B86636EDBE; Thu, 29 Apr 2021 09:13:06 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 452EB6EDC0; Thu, 29 Apr 2021 09:13:05 +0000 (UTC) IronPort-SDR: i9b2sI3pzTkGOUVNGBBASnSQPsnKvFOqd6FFOXRUAOmmfY9f6of7yaFsYAARbewMCVGuoKGumT 2GsmTyMn53Gg== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011306" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011306" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:05 -0700 IronPort-SDR: BKA7WUSvQGJ53JBgwMVTk18CVYXVZwExU/vBLAqSOBD2aHk8XiBF5TsqB1E33JrTL6EtreiVyK 1gxcjf7gFG/w== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298807" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:03 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 3/6] drm/i915: Add a separate low-level helper for masked workarounds Date: Thu, 29 Apr 2021 10:12:51 +0100 Message-Id: <20210429091254.855248-4-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin We distinguish masked registers from other workarounds by the mask (clr) being zero for the former. To avoid callers of the low-level wa_add having to know that, and be passing this zero explicitly, add a wa_masked_add low-level helper which embeds this knowledge. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 56 +++++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 62cb9ee5bfc3..a7abf9ca78ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -162,6 +162,18 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, _wa_add(wal, &wa); } +static void wa_masked_add(struct i915_wa_list *wal, i915_reg_t reg, + u32 set, u32 read_mask) +{ + struct i915_wa wa = { + .reg = reg, + .set = set, + .read = read_mask, + }; + + _wa_add(wal, &wa); +} + static void wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) { @@ -200,20 +212,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val); } static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { - wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); + wa_masked_add(wal, reg, _MASKED_BIT_DISABLE(val), val); } static void wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val) { - wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask); + wa_masked_add(wal, reg, _MASKED_FIELD(mask, val), mask); } static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -836,10 +848,10 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* L3 caching of data atomics doesn't work -- disable it. */ wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); - wa_add(wal, - HSW_ROW_CHICKEN3, 0, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), - 0 /* XXX does this reg exist? */); + wa_masked_add(wal, + HSW_ROW_CHICKEN3, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + 0 /* XXX does this reg exist? */); /* WaVSRefCountFullforceMissDisable:hsw */ wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); @@ -1947,10 +1959,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, GEN7_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, - GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4); } if (IS_GEN_RANGE(i915, 6, 7)) @@ -2000,10 +2012,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ - wa_add(wal, - GEN6_GT_MODE, 0, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), - GEN6_WIZ_HASHING_16x4); + wa_masked_field_set(wal, + GEN6_GT_MODE, + GEN6_WIZ_HASHING_MASK, + GEN6_WIZ_HASHING_16x4); /* WaDisable_RenderCache_OperationalFlush:snb */ wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); @@ -2021,10 +2033,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) if (IS_GEN_RANGE(i915, 4, 6)) /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - wa_add(wal, MI_MODE, - 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), - /* XXX bit doesn't stick on Broadwater */ - IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); + wa_masked_add(wal, MI_MODE, + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), + /* XXX bit doesn't stick on Broadwater */ + IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); if (IS_GEN(i915, 4)) /* @@ -2037,9 +2049,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * they are already accustomed to from before contexts were * enabled. */ - wa_add(wal, ECOSKPD, - 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), - 0 /* XXX bit doesn't stick on Broadwater */); + wa_masked_add(wal, ECOSKPD, + _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), + 0 /* XXX bit doesn't stick on Broadwater */); } static void From patchwork Thu Apr 29 09:12:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 147E1C433ED for ; Thu, 29 Apr 2021 09:13:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A815461441 for ; Thu, 29 Apr 2021 09:13:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A815461441 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B770B6E1AA; Thu, 29 Apr 2021 09:13:07 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 799DC88A33; Thu, 29 Apr 2021 09:13:06 +0000 (UTC) IronPort-SDR: UVNzwCjH7o7fc0OOxrIExi5fqRFg3/9h5sygE8ujom44+uvAV4s2p6+xWF8U/xG6R5fblZUR48 6NoGrMwbGzFg== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011308" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011308" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:06 -0700 IronPort-SDR: OaUXyzmJrfMT9cPxg9pGev35Unzf5YvpK/cYBHOFK7QpAEtLJN1eDbX17gounrgcACTeKwAKMB DiO/aaRPieOQ== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298812" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:05 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 4/6] drm/i915/icl: Use appropriate helper for a masked workaround Date: Thu, 29 Apr 2021 10:12:52 +0100 Message-Id: <20210429091254.855248-5-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Instead of "open coding" WaEnableFloatBlendOptimization:icl via wa_write_clr_set, which should be for non-masked workarounds, add a new helper wa_masked_en_no_verify and use it. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a7abf9ca78ec..07579bb9b6a7 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -215,6 +215,12 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), val); } +static void +wa_masked_en_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 val) +{ + wa_masked_add(wal, reg, _MASKED_BIT_ENABLE(val), 0); +} + static void wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -595,10 +601,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); /* WaEnableFloatBlendOptimization:icl */ - wa_write_clr_set(wal, - GEN10_CACHE_MODE_SS, - 0, /* write-only, so skip validation */ - _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); + wa_masked_en_no_verify(wal, + GEN10_CACHE_MODE_SS, + FLOAT_BLEND_OPTIMIZATION_ENABLE); /* WaDisableGPGPUMidThreadPreemption:icl */ wa_masked_field_set(wal, GEN8_CS_CHICKEN1, From patchwork Thu Apr 29 09:12:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2E92C43600 for ; Thu, 29 Apr 2021 09:13:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D0AA66143E for ; Thu, 29 Apr 2021 09:13:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D0AA66143E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4A706EDCA; Thu, 29 Apr 2021 09:13:13 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3CC06E1A7; Thu, 29 Apr 2021 09:13:07 +0000 (UTC) IronPort-SDR: Q+Jk6EVnnsbPJoPrtv+K6+2cByLxh4Ph25262/MqQqY9V6PgJUu7tHti+vlpKDd11K2Hs/S5CZ 4LjTSv36ibDw== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011312" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011312" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:07 -0700 IronPort-SDR: mV26fsgb/uE6BmvjbqHYul0hFxA9Cqdwx4kEIDlmaHwsSB/n0kQeNFNHJRmuTVPnfWT+5A991M X+9BC8X5Za8w== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298816" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:06 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 5/6] drm/i915/icl: Stop conflating mask and readback verify Date: Thu, 29 Apr 2021 10:12:53 +0100 Message-Id: <20210429091254.855248-6-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Add a new helper wa_write_no_verify for Wa_1604278689:icl,ehl which is a write only register. This allows the mask to correctly reflect what bits the workaround writes versus which bits it will verify during read- back. In turn this will allow more safety checks to be added in a following patch. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 07579bb9b6a7..cd84c2a86787 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -186,6 +186,12 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) wa_write_clr_set(wal, reg, ~0, set); } +static void +wa_write_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 set) +{ + wa_add(wal, reg, ~0, set, 0); +} + static void wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) { @@ -616,9 +622,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_1604278689:icl,ehl */ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); - wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, - 0, /* write-only register; skip validation */ - 0xFFFFFFFF); + wa_write_no_verify(wal, IVB_FBC_RT_BASE_UPPER, 0xFFFFFFFF); /* Wa_1406306137:icl,ehl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); From patchwork Thu Apr 29 09:12:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12230869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15A8C433ED for ; Thu, 29 Apr 2021 09:13:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7623561441 for ; Thu, 29 Apr 2021 09:13:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7623561441 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 266F26EDCF; Thu, 29 Apr 2021 09:13:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FCB56E1F7; Thu, 29 Apr 2021 09:13:09 +0000 (UTC) IronPort-SDR: RNO0E70EXb+WGg0WnlRP/8BN95vGWLgjtbOhxHslNizzLvjDbX9lePkGHXDKV+wpFHbmn555x/ vqDi3TF0d8TA== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="197011313" X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="197011313" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:08 -0700 IronPort-SDR: ItxURtprWcBJYL9iAPCax8Jh86ScTwTG+knmoJHvLSjnNenmLk5RTAcxGjvrDasbLPntdafIsI L8xjZ+t5iXpA== X-IronPort-AV: E=Sophos;i="5.82,258,1613462400"; d="scan'208";a="537298821" Received: from gwaise-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.208.64]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 02:13:07 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 6/6] drm/i915: Add more checks when building workaround lists Date: Thu, 29 Apr 2021 10:12:54 +0100 Message-Id: <20210429091254.855248-7-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> References: <20210429091254.855248-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andres Calderon Jaramillo , dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin In current code we check that a workaround is not completely overwriting the existing one, but for instance partial conflict in some bits would get missed, as would problems involving masked registers, courtesy of the mask (wa->clr) being forced to zero for such registers and also being conflated with the readback verification. Now that previous patches have separated write masks from readback masks, and ensured all masked registers are correctly tagged as such, we can improve the verification checks to also detect partial conflicts, wrong masks and inconsistent register usage. Signed-off-by: Tvrtko Ursulin Reported-by: Andres Calderon Jaramillo --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 +++++++++++++++---- .../gpu/drm/i915/gt/intel_workarounds_types.h | 4 + .../gpu/drm/i915/gt/selftest_workarounds.c | 4 +- 3 files changed, 72 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cd84c2a86787..c82f165bdd8b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -52,8 +52,11 @@ * - Public functions to init or apply the given workaround type. */ -static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) +static void +wa_init_start(struct drm_i915_private *i915, struct i915_wa_list *wal, + const char *name, const char *engine_name) { + wal->i915 = i915; wal->name = name; wal->engine_name = engine_name; } @@ -81,6 +84,59 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } +static void +log_bad_wa(const struct i915_wa_list *wal, const struct i915_wa *wa, + const char *msg) +{ + drm_err(&wal->i915->drm, + "Discarding %s workaround! (reg=%x %s=%x set=%x)\n", + msg, i915_mmio_reg_offset(wa->reg), wa->clr ? "clear" : "mask", + wa->clr ?: wa->set >> 16, wa->set); +} + +static bool +check_conflict(const struct i915_wa_list *wal, + const struct i915_wa *old, + const struct i915_wa *new) +{ + u32 new_mask, old_mask, common, new_set, old_set; + + if (new->clr && !old->clr) { + log_bad_wa(wal, new, "mixed masked and regular"); + return true; + } + + if (new->clr) { + new_mask = new->clr; + old_mask = old->clr; + new_set = new->set; + old_set = old->set; + } else { + new_mask = new->set >> 16; + old_mask = old->set >> 16; + new_set = new->set & 0xffff; + old_set = old->set & 0xffff; + } + + if (new_set && (new_set & ~new_mask)) { + log_bad_wa(wal, new, "write outside the mask"); + return true; + } + + common = new_mask & old_mask; + if (common) { + if ((new_set & common) != (old_set & common)) { + log_bad_wa(wal, new, "conflicting"); + return true; + } else if (new_mask == old_mask) { + log_bad_wa(wal, new, "duplicate"); + return true; + } + } + + return false; +} + static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) { unsigned int addr = i915_mmio_reg_offset(wa->reg); @@ -118,18 +174,13 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) } else { wa_ = &wal->list[mid]; - if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { - DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), - wa_->clr, wa_->set); - - wa_->set &= ~wa->clr; + if (!check_conflict(wal, wa_, wa)) { + wal->wa_count++; + wa_->set |= wa->set; + wa_->clr |= wa->clr; + wa_->read |= wa->read; } - wal->wa_count++; - wa_->set |= wa->set; - wa_->clr |= wa->clr; - wa_->read |= wa->read; return; } } @@ -716,7 +767,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, if (engine->class != RENDER_CLASS) return; - wa_init_start(wal, name, engine->name); + wa_init_start(engine->i915, wal, name, engine->name); if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); @@ -1232,7 +1283,7 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915) { struct i915_wa_list *wal = &i915->gt_wa_list; - wa_init_start(wal, "GT", "global"); + wa_init_start(i915, wal, "GT", "global"); gt_init_workarounds(i915, wal); wa_init_finish(wal); } @@ -1575,7 +1626,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) struct drm_i915_private *i915 = engine->i915; struct i915_wa_list *w = &engine->whitelist; - wa_init_start(w, "whitelist", engine->name); + wa_init_start(engine->i915, w, "whitelist", engine->name); if (IS_DG1(i915)) dg1_whitelist_build(engine); @@ -2095,7 +2146,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine) if (INTEL_GEN(engine->i915) < 4) return; - wa_init_start(wal, "engine", engine->name); + wa_init_start(engine->i915, wal, "engine", engine->name); engine_init_workarounds(engine, wal); wa_init_finish(wal); } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h index c214111ea367..b6a9d1582a5c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h @@ -10,6 +10,8 @@ #include "i915_reg.h" +struct drm_i915_private; + struct i915_wa { i915_reg_t reg; u32 clr; @@ -18,6 +20,8 @@ struct i915_wa { }; struct i915_wa_list { + struct drm_i915_private *i915; + const char *name; const char *engine_name; struct i915_wa *list; diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 64937ec3f2dc..536cbe7889cc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -64,14 +64,14 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists) memset(lists, 0, sizeof(*lists)); - wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); + wa_init_start(gt->i915, &lists->gt_wa_list, "GT_REF", "global"); gt_init_workarounds(gt->i915, &lists->gt_wa_list); wa_init_finish(&lists->gt_wa_list); for_each_engine(engine, gt, id) { struct i915_wa_list *wal = &lists->engine[id].wa_list; - wa_init_start(wal, "REF", engine->name); + wa_init_start(gt->i915, wal, "REF", engine->name); engine_init_workarounds(engine, wal); wa_init_finish(wal);