From patchwork Tue May 4 05:09:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12237367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 073EFC433ED for ; Tue, 4 May 2021 05:10:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB9BC6105A for ; Tue, 4 May 2021 05:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229836AbhEDFLG (ORCPT ); Tue, 4 May 2021 01:11:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbhEDFLF (ORCPT ); Tue, 4 May 2021 01:11:05 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F6B9C061763; Mon, 3 May 2021 22:10:09 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id h7so4197715plt.1; Mon, 03 May 2021 22:10:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cv/4YiQsaH7ILIGN0BX1YpHcnVqqlfcrRxQBrip78ZU=; b=oEQ5Z53lf72w8mlKNkYHfqXIuXgInjxUe4K5glLj2T/9jM2PWYWx8iYRUXpSrwcCta P+2bWM/LD1oFoouhjuKC8FTp9nodACwV7MNdpgWgXXvo0iRRhzwcrSTL3yMmUpxS+0Ds 1k7ZdvFnHtbxtYGmOZlrsuNOeEk6CLZQ+deiROvVCXH4Xag44t3G6I1JN/CgNRv2zq5s eV24EPkS+C+CYNVInUkOYA1ra1HJ6syofdsv/mSs9ce7+EFn4qUM435HX6T/1J2YXjfL 8t77QZjqzNtKKmjSztCEO/avhBhKgOw6gqC13Qafp/uXvPCW3kjKI7/qk6oIDzCfDEyf 60Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cv/4YiQsaH7ILIGN0BX1YpHcnVqqlfcrRxQBrip78ZU=; b=B6vvTQvcf7bX6Vyn5OSfH+XZ4QBREwWY2iOV8yfwl4bSyqwrrnZ5K/2oiTES++5lZk iOAuv9CSJ78AjE2a0tqc6/pJgErjrjejUiWw3vRgTn6IJpJ5dLjN1zw2pl0hyEdDHyAv /JwIrzZSFOeICZY9X7TRAU/uUD0sH6Ism0Ria9M8GZ7hdBEuP6EkzJizSRYvPcXpUZ2H Ic4wofusekgw2idbkyFB9qmfJ3PaMQe7e0OycebjPkVUhyAkAi4skZrDoISo6h7OA4OE 3K7gEbassurmFKJemwRbG8lf/mK/b3FAzJj56A09plmuCDoACWVi+n51pdMw6NS2/3jc bGSA== X-Gm-Message-State: AOAM532Tg+fn6cJdcWbzwN8S+WbIW25pDXMh7c5cHjGTUhJR6vEzeOmA qQbgHmkVUhSB+e1OpNDwbHE= X-Google-Smtp-Source: ABdhPJy5zSTk208UZ0vHHKQZ7/sDLiiYH5Z+40uwBevEAH6t3ew+Pe4X49RpxXwWZNTZk3Kofmj5pQ== X-Received: by 2002:a17:902:ee94:b029:ed:4204:5e44 with SMTP id a20-20020a170902ee94b02900ed42045e44mr24001350pld.60.1620105009587; Mon, 03 May 2021 22:10:09 -0700 (PDT) Received: from localhost.localdomain ([63.143.61.57]) by smtp.gmail.com with ESMTPSA id 3sm10457815pff.132.2021.05.03.22.10.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 May 2021 22:10:09 -0700 (PDT) From: dillon.minfei@gmail.com To: festevam@gmail.com, shawnguo@kernel.org, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, arnd@arndb.de, olof@lixom.net, s.hauer@pengutronix.de, kernel@pengutronix.de, prabhakar.csengg@gmail.com, mchehab@kernel.org, mchehab+huawei@kernel.org Cc: krzysztof.kozlowski@canonical.com, krzk@kernel.org, robh+dt@kernel.org, linux@rempel-privat.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-media@vger.kernel.org, Dillon Min Subject: [PATCH v5 1/4] dt-bindings: add dasheng vendor prefix Date: Tue, 4 May 2021 13:09:50 +0800 Message-Id: <1620104993-5850-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> References: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dillon Min Add vendor prefix for DaSheng, Inc. Signed-off-by: Dillon Min Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- v5: - no code change, just change my git author name from lower case to higher case Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f6064d84a424..4ec28488c963 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -309,6 +309,8 @@ patternProperties: description: DPTechnics "^dragino,.*": description: Dragino Technology Co., Limited + "^ds,.*": + description: DaSheng, Inc. "^dserve,.*": description: dServe Technology B.V. "^dynaimage,.*": From patchwork Tue May 4 05:09:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12237369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15D92C433ED for ; Tue, 4 May 2021 05:10:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7FEF613BB for ; Tue, 4 May 2021 05:10:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229863AbhEDFLS (ORCPT ); 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Mon, 03 May 2021 22:10:15 -0700 (PDT) From: dillon.minfei@gmail.com To: festevam@gmail.com, shawnguo@kernel.org, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, arnd@arndb.de, olof@lixom.net, s.hauer@pengutronix.de, kernel@pengutronix.de, prabhakar.csengg@gmail.com, mchehab@kernel.org, mchehab+huawei@kernel.org Cc: krzysztof.kozlowski@canonical.com, krzk@kernel.org, robh+dt@kernel.org, linux@rempel-privat.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-media@vger.kernel.org, Dillon Min Subject: [PATCH v5 2/4] dt-bindings: arm: imx: Add i.mx6q DaSheng COM-9XX SBC Date: Tue, 4 May 2021 13:09:51 +0800 Message-Id: <1620104993-5850-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> References: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dillon Min The DaSheng Com-9xx is and ARM based signle board computer (SBC) featuring: - i.MX6Q - 2GiB LPDDR3 DRAM - 8GiB eMMC 5.0 FLASH - 4MiB SPI Flash - USB 2.0 Host/Device - Multiple multi-protocol RS232/RS485 Serial ports - microSD socket - 5V DC power input - HDMI1.4a,1080p@60 - RGMIIx1 Gigabit Ethernet - CSI0x1, connect with ov2659 Signed-off-by: Dillon Min Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- v5: - no code change, just change my git author name from lower case to higher case Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..598fb44c1bb8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -197,6 +197,7 @@ properties: - boundary,imx6q-nitrogen6x - compulab,cm-fx6 # CompuLab CM-FX6 - dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board + - ds,imx6q-sbc # Da Sheng COM-9XX Modules - embest,imx6q-marsboard # Embest MarS Board i.MX6Dual - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base From patchwork Tue May 4 05:09:52 2021 Content-Type: text/plain; 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Mon, 03 May 2021 22:10:22 -0700 (PDT) From: dillon.minfei@gmail.com To: festevam@gmail.com, shawnguo@kernel.org, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, arnd@arndb.de, olof@lixom.net, s.hauer@pengutronix.de, kernel@pengutronix.de, prabhakar.csengg@gmail.com, mchehab@kernel.org, mchehab+huawei@kernel.org Cc: krzysztof.kozlowski@canonical.com, krzk@kernel.org, robh+dt@kernel.org, linux@rempel-privat.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-media@vger.kernel.org, Dillon Min Subject: [PATCH v5 3/4] arm: dts: imx: Add i.mx6q DaSheng COM-9XX SBC board support Date: Tue, 4 May 2021 13:09:52 +0800 Message-Id: <1620104993-5850-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> References: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dillon Min The DaSheng Com-9xx is and ARM based signle board computer (SBC) featuring: - i.MX6Q - 2GiB LPDDR3 DRAM - 8GiB eMMC 5.0 FLASH - 4MiB SPI Flash - USB 2.0 Host/Device - Multiple multi-protocol RS232/RS485 Serial ports - microSD socket - 5V DC power input - HDMI1.4a,1080p@60 - RGMIIx1 Gigabit Ethernet - CSI0x1, connect with ov2659 Signed-off-by: Dillon Min --- v5: - no code change, just change my git author name from lower case to higher case arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-ds.dts | 17 ++ arch/arm/boot/dts/imx6qdl-ds.dtsi | 460 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 478 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-ds.dts create mode 100644 arch/arm/boot/dts/imx6qdl-ds.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a19c5ab9df84..425fe17ef7c1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -510,6 +510,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/imx6q-ds.dts new file mode 100644 index 000000000000..b0a63a133977 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-ds.dtsi" + +/ { + model = "DaSheng i.MX6 Quad Com-9xx Board"; + compatible = "ds,imx6q-sbc", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/imx6qdl-ds.dtsi new file mode 100644 index 000000000000..a2069caf4ea7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ds.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; + status = "okay"; + + m25p80: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov2659: camera@30 { + compatible = "ovti,ov2659"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2659>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xvclk"; + reg = <0x30>; + powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov2659_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + link-frequencies = /bits/ 64 <70000000>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + >; + }; + + pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov2659: ov2659grp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; From patchwork Tue May 4 05:09:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 12237373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8BFBC43462 for ; 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Mon, 03 May 2021 22:10:29 -0700 (PDT) Received: from localhost.localdomain ([63.143.61.57]) by smtp.gmail.com with ESMTPSA id 3sm10457815pff.132.2021.05.03.22.10.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 May 2021 22:10:28 -0700 (PDT) From: dillon.minfei@gmail.com To: festevam@gmail.com, shawnguo@kernel.org, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, arnd@arndb.de, olof@lixom.net, s.hauer@pengutronix.de, kernel@pengutronix.de, prabhakar.csengg@gmail.com, mchehab@kernel.org, mchehab+huawei@kernel.org Cc: krzysztof.kozlowski@canonical.com, krzk@kernel.org, robh+dt@kernel.org, linux@rempel-privat.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-media@vger.kernel.org, Dillon Min Subject: [PATCH v5 4/4] media: i2c: ov2659: Use clk_{prepare_enable,disable_unprepare}() to set xvclk on/off Date: Tue, 4 May 2021 13:09:53 +0800 Message-Id: <1620104993-5850-5-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> References: <1620104993-5850-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dillon Min On some platform(imx6q), xvclk might not switch on in advance, also for power save purpose, xvclk should not be always on. so, add clk_prepare_enable(), clk_disable_unprepare() in driver side to set xvclk on/off at proper stage. Add following changes: - add 'struct clk *clk;' in 'struct ov2659 {}' - enable xvclk in ov2659_power_on() - disable xvclk in ov2659_power_off() Signed-off-by: Dillon Min Acked-by: Lad Prabhakar --- v5: - no code change, just change my git author name from lower case to higher case - add 'Acked-by: Lad Prabhakar ' drivers/media/i2c/ov2659.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ov2659.c b/drivers/media/i2c/ov2659.c index 42f64175a6df..fb78a1cedc03 100644 --- a/drivers/media/i2c/ov2659.c +++ b/drivers/media/i2c/ov2659.c @@ -204,6 +204,7 @@ struct ov2659 { struct i2c_client *client; struct v4l2_ctrl_handler ctrls; struct v4l2_ctrl *link_frequency; + struct clk *clk; const struct ov2659_framesize *frame_size; struct sensor_register *format_ctrl_regs; struct ov2659_pll_ctrl pll; @@ -1270,6 +1271,8 @@ static int ov2659_power_off(struct device *dev) gpiod_set_value(ov2659->pwdn_gpio, 1); + clk_disable_unprepare(ov2659->clk); + return 0; } @@ -1278,9 +1281,17 @@ static int ov2659_power_on(struct device *dev) struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); struct ov2659 *ov2659 = to_ov2659(sd); + int ret; dev_dbg(&client->dev, "%s:\n", __func__); + ret = clk_prepare_enable(ov2659->clk); + if (ret) { + dev_err(&client->dev, "%s: failed to enable clock\n", + __func__); + return ret; + } + gpiod_set_value(ov2659->pwdn_gpio, 0); if (ov2659->resetb_gpio) { @@ -1425,7 +1436,6 @@ static int ov2659_probe(struct i2c_client *client) const struct ov2659_platform_data *pdata = ov2659_get_pdata(client); struct v4l2_subdev *sd; struct ov2659 *ov2659; - struct clk *clk; int ret; if (!pdata) { @@ -1440,11 +1450,11 @@ static int ov2659_probe(struct i2c_client *client) ov2659->pdata = pdata; ov2659->client = client; - clk = devm_clk_get(&client->dev, "xvclk"); - if (IS_ERR(clk)) - return PTR_ERR(clk); + ov2659->clk = devm_clk_get(&client->dev, "xvclk"); + if (IS_ERR(ov2659->clk)) + return PTR_ERR(ov2659->clk); - ov2659->xvclk_frequency = clk_get_rate(clk); + ov2659->xvclk_frequency = clk_get_rate(ov2659->clk); if (ov2659->xvclk_frequency < 6000000 || ov2659->xvclk_frequency > 27000000) return -EINVAL; @@ -1506,7 +1516,9 @@ static int ov2659_probe(struct i2c_client *client) ov2659->frame_size = &ov2659_framesizes[2]; ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs; - ov2659_power_on(&client->dev); + ret = ov2659_power_on(&client->dev); + if (ret < 0) + goto error; ret = ov2659_detect(sd); if (ret < 0)