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bh=mmh/HasNad45uSD7aVtNYaJgQvNsNvTGr9AsS2eHU3s=; b=h1Uir//lhsqzuIsJczmbwZ62vhxkh8Yq66avzODBVUC7KQQDFe3jLZ6RCBairGZsel 8HAlOv9rvkMqzW3jp4oZCRbVcQp3PlUyQ0zNtmkvy5v1HDmGvnTmF8FjAtBTB6E9RIwP bL1WKu11Rt3YVvKyx4qx3lcqMZKKbn3xZjB9ooIXBwZjMlC5opCOXVQGJCIQ4sG8bWPS Gs4cqzVCQVZiZroFOBrp+c70rU8cWa7Jo6Yj2okxVgH9oZejqgPT0voSfb2xfQlRCY/W sg/1NTbEjXEK7joPuHckTU3p1eZUnO8Eka75cjm8r5j6SmhJrLLgBqZu2XSF/vtwgmfY 9Heg== X-Gm-Message-State: AOAM5303LMLocoC669t5K2C9EHwfY+iLeCtk0OwAR9Q/eMS1PtC8KKzk /wzxtLKK0GpCjm1Enub6VSwWvnc= X-Google-Smtp-Source: ABdhPJzw6qkCrj56jDT5D8uW81ZD4tJiE+Ui+OuZHuGtY5kaBkPhqNLmwdNvnacQapTZCpHH4kBZ37M= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:c762:3d3c:b811:8e75]) (user=pcc job=sendgmr) by 2002:a0c:e9c6:: with SMTP id q6mr7701948qvo.15.1620358663196; Thu, 06 May 2021 20:37:43 -0700 (PDT) Date: Thu, 6 May 2021 20:37:25 -0700 Message-Id: <20210507033725.1479129-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.31.1.607.g51e8a6a459-goog Subject: [PATCH] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon Cc: Peter Collingbourne , Evgenii Stepanov , Andrey Konovalov , linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210506_203746_223928_C73B526E X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A valid implementation choice for the ChooseRandomNonExcludedTag() pseudocode function used by IRG is to behave in the same way as with GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR which must have a non-zero value in order for IRG to properly produce pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value on soft reset and thus may reset to 0. Therefore we must initialize RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves as expected. Signed-off-by: Peter Collingbourne Cc: stable@vger.kernel.org Link: https://linux-review.googlesource.com/id/I2b089b6c7d6f17ee37e2f0db7df5ad5bcc04526c --- arch/arm64/mm/proc.S | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 0a48191534ff..e8e1eaee4b3f 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -437,7 +437,7 @@ SYM_FUNC_START(__cpu_setup) mrs x10, ID_AA64PFR1_EL1 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4 cmp x10, #ID_AA64PFR1_MTE - b.lt 1f + b.lt 2f /* Normal Tagged memory type at the corresponding MAIR index */ mov x10, #MAIR_ATTR_NORMAL_TAGGED @@ -447,6 +447,19 @@ SYM_FUNC_START(__cpu_setup) mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) msr_s SYS_GCR_EL1, x10 + /* + * Initialize RGSR_EL1.SEED to a non-zero value. If the implementation + * chooses to implement GCR_EL1.RRND=1 in the same way as RRND=0 then + * the seed will be used as an LFSR, so it should be put onto the MLS. + */ + mrs x10, CNTVCT_EL0 + and x10, x10, #SYS_RGSR_EL1_SEED_MASK + cbnz x10, 1f + mov x10, #1 +1: + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT + msr_s SYS_RGSR_EL1, x10 + /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr @@ -454,7 +467,7 @@ SYM_FUNC_START(__cpu_setup) /* set the TCR_EL1 bits */ mov_q x10, TCR_KASAN_HW_FLAGS orr tcr, tcr, x10 -1: +2: #endif tcr_clear_errata_bits tcr, x9, x5