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bh=bUlmaJ3DBmOWkEirS18krGME+5oWQAss7CnV2FEmkzk=; b=ZhAdgpVqfHfOTAZZgSMYjefAwt+LHfm+962EN4NZI8vcBc+NhvbPrWd7wvXkUPqsWj FWBJieRWk1nb1/r8+/VEFVfzL2zSMNUs+N/0JBYBpIQqBoWMDhWO8rnETQdY+ocNb+ZP M2I6xjWYUgsdi2q0xwhUE7hqUoq3Tn1mP8wVrwCVassrgxHGRjW7vUC1pKkZ/tfGxake 5NennpsY+TXbVvSDOg57UbwKTyOdcBhBRZj89F3cFc9PvRcLJz9Mx7ryTJxM0kDA3t1+ UQD4+4EShd+xkcj968VyWE7fyOB42pQAM7TLSqB4OCnLut/C6M6dNSGUsTSU1A6XzSxD O/cA== X-Gm-Message-State: AOAM532cSt/uN/J/EcA7aoI6LerBTGUIkxTAlfDT3tO/atsKVtLSGNv2 SoEpVejKJaBUa+dhmwpimvmPbGM= X-Google-Smtp-Source: ABdhPJwbAM/J36vBWavQC7bJD9ssurzMNB9MreR8OB6/9spaIo9+Ja5ENG1xLTKBo6cktzQtD+Uopkk= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:f4bc:e4fd:1d93:96b2]) (user=pcc job=sendgmr) by 2002:a25:2bc1:: with SMTP id r184mr15777161ybr.51.1620413950833; Fri, 07 May 2021 11:59:10 -0700 (PDT) Date: Fri, 7 May 2021 11:59:05 -0700 Message-Id: <20210507185905.1745402-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.31.1.607.g51e8a6a459-goog Subject: [PATCH v2] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Mark Rutland Cc: Peter Collingbourne , Evgenii Stepanov , Andrey Konovalov , linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210507_115917_387084_DE055A2B X-CRM114-Status: GOOD ( 12.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A valid implementation choice for the ChooseRandomNonExcludedTag() pseudocode function used by IRG is to behave in the same way as with GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR which must have a non-zero value in order for IRG to properly produce pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value on soft reset and thus may reset to 0. Therefore we must initialize RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves as expected. Signed-off-by: Peter Collingbourne Fixes: 3b714d24ef17 ("arm64: mte: CPU feature detection and initial sysreg configuration") Cc: # 5.10 Link: https://linux-review.googlesource.com/id/I2b089b6c7d6f17ee37e2f0db7df5ad5bcc04526c Acked-by: Mark Rutland --- arch/arm64/mm/proc.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 0a48191534ff..97d7bcd8d4f2 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) msr_s SYS_GCR_EL1, x10 + /* + * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then + * RGSR_EL1.SEED must be non-zero for IRG to produce + * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we + * must initialize it. + */ + mrs x10, CNTVCT_EL0 + ands x10, x10, #SYS_RGSR_EL1_SEED_MASK + csinc x10, x10, xzr, ne + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT + msr_s SYS_RGSR_EL1, x10 + /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr