From patchwork Mon May 10 19:46:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12249261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92884C43460 for ; Mon, 10 May 2021 19:48:46 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C67261288 for ; Mon, 10 May 2021 19:48:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C67261288 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aN7lSEA/gFevGeuHreNN5p6sVWDuEztQsA9ibpQCFqw=; b=DidKNOcy9OftIraGf2X9QGJLJ 08RwUG0sqhiKnAe4ENnV8uaXIPruIPyZaPgy8AX1D5IfMubF/7UTDttTXYP411xkkK8e/PiAeSUl1 8MWo/XEAHBfIfj/8RJU1+2WZR0iMucN6t1g+TDSo3HUVaShJ72//MX/LBSNtMt0Mp8qlue0nYhTut gBaHTa0JF7QmLVUfpl6lU77fdBTc9061eNeKWTipoZYZocic76RORGejAVryrAnloGzDzQMdKup0p G5IgpCKph/kLEFm8Osx3y8a/t7+1BC8P8DZjY70o/DU3dJjBvyVbI++NSNXrdJoxbZWRbRWMVpZjq llIqT2fGw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrY-00FatX-Nv; Mon, 10 May 2021 19:46:44 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrQ-00FarX-23 for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 19:46:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=pAkTe+AR1PYdg3kzz2pRJGxqb07CGmK5UpnbOiu/3Eo=; b=LAIypbaEnVlJYN0EuqS0D+uBld pNjlQVZfcsA8awDaVKupwiCewkARekNf2rNxM9/q19DiTVtGseRwFnGIeUZZTUp6Dd9YWhpJ6H99C vPiYUHh6WM+dlQqns4u37hQeN7rEAUXe3EBdVLM3DZ57WeFFjvzCXOMGixgnp58ospup5ZUmeQlXP GC46MbMvRA9Baf6HkdK4B1DhOi73sQxcsAuw3rOmtq/H67//AMD18llgRMsjraJMTwXCLz6Kcubwf GD+w8yQ0S8hbDis849z5Y4jO+PWpY8kX7KRrwrFm5zYmkm+cw6AGDxGEngsAzQqC4jAcOuwO0ev2P Qabtcz4g==; Received: from mga12.intel.com ([192.55.52.136]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrN-00958g-KP for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 19:46:34 +0000 IronPort-SDR: /heR37UUTH3FyFuWQJAAWk4ekLw9/YQOCg2x2vfE2dYz/s4Tc7Pmdn1ho7YL+5pXT5U1AGS0ki f71tO5gNLLNg== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="178862760" X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="178862760" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 12:46:32 -0700 IronPort-SDR: skx2BXdixhd2BIcN0VDt47fjCUwxy0uOVBKUMtthJMfWfvLwEhsQ4tDuCEvcFEimNNJA3BV3Dm SXh/3aGkwKzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="621386418" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2021 12:46:29 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5850DD7; Mon, 10 May 2021 22:46:50 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Srinivas Neeli , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shubhrajyoti Datta , Michal Simek , Bartosz Golaszewski , Yury Norov , Rasmus Villemoes , Neeli Srinivas Subject: [PATCH v2 1/5] bitmap: Make bitmap_remap() and bitmap_bitremap() available to users Date: Mon, 10 May 2021 22:46:29 +0300 Message-Id: <20210510194633.11943-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> References: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_124633_695749_F795E3A1 X-CRM114-Status: GOOD ( 10.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the bitmap_remap() and bitmap_bitremap() are available only for CONFIG_NUMA=y case, while some users may benefit out of it and being independent to NUMA code. Make them available to users by moving out of ifdeffery and exporting for modules. Signed-off-by: Andy Shevchenko Tested-by: Neeli Srinivas Acked-by: Yury Norov Reviewed-by: Linus Walleij --- lib/bitmap.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/bitmap.c b/lib/bitmap.c index 74ceb02f45e3..7b6b2a67a6a6 100644 --- a/lib/bitmap.c +++ b/lib/bitmap.c @@ -784,8 +784,6 @@ int bitmap_parse(const char *start, unsigned int buflen, } EXPORT_SYMBOL(bitmap_parse); - -#ifdef CONFIG_NUMA /** * bitmap_pos_to_ord - find ordinal of set bit at given position in bitmap * @buf: pointer to a bitmap @@ -894,6 +892,7 @@ void bitmap_remap(unsigned long *dst, const unsigned long *src, set_bit(bitmap_ord_to_pos(new, n % w, nbits), dst); } } +EXPORT_SYMBOL(bitmap_remap); /** * bitmap_bitremap - Apply map defined by a pair of bitmaps to a single bit @@ -931,7 +930,9 @@ int bitmap_bitremap(int oldbit, const unsigned long *old, else return bitmap_ord_to_pos(new, n % w, bits); } +EXPORT_SYMBOL(bitmap_bitremap); +#ifdef CONFIG_NUMA /** * bitmap_onto - translate one bitmap relative to another * @dst: resulting translated bitmap From patchwork Mon May 10 19:46:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12249269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3552C433B4 for ; Mon, 10 May 2021 19:49:14 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9212B613DF for ; Mon, 10 May 2021 19:49:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9212B613DF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fyOiRtn4JKasqzLg+8gp6ObQbzOWDIZ12cuOBJkezsI=; b=MzjUw/qZolFoboqehw7mnjlQK kR0G/ESabtcroAu6cXSRk5o7Sct+nEI1x4hFNrXdyBPx48+lVBv8j2R2d+j3f139lc8vdqD4EDLg3 GCNoe+pVU33kIqW9LOevziWNjW6zqDKlxt8KJ7/rs9q7ZRuzPVnc/2EsGb6s0xy6aTrePeLPH0xCu RKxN8hccxU4lRpEFJ8GD+8qrzdACO0nRELwtqNcH7/qOGmEQ2rh93VbfG6GiAqqz58CXjeBMvutyE AUcLC4s7Gvudgit6dqU1ij/Ic7q+3q2qM0mmbjOfTeFDPlxuqa6a4cWkTAf9pnwsU4uKkAkDynl4o +jbsDNuhg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgBsQ-00Fb3G-0F; Mon, 10 May 2021 19:47:38 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBra-00FauF-6Y for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 19:46:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=k+pwEYXAB0nD8Mwl4kmjuSWAPb+ukFdXy2/WAhbdq8o=; b=CxAnAlF+PKllwVV08ae/WdbwL7 DIAVq6RmP6KQw1WmzSmMhsFr3ZNxUQTtCZJX1Yv8FucMtMBf9OUMVqdRB6sSr/XXaTbJMVPkPBClk Ov5bXx5nE62GQlcFDoavpdRcjuRXZTftVhHkj7bcBp8Dn/YCETxh1nNUIYDwZ2DlX8tW1crRs6FAh aaICFOvyf6PXp425reLSBkONq5/yo5QBVW2REMHlf5ToMtjjZB8StNQXDnTYPkmWmT4YPdMbKkDcF Q9g008o5HS7wZcpiclDQEpUw0jt3gvVrCYTs7WaKCTPT5akGRV3b+ibDxhZze+Y4yYFueHfOidDcO 3timiokg==; Received: from mga01.intel.com ([192.55.52.88]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrX-00959y-RE for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 19:46:45 +0000 IronPort-SDR: gZ6fBV+7PDNXEpsl8GuJQD0Y1k0NC5UK2S7iAMVw5LaqKOK8IBxRVAWWYsS1snqiDTmxldjmhI Yzc/urWmSByw== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="220225204" X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="220225204" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 12:46:36 -0700 IronPort-SDR: AdpFx4UlgHPf6vAd0jzLHCjErUuPp+cPqvtnfZhXnA7ynTyb6T1Nk0JuWV0dsBCrLO8VCbm2hp NqBhlc79EA2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="430025425" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 10 May 2021 12:46:32 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id CDE3812A; Mon, 10 May 2021 22:46:52 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Srinivas Neeli , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shubhrajyoti Datta , Michal Simek , Bartosz Golaszewski , Yury Norov , Rasmus Villemoes , Neeli Srinivas Subject: [PATCH v2 2/5] gpio: xilinx: Correct kernel doc for xgpio_probe() Date: Mon, 10 May 2021 22:46:30 +0300 Message-Id: <20210510194633.11943-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> References: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_124643_909492_FC83D954 X-CRM114-Status: GOOD ( 13.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Kernel doc validator complains: .../gpio-xilinx.c:556: warning: expecting prototype for xgpio_of_probe(). Prototype was for xgpio_probe() instead Correct as suggested by changing the name of the function in the doc.. Fixes: 749564ffd52d ("gpio/xilinx: Convert the driver to platform device interface") Signed-off-by: Andy Shevchenko Tested-by: Neeli Srinivas Reviewed-by: Michal Simek --- drivers/gpio/gpio-xilinx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index b411d3156e0b..136557e7dd3c 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -542,7 +542,7 @@ static void xgpio_irqhandler(struct irq_desc *desc) } /** - * xgpio_of_probe - Probe method for the GPIO device. + * xgpio_probe - Probe method for the GPIO device. * @pdev: pointer to the platform device * * Return: From patchwork Mon May 10 19:46:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12249263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3094C433ED for ; Mon, 10 May 2021 19:48:51 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 08DEB61432 for ; Mon, 10 May 2021 19:48:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 08DEB61432 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kMjVLEgI+cUO8PIKJWFuZs11jZwA4j4OdBcmnT0Kdxk=; b=AYvXhSGX9EYReKEa7ZV5AGtKK ixA+XROkvxvu2DFEshGdjlJbk1J7meHrS8I0Zs8jvSGXWu3Zof7ogeGBn/qHA2wiUxrosPTqLe0BP nG0J3vew0aLIMIjKYmyUxLbiafLObaidqJfqUwNjzJ5nWfO4yFpx03kZ/NyxbwhCqB0OvtnxcDDwd nKjMKHJtpXj6BrUuyvHzdRkGiuA6HAQGhV0Gtgxx4ZW4eZxYfzEFvsJqlZ3QfVREgUorjT7QZPJHD Kru0QcYqf4UIZThSibAxWIJH4AajH6jNWg5hl9t4WOe5icJecceVjHVgE9ut4LkZK7MH6mLHuvizK CgkiikUKw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrk-00FawM-I4; Mon, 10 May 2021 19:46:56 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrV-00FatB-Oy for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 19:46:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=NcHvo73ZD+JBjAiurXEmqn6HN7kLX5WiP07GvcQ4uy8=; b=h1xAUIRzgFePZ0VIGOMro4TbWJ kbWX8+bNUHy3AvW3lxbeOZiGer2YIShA2nQ/ydb9Vnc2KQvaDXkGOlsi3/P2btbW/Hi4qf7ge1e5t z1X9/kg3T/Bxa86Ickh/zGQ6j3/E+JiatRpX2vcCebeDxxTL63gkizqFdxzZt71YzqiHfvOHf5JDy 7t/CNFrTLkgQOrwss7wzL2kA5cOOuB93zsk7PkbyKYOnjrtCmxoS5FGI461SUQQxRdhIhrzUj4bbo ObVswtcUujleFaqYdvrYvvPHAgm6LRJ3zyhbD+Paxw6Frz1sQXhK2PSCHp857nSc+/5Z6tS2amBHB W2EY8ukw==; Received: from mga11.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrT-00959A-0a for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 19:46:40 +0000 IronPort-SDR: hQhpOD5ndwve7JLi0/bcdhHGD5iwdaq0qUR2UfBdLlVMT5WJbZ4G2qPE/wsG5nbqGEvaOpjIZU RKrOWHkTgZSw== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="196181156" X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="196181156" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 12:46:37 -0700 IronPort-SDR: wWi9F5HVRxBjqd7EgEWLiXjudAVJ2wqqtTKYQTJxq+IJlFQgh3HKdKp+f5gUWtFmSHAp6yreGL ZZoHynyaJuoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="609214218" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 10 May 2021 12:46:33 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 1EAF7D7; Mon, 10 May 2021 22:46:54 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Srinivas Neeli , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shubhrajyoti Datta , Michal Simek , Bartosz Golaszewski , Yury Norov , Rasmus Villemoes , Neeli Srinivas Subject: [PATCH v2 3/5] gpio: xilinx: Introduce xgpio_read_chan() / xgpio_write_chan() Date: Mon, 10 May 2021 22:46:31 +0300 Message-Id: <20210510194633.11943-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> References: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_124639_091353_2713185B X-CRM114-Status: GOOD ( 17.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the new helpers, i.e. xgpio_read_chan() / xgpio_write_chan(), the code is easier to read and maintain. No functional changes intended. Signed-off-by: Andy Shevchenko Tested-by: Neeli Srinivas --- drivers/gpio/gpio-xilinx.c | 68 +++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 136557e7dd3c..e6c78409ab3a 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -23,7 +23,8 @@ #define XGPIO_DATA_OFFSET (0x0) /* Data register */ #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ -#define XGPIO_CHANNEL_OFFSET 0x8 +#define XGPIO_CHANNEL0_OFFSET 0x0 +#define XGPIO_CHANNEL1_OFFSET 0x8 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ #define XGPIO_GIER_IE BIT(31) @@ -79,12 +80,26 @@ static inline int xgpio_index(struct xgpio_instance *chip, int gpio) return 0; } -static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio) +static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) { - if (xgpio_index(chip, gpio)) - return XGPIO_CHANNEL_OFFSET; + switch (ch) { + case 0: + return XGPIO_CHANNEL0_OFFSET; + case 1: + return XGPIO_CHANNEL1_OFFSET; + default: + return -EINVAL; + } +} - return 0; +static inline u32 xgpio_read_chan(struct xgpio_instance *chip, int reg, int ch) +{ + return xgpio_readreg(chip->regs + reg + xgpio_regoffset(chip, ch)); +} + +static inline void xgpio_write_chan(struct xgpio_instance *chip, int reg, int ch, u32 v) +{ + xgpio_writereg(chip->regs + reg + xgpio_regoffset(chip, ch), v); } static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) @@ -109,12 +124,13 @@ static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { struct xgpio_instance *chip = gpiochip_get_data(gc); + int index = xgpio_index(chip, gpio); + int offset = xgpio_offset(chip, gpio); u32 val; - val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio)); + val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); - return !!(val & BIT(xgpio_offset(chip, gpio))); + return !!(val & BIT(offset)); } /** @@ -141,8 +157,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) else chip->gpio_state[index] &= ~BIT(offset); - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_state[index]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -172,9 +187,8 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, break; /* Once finished with an index write it out to the register */ if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, + chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock, flags); index = xgpio_index(chip, i); spin_lock_irqsave(&chip->gpio_lock, flags); @@ -188,8 +202,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, } } - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -214,8 +227,7 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) /* Set the GPIO bit in shadow register and set direction as input */ chip->gpio_dir[index] |= BIT(offset); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); + xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -248,13 +260,11 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) chip->gpio_state[index] |= BIT(offset); else chip->gpio_state[index] &= ~BIT(offset); - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_state[index]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); /* Clear the GPIO bit in shadow register and set direction as output */ chip->gpio_dir[index] &= ~BIT(offset); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + - xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); + xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -267,16 +277,14 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) */ static void xgpio_save_regs(struct xgpio_instance *chip) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 0, chip->gpio_state[0]); + xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 0, chip->gpio_dir[0]); if (!chip->gpio_width[1]) return; - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, - chip->gpio_state[1]); - xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, - chip->gpio_dir[1]); + xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 1, chip->gpio_state[1]); + xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 1, chip->gpio_dir[1]); } static int xgpio_request(struct gpio_chip *chip, unsigned int offset) @@ -434,8 +442,7 @@ static void xgpio_irq_unmask(struct irq_data *irq_data) xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); /* Update GPIO IRQ read data before enabling interrupt*/ - val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET); + val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); chip->gpio_last_irq_read[index] = val; /* Enable per channel interrupt */ @@ -512,8 +519,7 @@ static void xgpio_irqhandler(struct irq_desc *desc) unsigned int irq; spin_lock_irqsave(&chip->gpio_lock, flags); - data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET); + data = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); rising_events = data & ~chip->gpio_last_irq_read[index] & chip->irq_enable[index] & From patchwork Mon May 10 19:46:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12249267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65D6DC433ED for ; Mon, 10 May 2021 19:49:12 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A1A561288 for ; Mon, 10 May 2021 19:49:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A1A561288 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1tYvSNbZOnk7g3zKsDV5XHbCFatZIVBBaN+O7W3T+wQ=; b=a0ZmAgZiIbN4NPRuD82qlWrQO EQR1iMLfgqROb70gPBYsLRibkJFjgsFN4xsnjm0vMDY0ylOU4npztEDVHPUceg+EFqsYQhA5+JymL hvMe5FdEyVomITz2PNOjSg/qa/sKFJN2PoDw1Sf4kmE49sJCNrcuqcgz0Ox/QmuDKsS/P3G37Cnwy r3aB2Sh57hX5wFi1JHxVIAB+yVINu30mt69VV0Wni1NdE1vmT7e11XeAiL2bAeQqtiC4NeZ+1DnNS nPfeVvMse5j7s1P2WQJ0w+ZoBDbzTe/xThw0jQul0KhJaKo24S46OaVqWTPQOPhBURy5Rx1Mhq3cN QePHWiOsA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgBsA-00Fazp-Aq; Mon, 10 May 2021 19:47:23 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrX-00FatG-9K for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 19:46:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=8bilSTqM3ORPZY9/J/lYpjWbIbmjZEMAcrsQrwSovvU=; b=TZEODgujratopx4755CQS4HjE/ bTOOuhjmC9WXc3iZdA5/svQp0RcXtX9VNxTwT7GCIt63zNkVthzWA4lNqmCW1gQWF3Wt5MZ3BHzhF NlMWT3EtjDyZnfs/2S5REYPclXEI7GhnXGJpI1DxwPKdVvaYdQo7mcR75GcaJqnIZG7mbGTOndbqm AtjPht6CYZZECvQVC/Hg4XTAY+gtFszNzsIpFG3zxle4U7dHVnC8eElkYlHkgJpbEfYdVAtx0gUIy 0iaSxqZIM81WmGu24137WxDgwgnB23bB5bwd6lGv7oqrl8/lUZyUswXkSZC7jiXNX0vvCy3sde0g6 Q4knlLzw==; Received: from mga11.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrT-00959P-IB for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 19:46:42 +0000 IronPort-SDR: kw5Yf2/wV7Q32QwyL8K5QZWwHoung8ozt61tUPc9L2lnXnOxjGE+kZzqyKr0s7Jc5Cg4Vzd1dQ sEXaPVELqt+g== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="196181160" X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="196181160" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 12:46:39 -0700 IronPort-SDR: ElVYfUiyKPfPtZRcFY7qi42VLfX+miMKPmdQY8Nx50WdvGTgaL8+WKsPQQmiNpkQMignxT0B/0 EQ+GaSrvUe3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="609214239" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 10 May 2021 12:46:34 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 53F0E142; Mon, 10 May 2021 22:46:55 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Srinivas Neeli , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shubhrajyoti Datta , Michal Simek , Bartosz Golaszewski , Yury Norov , Rasmus Villemoes , Neeli Srinivas Subject: [PATCH v2 4/5] gpio: xilinx: Switch to use bitmap APIs Date: Mon, 10 May 2021 22:46:32 +0300 Message-Id: <20210510194633.11943-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> References: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_124639_657661_15A42690 X-CRM114-Status: GOOD ( 24.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It seems that Xilinx GPIO driver operates with bit arrays longer than 32 and thus can leverage bitmap APIs for that. It makes code better to understand. The ->probe() function is modified to try read properties for both channels since is_dual check makes only sense for the amount of pins used for the second channel. On top of that kzalloc() guarantees zero initial values for the fields in the private data structure, hence drop unneeded conditionals and assignments. The change is inspired by Syed Nayyar Waris' ideas about bitmap API extension. Signed-off-by: Andy Shevchenko Tested-by: Neeli Srinivas --- drivers/gpio/gpio-xilinx.c | 356 ++++++++++++++++++------------------- 1 file changed, 178 insertions(+), 178 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index e6c78409ab3a..d2b7458b1d69 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -5,6 +5,7 @@ * Copyright 2008 - 2013 Xilinx, Inc. */ +#include #include #include #include @@ -44,40 +45,61 @@ * struct xgpio_instance - Stores information about GPIO device * @gc: GPIO chip * @regs: register block - * @gpio_width: GPIO width for every channel - * @gpio_state: GPIO write state shadow register - * @gpio_last_irq_read: GPIO read state register from last interrupt - * @gpio_dir: GPIO direction shadow register + * @hw_map: GPIO pin mapping on hardware side + * @sw_map: GPIO pin mapping on software side + * @state: GPIO write state shadow register + * @last_irq_read: GPIO read state register from last interrupt + * @dir: GPIO direction shadow register * @gpio_lock: Lock used for synchronization * @irq: IRQ used by GPIO device * @irqchip: IRQ chip - * @irq_enable: GPIO IRQ enable/disable bitfield - * @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield - * @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield + * @enable: GPIO IRQ enable/disable bitfield + * @rising_edge: GPIO IRQ rising edge enable/disable bitfield + * @falling_edge: GPIO IRQ falling edge enable/disable bitfield * @clk: clock resource for this driver */ struct xgpio_instance { struct gpio_chip gc; void __iomem *regs; - unsigned int gpio_width[2]; - u32 gpio_state[2]; - u32 gpio_last_irq_read[2]; - u32 gpio_dir[2]; + DECLARE_BITMAP(hw_map, 64); + DECLARE_BITMAP(sw_map, 64); + DECLARE_BITMAP(state, 64); + DECLARE_BITMAP(last_irq_read, 64); + DECLARE_BITMAP(dir, 64); spinlock_t gpio_lock; /* For serializing operations */ int irq; struct irq_chip irqchip; - u32 irq_enable[2]; - u32 irq_rising_edge[2]; - u32 irq_falling_edge[2]; + DECLARE_BITMAP(enable, 64); + DECLARE_BITMAP(rising_edge, 64); + DECLARE_BITMAP(falling_edge, 64); struct clk *clk; }; -static inline int xgpio_index(struct xgpio_instance *chip, int gpio) +static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) { - if (gpio >= chip->gpio_width[0]) - return 1; + return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); +} - return 0; +static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) +{ + return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); +} + +static inline u32 xgpio_get_value32(const unsigned long *map, int bit) +{ + const size_t index = BIT_WORD(bit); + const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); + + return (map[index] >> offset) & 0xFFFFFFFFul; +} + +static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) +{ + const size_t index = BIT_WORD(bit); + const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); + + map[index] &= ~(0xFFFFFFFFul << offset); + map[index] |= v << offset; } static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) @@ -92,22 +114,32 @@ static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) } } -static inline u32 xgpio_read_chan(struct xgpio_instance *chip, int reg, int ch) +static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) { - return xgpio_readreg(chip->regs + reg + xgpio_regoffset(chip, ch)); + void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); + xgpio_set_value32(a, bit, xgpio_readreg(addr)); } -static inline void xgpio_write_chan(struct xgpio_instance *chip, int reg, int ch, u32 v) +static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) { - xgpio_writereg(chip->regs + reg + xgpio_regoffset(chip, ch), v); + void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); + xgpio_writereg(addr, xgpio_get_value32(a, bit)); } -static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) +static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) { - if (xgpio_index(chip, gpio)) - return gpio - chip->gpio_width[0]; + int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); - return gpio; + for (bit = 0; bit <= lastbit ; bit += 32) + xgpio_read_ch(chip, reg, bit, a); +} + +static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) +{ + int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); + + for (bit = 0; bit <= lastbit ; bit += 32) + xgpio_write_ch(chip, reg, bit, a); } /** @@ -124,13 +156,12 @@ static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); - u32 val; + int bit = xgpio_to_bit(chip, gpio); + DECLARE_BITMAP(state, 64); - val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); + xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); - return !!(val & BIT(offset)); + return test_bit(bit, state); } /** @@ -146,18 +177,14 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signal and set its direction to output */ - if (val) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); + __assign_bit(bit, chip->state, val); - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); + xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -174,35 +201,22 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { + DECLARE_BITMAP(hw_mask, 64); + DECLARE_BITMAP(hw_bits, 64); + DECLARE_BITMAP(state, 64); unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; + + bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); + bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); spin_lock_irqsave(&chip->gpio_lock, flags); - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock, flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock, flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } - } + bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); + xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); + + bitmap_copy(chip->state, state, 64); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -220,14 +234,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ - chip->gpio_dir[index] |= BIT(offset); - xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]); + __set_bit(bit, chip->dir); + xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -250,21 +263,17 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, gpio); - int offset = xgpio_offset(chip, gpio); + int bit = xgpio_to_bit(chip, gpio); spin_lock_irqsave(&chip->gpio_lock, flags); /* Write state of GPIO signal */ - if (val) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, index, chip->gpio_state[index]); + __assign_bit(bit, chip->state, val); + xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); /* Clear the GPIO bit in shadow register and set direction as output */ - chip->gpio_dir[index] &= ~BIT(offset); - xgpio_write_chan(chip, XGPIO_TRI_OFFSET, index, chip->gpio_dir[index]); + __clear_bit(bit, chip->dir); + xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -277,14 +286,8 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) */ static void xgpio_save_regs(struct xgpio_instance *chip) { - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 0, chip->gpio_state[0]); - xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 0, chip->gpio_dir[0]); - - if (!chip->gpio_width[1]) - return; - - xgpio_write_chan(chip, XGPIO_DATA_OFFSET, 1, chip->gpio_state[1]); - xgpio_write_chan(chip, XGPIO_TRI_OFFSET, 1, chip->gpio_dir[1]); + xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); + xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); } static int xgpio_request(struct gpio_chip *chip, unsigned int offset) @@ -399,18 +402,17 @@ static void xgpio_irq_mask(struct irq_data *irq_data) unsigned long flags; struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); + int bit = xgpio_to_bit(chip, irq_offset); + u32 mask = BIT(bit / 32), temp; spin_lock_irqsave(&chip->gpio_lock, flags); - chip->irq_enable[index] &= ~BIT(offset); + __clear_bit(bit, chip->enable); - if (!chip->irq_enable[index]) { + if (xgpio_get_value32(chip->enable, bit) == 0) { /* Disable per channel interrupt */ - u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); - - temp &= ~BIT(index); + temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); + temp &= ~mask; xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); } spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -425,29 +427,26 @@ static void xgpio_irq_unmask(struct irq_data *irq_data) unsigned long flags; struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); - u32 old_enable = chip->irq_enable[index]; + int bit = xgpio_to_bit(chip, irq_offset); + u32 old_enable = xgpio_get_value32(chip->enable, bit); + u32 mask = BIT(bit / 32), val; spin_lock_irqsave(&chip->gpio_lock, flags); - chip->irq_enable[index] |= BIT(offset); + __set_bit(bit, chip->enable); - if (!old_enable) { + if (old_enable == 0) { /* Clear any existing per-channel interrupts */ - u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & - BIT(index); - - if (val) - xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); + val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + val &= mask; + xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); /* Update GPIO IRQ read data before enabling interrupt*/ - val = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); - chip->gpio_last_irq_read[index] = val; + xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); /* Enable per channel interrupt */ val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); - val |= BIT(index); + val |= mask; xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); } @@ -466,8 +465,7 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) { struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); int irq_offset = irqd_to_hwirq(irq_data); - int index = xgpio_index(chip, irq_offset); - int offset = xgpio_offset(chip, irq_offset); + int bit = xgpio_to_bit(chip, irq_offset); /* * The Xilinx GPIO hardware provides a single interrupt status @@ -477,16 +475,16 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) */ switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_BOTH: - chip->irq_rising_edge[index] |= BIT(offset); - chip->irq_falling_edge[index] |= BIT(offset); + __set_bit(bit, chip->rising_edge); + __set_bit(bit, chip->falling_edge); break; case IRQ_TYPE_EDGE_RISING: - chip->irq_rising_edge[index] |= BIT(offset); - chip->irq_falling_edge[index] &= ~BIT(offset); + __set_bit(bit, chip->rising_edge); + __clear_bit(bit, chip->falling_edge); break; case IRQ_TYPE_EDGE_FALLING: - chip->irq_rising_edge[index] &= ~BIT(offset); - chip->irq_falling_edge[index] |= BIT(offset); + __clear_bit(bit, chip->rising_edge); + __set_bit(bit, chip->falling_edge); break; default: return -EINVAL; @@ -503,45 +501,45 @@ static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) static void xgpio_irqhandler(struct irq_desc *desc) { struct xgpio_instance *chip = irq_desc_get_handler_data(desc); + struct gpio_chip *gc = &chip->gc; struct irq_chip *irqchip = irq_desc_get_chip(desc); - u32 num_channels = chip->gpio_width[1] ? 2 : 1; - u32 offset = 0, index; - u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + DECLARE_BITMAP(rising, 64); + DECLARE_BITMAP(falling, 64); + DECLARE_BITMAP(all, 64); + int irq_offset; + u32 status; + u32 bit; + unsigned long flags; + status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); chained_irq_enter(irqchip, desc); - for (index = 0; index < num_channels; index++) { - if ((status & BIT(index))) { - unsigned long rising_events, falling_events, all_events; - unsigned long flags; - u32 data, bit; - unsigned int irq; - - spin_lock_irqsave(&chip->gpio_lock, flags); - data = xgpio_read_chan(chip, XGPIO_DATA_OFFSET, index); - rising_events = data & - ~chip->gpio_last_irq_read[index] & - chip->irq_enable[index] & - chip->irq_rising_edge[index]; - falling_events = ~data & - chip->gpio_last_irq_read[index] & - chip->irq_enable[index] & - chip->irq_falling_edge[index]; - dev_dbg(chip->gc.parent, - "IRQ chan %u rising 0x%lx falling 0x%lx\n", - index, rising_events, falling_events); - all_events = rising_events | falling_events; - chip->gpio_last_irq_read[index] = data; - spin_unlock_irqrestore(&chip->gpio_lock, flags); - - for_each_set_bit(bit, &all_events, 32) { - irq = irq_find_mapping(chip->gc.irq.domain, - offset + bit); - generic_handle_irq(irq); - } - } - offset += chip->gpio_width[index]; + + spin_lock_irqsave(&chip->gpio_lock, flags); + + xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); + + bitmap_complement(rising, chip->last_irq_read, 64); + bitmap_and(rising, rising, all, 64); + bitmap_and(rising, rising, chip->enable, 64); + bitmap_and(rising, rising, chip->rising_edge, 64); + + bitmap_complement(falling, all, 64); + bitmap_and(falling, falling, chip->last_irq_read, 64); + bitmap_and(falling, falling, chip->enable, 64); + bitmap_and(falling, falling, chip->falling_edge, 64); + + bitmap_copy(chip->last_irq_read, all, 64); + bitmap_or(all, rising, falling, 64); + + spin_unlock_irqrestore(&chip->gpio_lock, flags); + + dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); + + for_each_set_bit(bit, all, 64) { + irq_offset = xgpio_from_bit(chip, bit); + generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset)); } chained_irq_exit(irqchip, desc); @@ -562,6 +560,9 @@ static int xgpio_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; u32 is_dual = 0; u32 cells = 2; + u32 width[2]; + u32 state[2]; + u32 dir[2]; struct gpio_irq_chip *girq; u32 temp; @@ -571,13 +572,25 @@ static int xgpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, chip); + /* First, check if the device is dual-channel */ + of_property_read_u32(np, "xlnx,is-dual", &is_dual); + + /* Setup defaults */ + memset32(width, 0, ARRAY_SIZE(width)); + memset32(state, 0, ARRAY_SIZE(state)); + memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); + /* Update GPIO state shadow register with default value */ - if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0])) - chip->gpio_state[0] = 0x0; + of_property_read_u32(np, "xlnx,dout-default", &state[0]); + of_property_read_u32(np, "xlnx,dout-default-2", &state[1]); + + bitmap_from_arr32(chip->state, state, 64); /* Update GPIO direction shadow register with default value */ - if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) - chip->gpio_dir[0] = 0xFFFFFFFF; + of_property_read_u32(np, "xlnx,tri-default", &dir[0]); + of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]); + + bitmap_from_arr32(chip->dir, dir, 64); /* Update cells with gpio-cells value */ if (of_property_read_u32(np, "#gpio-cells", &cells)) @@ -592,42 +605,29 @@ static int xgpio_probe(struct platform_device *pdev) * Check device node and parent device node for device width * and assume default width of 32 */ - if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) - chip->gpio_width[0] = 32; + if (of_property_read_u32(np, "xlnx,gpio-width", &width[0])) + width[0] = 32; - if (chip->gpio_width[0] > 32) + if (width[0] > 32) return -EINVAL; - spin_lock_init(&chip->gpio_lock); + if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1])) + width[1] = 32; - if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) - is_dual = 0; - - if (is_dual) { - /* Update GPIO state shadow register with default value */ - if (of_property_read_u32(np, "xlnx,dout-default-2", - &chip->gpio_state[1])) - chip->gpio_state[1] = 0x0; - - /* Update GPIO direction shadow register with default value */ - if (of_property_read_u32(np, "xlnx,tri-default-2", - &chip->gpio_dir[1])) - chip->gpio_dir[1] = 0xFFFFFFFF; - - /* - * Check device node and parent device node for device width - * and assume default width of 32 - */ - if (of_property_read_u32(np, "xlnx,gpio2-width", - &chip->gpio_width[1])) - chip->gpio_width[1] = 32; - - if (chip->gpio_width[1] > 32) - return -EINVAL; - } + if (width[1] > 32) + return -EINVAL; + + /* Setup software pin mapping */ + bitmap_set(chip->sw_map, 0, width[0] + width[1]); + + /* Setup hardware pin mapping */ + bitmap_set(chip->hw_map, 0, width[0]); + bitmap_set(chip->hw_map, 32, width[1]); + + spin_lock_init(&chip->gpio_lock); chip->gc.base = -1; - chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; + chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); chip->gc.parent = &pdev->dev; chip->gc.direction_input = xgpio_dir_in; chip->gc.direction_output = xgpio_dir_out; From patchwork Mon May 10 19:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12249265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C603C433ED for ; Mon, 10 May 2021 19:49:05 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A48DB613DF for ; Mon, 10 May 2021 19:49:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A48DB613DF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bU3cEyfuV39Uz8pin9s9cDyt1rSq7na01n/Tsqrqino=; b=jVgYpCwP8c7S01lHuPR8Jd41B ZzE5lc4aGtfJHnATUj2NghxnBGGrfEdVBle+tT+7Gsns0t3c/eVd5G1pAifiTJayIN32UARU3tWJ3 HZtYtR+46XCoz+wVENfb8LXFmYnPiLu+YiXIi6OVJs+gx5QWEZ2xHnlbHQaUc9NW9FTF6PqhdAVY8 BNmvsV2VC4YD9EJtITJvrMN4lshTxSiKbCX6xMNM9ENmIDiJT3CCJAIthAUTu9IyTVX91QMr9nf3G vVS17nKNrBq9y2jDvHCB8iC88MYIoIei3aloVq72of+AhgMEZaUNasMsHA76rfAtGrDppyikNaf8Y rNMTf2W0Q==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrv-00FaxW-D6; Mon, 10 May 2021 19:47:07 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrW-00FatE-Ss for linux-arm-kernel@desiato.infradead.org; Mon, 10 May 2021 19:46:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=buP75qmnMp2WS36AZ/PhTvBmVRDzbiPXTrnxj3aRe+M=; b=xrZ7NWtvAXJhOdXPHl5RfW9bS5 Q/6BIskardmmWPJTvQ/U6JS9df0BNPH0IJawP3A//BeiwGHmYPaCMSSlec6ws+7XRuuzSgOxbmajQ mJiVIb8VT5Gu1bN1bdLcehRg+6vmug2Vrc8jahyldc0aPvAb4H/pvo3oorKUYVvgNE3KpLsnofeSv vq1eUwtQUROHnhauktWjdHYg9NPA8itBedItjQNNYzSwKjpRZfxD69efNw9oHL9ePgk2tVN78vazH O7ofCFHIyq7gV9Hr67+ODtYMx7fsg/9pImUdtkFcJY85fJj5hkFqd5EBruDxBV5ak1i8QfKZhxbEM fSzOaiMw==; Received: from mga06.intel.com ([134.134.136.31]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgBrT-00959Q-TI for linux-arm-kernel@lists.infradead.org; Mon, 10 May 2021 19:46:41 +0000 IronPort-SDR: nisFQDBrRft8x8rKlMGEtPocFZcu7SLKeH7DV0ebOMexSqoExBSHpZBMDMeQyxdF04BnNaQrqn n/GztHfxftmw== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="260537056" X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="260537056" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 12:46:39 -0700 IronPort-SDR: buGZfkBkjYKxe70vzI2EcwTs2CzIQFx9sTc4F0k1O0OqkDCpdVanWV0E0+m70/ySmcH3kSXbCr 1C5kiKBllJhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,288,1613462400"; d="scan'208";a="391096812" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 10 May 2021 12:46:36 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id DEA15147; Mon, 10 May 2021 22:46:56 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Srinivas Neeli , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shubhrajyoti Datta , Michal Simek , Bartosz Golaszewski , Yury Norov , Rasmus Villemoes , Neeli Srinivas Subject: [PATCH v2 5/5] gpio: xilinx: No need to disable IRQs in the handler Date: Mon, 10 May 2021 22:46:33 +0300 Message-Id: <20210510194633.11943-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> References: <20210510194633.11943-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_124640_000159_B12B80B1 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, it is not a problem because IRQ framework keeps interrupt disabled there as well. Remove disabling IRQ part in the handler. Signed-off-by: Andy Shevchenko Tested-by: Neeli Srinivas --- drivers/gpio/gpio-xilinx.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index d2b7458b1d69..109b32104867 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -509,14 +509,13 @@ static void xgpio_irqhandler(struct irq_desc *desc) int irq_offset; u32 status; u32 bit; - unsigned long flags; status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); chained_irq_enter(irqchip, desc); - spin_lock_irqsave(&chip->gpio_lock, flags); + spin_lock(&chip->gpio_lock); xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); @@ -533,7 +532,7 @@ static void xgpio_irqhandler(struct irq_desc *desc) bitmap_copy(chip->last_irq_read, all, 64); bitmap_or(all, rising, falling, 64); - spin_unlock_irqrestore(&chip->gpio_lock, flags); + spin_unlock(&chip->gpio_lock); dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);