From patchwork Mon May 10 21:36:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 12249351 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FB7DC433B4 for ; Mon, 10 May 2021 21:37:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C42E060FE7 for ; Mon, 10 May 2021 21:37:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230165AbhEJViU (ORCPT ); Mon, 10 May 2021 17:38:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232082AbhEJViU (ORCPT ); Mon, 10 May 2021 17:38:20 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8217FC061574 for ; Mon, 10 May 2021 14:37:14 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id i9so18994387lfe.13 for ; Mon, 10 May 2021 14:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F6J3or1SAc2IwbCi7ek22wAk4JQQDxayXS5WD4oDLPI=; b=lE6oCeNQIFAYQCXkjbLN8qm+ZDNB0WzeGqkdDga+tgD182oCEq2WBp0cmHKs8ftSAC 3bMIL76svxmDEREcwiLrvKxJE3mek/kA2skt9+n0MUyGMThPdJ4DGBZQdgNrCoXJFyzO +56mgI+BGcMRd1/75EUxVJO6QLthMKDaC3uQ2eEygCdZioulTyGdlI3Rs8hWpe4kSPng HrureIRp9Ye4m5R81UNI1mO7Qfdzzoof01JLZalI2jjWv+8ekQziZ9okS5xIGT4EcEH8 NZ91I2FwmRHuGlp3jn/sP+KCxtElM55/BHshgMS4roYqDjzW8i+pa3d0snAfMjaEwrB5 3Fkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F6J3or1SAc2IwbCi7ek22wAk4JQQDxayXS5WD4oDLPI=; b=GK+Xytxa7pFjUnpkSGzQrpf2JVEhdj0BAI43QbJoYT5PekG6FJS+FhoZaSGovLjrip CmUIyRLCmSJa7lMhI/kGshwqAzPvOcVmUa+8JPjrg97MfDjeUQECCm/fGoO6VCryFb0M mTETBAp5sIq7LzNQy/vm1PL1fcstSoPbVfVi0cBQeOYBE69zcsjJ0p1MxJimtXL4fNDR xOy+VxmiG2eZi1G2J3Owsg0aEajgck0X1tPkwLDcdPW/GUVVg9yDCoLlfXRaRSvnfnSR jNpWORM6dwQXxBExWv8xEC84JHffFIYoSUfZk3qwhUe6N6LKLO11T+DYO6YMICF29hKB 8z1Q== X-Gm-Message-State: AOAM531XNysjIBfy/fBzhm0/K5baCKZSGMXW7yzZq1uOnXo+jmed6PPY XpUUhJQPgB+cQVuLGvOH2qlkzWWG+9Nmag== X-Google-Smtp-Source: ABdhPJz2rwXNay1bX9Q1q81JNxvHlgP0BkhIIeka7GD+siDu87gDz8qKAGwgqBEapng921QvJsYY5w== X-Received: by 2002:a05:6512:b83:: with SMTP id b3mr18378648lfv.312.1620682632823; Mon, 10 May 2021 14:37:12 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id q19sm1091660lff.16.2021.05.10.14.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 14:37:09 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa , Arnd Bergmann , Linus Walleij Subject: [PATCH 1/3] crypto: ixp4xx: convert to platform driver Date: Mon, 10 May 2021 23:36:32 +0200 Message-Id: <20210510213634.600866-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Arnd Bergmann The ixp4xx_crypto driver traditionally registers a bare platform device without attaching it to a driver, and detects the hardware at module init time by reading an SoC specific hardware register. Change this to the conventional method of registering the platform device from the platform code itself when the device is present, turning the module_init/module_exit functions into probe/release driver callbacks. This enables compile-testing as well as potentially having ixp4xx coexist with other ARMv5 platforms in the same kernel in the future. Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij Tested-by: Corentin Labbe --- Herbert, David: I am looking for an ACK to take this into the ARM SoC tree as we want to change more stuff in the machine at the same time that we want to resolve there. --- arch/arm/mach-ixp4xx/common.c | 26 ++++++++++++++++++++++++ drivers/crypto/Kconfig | 3 ++- drivers/crypto/ixp4xx_crypto.c | 37 ++++++++++++---------------------- 3 files changed, 41 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 000f672a94c9..007a44412e24 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -233,12 +233,38 @@ static struct platform_device *ixp46x_devices[] __initdata = { unsigned long ixp4xx_exp_bus_size; EXPORT_SYMBOL(ixp4xx_exp_bus_size); +static struct platform_device_info ixp_dev_info __initdata = { + .name = "ixp4xx_crypto", + .id = 0, + .dma_mask = DMA_BIT_MASK(32), +}; + +static int __init ixp_crypto_register(void) +{ + struct platform_device *pdev; + + if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | + IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { + printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); + return -ENODEV; + } + + pdev = platform_device_register_full(&ixp_dev_info); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; +} + void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX)) + ixp_crypto_register(); + if (cpu_is_ixp46x()) { int region; diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 9a4c275a1335..aa389e741876 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -324,7 +324,8 @@ config CRYPTO_DEV_TALITOS2 config CRYPTO_DEV_IXP4XX tristate "Driver for IXP4xx crypto hardware acceleration" - depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE + depends on IXP4XX_QMGR && IXP4XX_NPE + depends on ARCH_IXP4XX || COMPILE_TEST select CRYPTO_LIB_DES select CRYPTO_AEAD select CRYPTO_AUTHENC diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 0616e369522e..879b93927e2a 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -224,8 +224,6 @@ static dma_addr_t crypt_phys; static int support_aes = 1; -#define DRIVER_NAME "ixp4xx_crypto" - static struct platform_device *pdev; static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt) @@ -432,11 +430,6 @@ static int init_ixp_crypto(struct device *dev) int ret = -ENODEV; u32 msg[2] = { 0, 0 }; - if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | - IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { - printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); - return ret; - } npe_c = npe_request(NPE_ID); if (!npe_c) return ret; @@ -1364,26 +1357,17 @@ static struct ixp_aead_alg ixp4xx_aeads[] = { #define IXP_POSTFIX "-ixp4xx" -static const struct platform_device_info ixp_dev_info __initdata = { - .name = DRIVER_NAME, - .id = 0, - .dma_mask = DMA_BIT_MASK(32), -}; - -static int __init ixp_module_init(void) +static int ixp_crypto_probe(struct platform_device *_pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i, err; - pdev = platform_device_register_full(&ixp_dev_info); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); + pdev = _pdev; err = init_ixp_crypto(&pdev->dev); - if (err) { - platform_device_unregister(pdev); + if (err) return err; - } + for (i=0; i< num; i++) { struct skcipher_alg *cra = &ixp4xx_algos[i].crypto; @@ -1456,7 +1440,7 @@ static int __init ixp_module_init(void) return 0; } -static void __exit ixp_module_exit(void) +static int ixp_crypto_remove(struct platform_device *pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i; @@ -1471,11 +1455,16 @@ static void __exit ixp_module_exit(void) crypto_unregister_skcipher(&ixp4xx_algos[i].crypto); } release_ixp_crypto(&pdev->dev); - platform_device_unregister(pdev); + + return 0; } -module_init(ixp_module_init); -module_exit(ixp_module_exit); +static struct platform_driver ixp_crypto_driver = { + .probe = ixp_crypto_probe, + .remove = ixp_crypto_remove, + .driver = { .name = "ixp4xx_crypto" }, +}; +module_platform_driver(ixp_crypto_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Christian Hohnstaedt "); From patchwork Mon May 10 21:36:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 12249353 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53809C433ED for ; Mon, 10 May 2021 21:37:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 368E06146E for ; Mon, 10 May 2021 21:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232530AbhEJVic (ORCPT ); Mon, 10 May 2021 17:38:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232461AbhEJVib (ORCPT ); Mon, 10 May 2021 17:38:31 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 868ADC06175F for ; Mon, 10 May 2021 14:37:25 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id w4so22604603ljw.9 for ; Mon, 10 May 2021 14:37:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CUvl66hkrXjCfS0+MBNd5h698LfIk3X/AE2d1CppJVM=; b=dID648OqvC6fpie5hQioI8+BavivqlqN/iNII27m9wwegXP/fBT4072x9hLy3uheNZ Akb5f9TqDODDJATz4d4J69ahd/nnqkbveL5jhMhJ1sxubL/xnqz2GxrdSbVDjneff+Zc bgmTpI+CJl6O6N39Iyj/olaT6kqY+L3lLzRCOUKz506ZhSDBESm1OUT5BbInTSIkJ2L8 +MbyeIezWVuAYYloHmQnPEfjhQYK5EKcQq2ltvzLjTIrI4NsSIhNE882WX9bR9zW7xRl TDE/IUx4DrHnHVWcLgu0jyzgvgNiXmU+W4ZlEDa+Tq+AAIoiA0HeIT2gr03b8AebJcDL Hz9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CUvl66hkrXjCfS0+MBNd5h698LfIk3X/AE2d1CppJVM=; b=hyEgOyRbrtSu12m/vRombiIPYGFXARc3Y8+SW+IRywHfI/C4Tkns/QPhYiBlwNiJvz b6DYRIbXAo3Ml7vt9vAJLv6FaNAEeCURAU4JW28kRlqKty7qm99irY6JHwNRU78Y82q0 DGbuO95Jt+oPLkEYNNJxvgA/ypkNGb3Ubecjlt2v4gwyqREy5/Qhztvg5ERT3BYOLy1I zezKt9aRWg4T33k1pncwoOIl9bBck/9HOUeacgtRkiQ2lCikVK33gzb81rXDiy4YxKzq 64UQgOT1yLgEpiadKm4tpZifFzUulPIRrM5E/BlWxpOd0iWXUmjxFhqERAcNbtzRhelW GBsA== X-Gm-Message-State: AOAM530BWEQOQNwVfiY2smBPhMTRXmlDFDFufkMurLudg23zEYEJIT53 MI1TjCc2SuUmrszIst7VHssjSSqkvpjhfw== X-Google-Smtp-Source: ABdhPJztyPIQuhm88sYU82lPmNBi5JTeQ9tTCbuESFnM9KRry16gs7IhDgtCmSJQBXwLzA3c+zmPJQ== X-Received: by 2002:a2e:8797:: with SMTP id n23mr2063883lji.248.1620682643921; Mon, 10 May 2021 14:37:23 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id q19sm1091660lff.16.2021.05.10.14.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 14:37:22 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa , Arnd Bergmann , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 2/3] crypto: ixp4xx: Add DT bindings Date: Mon, 10 May 2021 23:36:33 +0200 Message-Id: <20210510213634.600866-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510213634.600866-1-linus.walleij@linaro.org> References: <20210510213634.600866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This adds device tree bindings for the ixp4xx crypto engine. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Herbert, David: This can be applied separately once we are happy with the bindings, alternatively it can be merged with the support code into ARM SoC. --- .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml new file mode 100644 index 000000000000..28d75f4f9a76 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx cryptographic engine + +maintainers: + - Linus Walleij + +description: | + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE + (Network Processing Engine). Since it is not a device on its own + it is defined as a subnode of the NPE, if crypto support is + available on the platform. + +properties: + compatible: + const: intel,ixp4xx-crypto + + intel,npe-handle: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the NPE this ethernet instance is using + and the instance to use in the second cell + + queue-rx: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the RX queue on the NPE + + queue-txready: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the TX READY queue on the NPE + +required: + - compatible + - intel,npe-handle + - queue-rx + - queue-txready + +additionalProperties: false + +examples: + - | + npe: npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; + }; From patchwork Mon May 10 21:36:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 12249355 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FEDBC433ED for ; Mon, 10 May 2021 21:37:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8557D61554 for ; Mon, 10 May 2021 21:37:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232469AbhEJVij (ORCPT ); Mon, 10 May 2021 17:38:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232623AbhEJVii (ORCPT ); Mon, 10 May 2021 17:38:38 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61BC2C061574 for ; Mon, 10 May 2021 14:37:33 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id y9so22615056ljn.6 for ; Mon, 10 May 2021 14:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Vig3/UDb6d/s3uE2zPkqOtgiQdK59B99+ZtUFYrpu4=; b=o8XPJWal9K1NyQu6/2oTMjhfSKc1Jei07YTnAWhXpAKrx6S+H3ukz20D673uyk9qGG q4AbdvtTojROoi/qnyUP/bccINyqUw5lKVAGMLQMD54THfy3dBFMHg0whg0zad4ej0Wz aQ4H9sdQgCZv+eJ5fvLg6VYUZpf6EeMdP4v7oo6/GEzZSO6AVo1l7Pk25we5nb0D984q Iqd1DsZ7Cne2F2L1FtQ8VuVjSIMMJGiU6o0M4xBX/7WiGbNFMbddl8nYMqyVFZKz0w1O DthWBPSgQwO03uYrcbRBZQ++c086n+p+tGkniRrC9LxIt2c4Yrgq0IP3GC2PRnYdedLL C/wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Vig3/UDb6d/s3uE2zPkqOtgiQdK59B99+ZtUFYrpu4=; b=mNneHD2iPKDaby64QrKSAoVoxqpsayJvIYdLxRVpSQD2bcnXoChy8jEBD0GyALu027 ScQVbtMaaoTrvnT4DJD1Cbw3YMQ9RacXCZhKe6E54oAuRn3FpXD604Z7yV750q8cNGKm 9Rmjfap5ak4OWfYIqRYwlhQcD0cUEjhDyZ7Y1AYEPp9q+1dOxEQLspENxt6mnHmeL/S1 lcPzGush8XX1Nn6YAzW75qlbBich4QYrnH8/B8A5DBMIoSZP58SMsFdYRg+dOgYjH6Ym 7dsWNks8AtK880fjMOHNwjX9HUhDKnz/HjH9omwKs3TFlfgyVaITriYngb8ZOomKsxc3 tv3Q== X-Gm-Message-State: AOAM532jUGiZF68v80IvFkWEQbzfUb4IH+Vv9ZY1BbtBEZizXNlvzQvS xAtI9hbpmf5qT0C1K6l0v8XRaODgKibMgw== X-Google-Smtp-Source: ABdhPJxhXyzaeEUGUUCEZTyDSWRuCrRHPkrd3nbY9BAIcAaqIZ+rdSn5XTEZcg9IGeRMACNi2lKd8g== X-Received: by 2002:a2e:8557:: with SMTP id u23mr21584878ljj.221.1620682651582; Mon, 10 May 2021 14:37:31 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id q19sm1091660lff.16.2021.05.10.14.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 14:37:31 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa , Arnd Bergmann , Linus Walleij Subject: [PATCH 3/3] crypto: ixp4xx: Add device tree support Date: Mon, 10 May 2021 23:36:34 +0200 Message-Id: <20210510213634.600866-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510213634.600866-1-linus.walleij@linaro.org> References: <20210510213634.600866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This makes the IXP4xx driver probe from the device tree and retrieve the NPE and two queue manager handled used to process crypto from the device tree. As the crypto engine is topologically a part of the NPE hardware, we augment the NPE driver to spawn the crypto engine as a child. The platform data probe path is going away in due time, for now it is an isolated else clause. Signed-off-by: Linus Walleij --- Herbert, David: I am looking for an ACK to take this into the ARM SoC tree as follow-on to the refactoring into a platform device. --- drivers/crypto/ixp4xx_crypto.c | 105 ++++++++++++++++++++++++-------- drivers/soc/ixp4xx/ixp4xx-npe.c | 8 +++ 2 files changed, 86 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 879b93927e2a..49d3454280b6 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -71,15 +72,11 @@ #define MOD_AES256 (0x0a00 | KEYLEN_256) #define MAX_IVLEN 16 -#define NPE_ID 2 /* NPE C */ #define NPE_QLEN 16 /* Space for registering when the first * NPE_QLEN crypt_ctl are busy */ #define NPE_QLEN_TOTAL 64 -#define SEND_QID 29 -#define RECV_QID 30 - #define CTL_FLAG_UNUSED 0x0000 #define CTL_FLAG_USED 0x1000 #define CTL_FLAG_PERFORM_ABLK 0x0001 @@ -216,6 +213,8 @@ static const struct ix_hash_algo hash_alg_sha1 = { }; static struct npe *npe_c; +static unsigned int send_qid; +static unsigned int recv_qid; static struct dma_pool *buffer_pool = NULL; static struct dma_pool *ctx_pool = NULL; @@ -417,7 +416,7 @@ static void crypto_done_action(unsigned long arg) int i; for(i=0; i<4; i++) { - dma_addr_t phys = qmgr_get_entry(RECV_QID); + dma_addr_t phys = qmgr_get_entry(recv_qid); if (!phys) return; one_packet(phys); @@ -427,10 +426,52 @@ static void crypto_done_action(unsigned long arg) static int init_ixp_crypto(struct device *dev) { - int ret = -ENODEV; + struct device_node *np = dev->of_node; u32 msg[2] = { 0, 0 }; + int ret = -ENODEV; + unsigned int npe_id; + + dev_info(dev, "probing...\n"); + + /* Locate the NPE and queue manager to use from the phandle in the device tree */ + if (IS_ENABLED(CONFIG_OF) && np) { + struct of_phandle_args queue_spec; + struct of_phandle_args npe_spec; + + ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, + &npe_spec); + if (ret) { + dev_err(dev, "no NPE engine specified\n"); + return -ENODEV; + } + npe_id = npe_spec.args[0]; + + ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, + &queue_spec); + if (ret) { + dev_err(dev, "no rx queue phandle\n"); + return -ENODEV; + } + recv_qid = queue_spec.args[0]; + + ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, + &queue_spec); + if (ret) { + dev_err(dev, "no txready queue phandle\n"); + return -ENODEV; + } + send_qid = queue_spec.args[0]; + } else { + /* + * Hardcoded engine when using platform data, this goes away + * when we switch to using DT only. + */ + npe_id = 2; + send_qid = 29; + recv_qid = 30; + } - npe_c = npe_request(NPE_ID); + npe_c = npe_request(npe_id); if (!npe_c) return ret; @@ -479,20 +520,20 @@ static int init_ixp_crypto(struct device *dev) if (!ctx_pool) { goto err; } - ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0, + ret = qmgr_request_queue(send_qid, NPE_QLEN_TOTAL, 0, 0, "ixp_crypto:out", NULL); if (ret) goto err; - ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0, + ret = qmgr_request_queue(recv_qid, NPE_QLEN, 0, 0, "ixp_crypto:in", NULL); if (ret) { - qmgr_release_queue(SEND_QID); + qmgr_release_queue(send_qid); goto err; } - qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL); + qmgr_set_irq(recv_qid, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL); tasklet_init(&crypto_done_tasklet, crypto_done_action, 0); - qmgr_enable_irq(RECV_QID); + qmgr_enable_irq(recv_qid); return 0; npe_error: @@ -508,11 +549,11 @@ static int init_ixp_crypto(struct device *dev) static void release_ixp_crypto(struct device *dev) { - qmgr_disable_irq(RECV_QID); + qmgr_disable_irq(recv_qid); tasklet_kill(&crypto_done_tasklet); - qmgr_release_queue(SEND_QID); - qmgr_release_queue(RECV_QID); + qmgr_release_queue(send_qid); + qmgr_release_queue(recv_qid); dma_pool_destroy(ctx_pool); dma_pool_destroy(buffer_pool); @@ -645,8 +686,8 @@ static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target, buf->phys_addr = pad_phys; atomic_inc(&ctx->configuring); - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return 0; } @@ -720,8 +761,8 @@ static int gen_rev_aes_key(struct crypto_tfm *tfm) crypt->ctl_flags |= CTL_FLAG_GEN_REVAES; atomic_inc(&ctx->configuring); - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return 0; } @@ -872,7 +913,7 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC; - if (qmgr_stat_full(SEND_QID)) + if (qmgr_stat_full(send_qid)) return -EAGAIN; if (atomic_read(&ctx->configuring)) return -EAGAIN; @@ -916,8 +957,8 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) req_ctx->src = src_hook.next; crypt->src_buf = src_hook.phys_next; crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK; - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return -EINPROGRESS; free_buf_src: @@ -980,7 +1021,7 @@ static int aead_perform(struct aead_request *req, int encrypt, enum dma_data_direction src_direction = DMA_BIDIRECTIONAL; unsigned int lastlen; - if (qmgr_stat_full(SEND_QID)) + if (qmgr_stat_full(send_qid)) return -EAGAIN; if (atomic_read(&ctx->configuring)) return -EAGAIN; @@ -1064,8 +1105,8 @@ static int aead_perform(struct aead_request *req, int encrypt, } crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD; - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return -EINPROGRESS; free_buf_dst: @@ -1359,12 +1400,13 @@ static struct ixp_aead_alg ixp4xx_aeads[] = { static int ixp_crypto_probe(struct platform_device *_pdev) { + struct device *dev = &_pdev->dev; int num = ARRAY_SIZE(ixp4xx_algos); int i, err; pdev = _pdev; - err = init_ixp_crypto(&pdev->dev); + err = init_ixp_crypto(dev); if (err) return err; @@ -1458,11 +1500,20 @@ static int ixp_crypto_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id ixp4xx_crypto_of_match[] = { + { + .compatible = "intel,ixp4xx-crypto", + }, + {}, +}; static struct platform_driver ixp_crypto_driver = { .probe = ixp_crypto_probe, .remove = ixp_crypto_remove, - .driver = { .name = "ixp4xx_crypto" }, + .driver = { + .name = "ixp4xx_crypto", + .of_match_table = ixp4xx_crypto_of_match, + }, }; module_platform_driver(ixp_crypto_driver); diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c index ec90b44fa0cd..e9e56f926e2d 100644 --- a/drivers/soc/ixp4xx/ixp4xx-npe.c +++ b/drivers/soc/ixp4xx/ixp4xx-npe.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -679,7 +680,9 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) { int i, found = 0; struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct resource *res; + int ret; for (i = 0; i < NPE_COUNT; i++) { struct npe *npe = &npe_tab[i]; @@ -711,6 +714,11 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) if (!found) return -ENODEV; + + /* Spawn crypto subdevice if using device tree */ + if (IS_ENABLED(CONFIG_OF) && np) + devm_of_platform_populate(dev); + return 0; }