From patchwork Fri May 14 05:28:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12257135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E143C433B4 for ; Fri, 14 May 2021 05:25:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E139D61407 for ; Fri, 14 May 2021 05:25:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E139D61407 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CE3F8970B; Fri, 14 May 2021 05:25:47 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A69D8970B for ; Fri, 14 May 2021 05:25:43 +0000 (UTC) IronPort-SDR: VT7bZghS4S83IMbxaGSkepbWRaafk+j/eXRVyQSB9ezzlUSy5VsHNDpNHrdXQG1lhTnlFEmdkf UaxziBdGDZZA== X-IronPort-AV: E=McAfee;i="6200,9189,9983"; a="179714750" X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="179714750" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 IronPort-SDR: prFJbIEOZ1f9ngZ+sCi+5l9tMLkra7CQtkfIILmw5/eYounZD3lnMYBwBvgqrTnDPk8QXqRg/7 Ld6jvH3RaOSA== X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="626679108" Received: from thoang1-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.122]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 13 May 2021 22:28:40 -0700 Message-Id: <20210514052843.9456-1-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Nuke has_infoframe X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This was only reduntant information has_hdmi_sink can do the same job. set_infoframes() hooks will call intel_write_infoframe() for the supported infoframes types and it will only be enabled if given type is set in crtc_state->infoframes.enable. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/g4x_hdmi.c | 22 ++++++------------- drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++--------- drivers/gpu/drm/i915/display/intel_display.c | 6 ++--- .../drm/i915/display/intel_display_types.h | 3 --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +++++------ 6 files changed, 22 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index be352e9f0afc..f35db96e6239 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -105,9 +105,6 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); - if (pipe_config->infoframes.enable) - pipe_config->has_infoframe = true; - if (tmp & HDMI_AUDIO_ENABLE) pipe_config->has_audio = true; @@ -343,9 +340,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } - dig_port->set_infoframes(encoder, - false, - old_crtc_state, old_conn_state); + dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); } @@ -390,9 +385,8 @@ static void intel_hdmi_pre_enable(struct intel_atomic_state *state, intel_hdmi_prepare(encoder, pipe_config); - dig_port->set_infoframes(encoder, - pipe_config->has_infoframe, - pipe_config, conn_state); + dig_port->set_infoframes(encoder, pipe_config->has_hdmi_sink, + pipe_config, conn_state); } static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, @@ -410,9 +404,8 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 0x2b245f5f, 0x00002000, 0x5578b83a, 0x2b247878); - dig_port->set_infoframes(encoder, - pipe_config->has_infoframe, - pipe_config, conn_state); + dig_port->set_infoframes(encoder, pipe_config->has_hdmi_sink, + pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); @@ -487,9 +480,8 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, /* Use 800mV-0dB */ chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); - dig_port->set_infoframes(encoder, - pipe_config->has_infoframe, - pipe_config, conn_state); + dig_port->set_infoframes(encoder, pipe_config->has_hdmi_sink, + pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b7a2fce684c9..5bc5528f3091 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2722,9 +2722,8 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, intel_ddi_enable_pipe_clock(encoder, crtc_state); - dig_port->set_infoframes(encoder, - crtc_state->has_infoframe, - crtc_state, conn_state); + dig_port->set_infoframes(encoder, crtc_state->has_hdmi_sink, crtc_state, + conn_state); } static void intel_ddi_pre_enable(struct intel_atomic_state *state, @@ -2765,9 +2764,8 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, /* FIXME precompute everything properly */ /* FIXME how do we turn infoframes off again? */ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) - dig_port->set_infoframes(encoder, - crtc_state->has_infoframe, - crtc_state, conn_state); + dig_port->set_infoframes(encoder, true, crtc_state, + conn_state); } } @@ -2813,8 +2811,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (!is_mst) - intel_dp_set_infoframes(encoder, false, - old_crtc_state, old_conn_state); + intel_dp_set_infoframes(encoder, false, old_crtc_state, + old_conn_state); /* * Power down sink before disabling the port, otherwise we end @@ -3569,9 +3567,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); - if (pipe_config->infoframes.enable) - pipe_config->has_infoframe = true; - if (temp & TRANS_DDI_HDMI_SCRAMBLING) pipe_config->hdmi_scrambling = true; if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0c2b194006f8..1be88c3a0eea 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7594,9 +7594,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, } drm_dbg_kms(&dev_priv->drm, - "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", - pipe_config->has_audio, pipe_config->has_infoframe, - pipe_config->infoframes.enable); + "audio: %i, infoframes enabled: 0x%x\n", + pipe_config->has_audio, pipe_config->infoframes.enable); if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) @@ -8498,7 +8497,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(hdmi_scrambling); PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); - PIPE_CONF_CHECK_BOOL(has_infoframe); /* FIXME do the readout properly and get rid of this quirk */ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) PIPE_CONF_CHECK_BOOL(fec_enable); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9c0adfc60c6f..669c5d8a2131 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -952,9 +952,6 @@ struct intel_crtc_state { * between pch encoders and cpu encoders. */ bool has_pch_encoder; - /* Are we sending infoframes on the attached port */ - bool has_infoframe; - /* CPU Transcoder for the pipe. Currently this can only differ from the * pipe on Haswell and later (where we have a special eDP transcoder) * and Broxton (where we have special DSI transcoders). */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 332d2f9fda5c..1eb54f8ed51a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -435,8 +435,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, * the transcoder clock select is set to none. */ if (last_mst_stream) - intel_dp_set_infoframes(&dig_port->base, false, - old_crtc_state, NULL); + intel_dp_set_infoframes(&dig_port->base, false, old_crtc_state, + old_conn_state); /* * From TGL spec: "If multi-stream slave transcoder: Configure * Transcoder Clock Select to direct no clock to the transcoder" diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 4a1b2d863b0c..4b970587067d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -712,7 +712,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, struct drm_connector *connector = conn_state->connector; int ret; - if (!crtc_state->has_infoframe) + if (!crtc_state->has_hdmi_sink) return true; crtc_state->infoframes.enable |= @@ -766,7 +766,7 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; int ret; - if (!crtc_state->has_infoframe) + if (!crtc_state->has_hdmi_sink) return true; crtc_state->infoframes.enable |= @@ -796,7 +796,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, &conn_state->connector->display_info; int ret; - if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) + if (!crtc_state->has_hdmi_sink || !info->has_hdmi_infoframe) return true; crtc_state->infoframes.enable |= @@ -827,7 +827,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, if (DISPLAY_VER(dev_priv) < 10) return true; - if (!crtc_state->has_infoframe) + if (!crtc_state->has_hdmi_sink) return true; if (!conn_state->hdr_output_metadata) @@ -1018,7 +1018,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) + if (IS_G4X(dev_priv) || !crtc_state->has_hdmi_sink) return; crtc_state->infoframes.enable |= @@ -2172,9 +2172,6 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, conn_state); - if (pipe_config->has_hdmi_sink) - pipe_config->has_infoframe = true; - if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) pipe_config->pixel_multiplier = 2; From patchwork Fri May 14 05:28:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12257137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E7AEC433ED for ; Fri, 14 May 2021 05:25:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 199126144A for ; Fri, 14 May 2021 05:25:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 199126144A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 915246EE1A; Fri, 14 May 2021 05:25:48 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FFD86E0E6 for ; Fri, 14 May 2021 05:25:45 +0000 (UTC) IronPort-SDR: 6hVdPoErxzVjk/M00x/88QlK7uR2aomR62o2mdT+naCRMgYu/HKUQAyyVxhHloaBHc9uNVNmRl Pou+rJgD0PWw== X-IronPort-AV: E=McAfee;i="6200,9189,9983"; a="179714751" X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="179714751" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 IronPort-SDR: p33mBlTgMfZwUFhABCJCN6l2MR9JH5dyfxGTUSr3aMgKM+0jNP5QuwJYmfkYbgkglkDi9vPcjl gaJdvjfHO2Dw== X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="626679111" Received: from thoang1-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.122]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 13 May 2021 22:28:41 -0700 Message-Id: <20210514052843.9456-2-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210514052843.9456-1-jose.souza@intel.com> References: <20210514052843.9456-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: Replace intel_dp_set_infoframes() disable calls by dig_port->set_infoframes() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Both do the same thing and this change help towards the goal of nuke intel_dp_set_infoframes() completely. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5bc5528f3091..ba2f98881638 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2762,7 +2762,6 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, conn_state); /* FIXME precompute everything properly */ - /* FIXME how do we turn infoframes off again? */ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) dig_port->set_infoframes(encoder, true, crtc_state, conn_state); @@ -2811,8 +2810,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (!is_mst) - intel_dp_set_infoframes(encoder, false, old_crtc_state, - old_conn_state); + dig_port->set_infoframes(encoder, false, old_crtc_state, + old_conn_state); /* * Power down sink before disabling the port, otherwise we end diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1eb54f8ed51a..2866303279ed 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -435,8 +435,9 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, * the transcoder clock select is set to none. */ if (last_mst_stream) - intel_dp_set_infoframes(&dig_port->base, false, old_crtc_state, - old_conn_state); + dig_port->set_infoframes(&dig_port->base, false, old_crtc_state, + old_conn_state); + /* * From TGL spec: "If multi-stream slave transcoder: Configure * Transcoder Clock Select to direct no clock to the transcoder" From patchwork Fri May 14 05:28:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12257139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4527C43460 for ; Fri, 14 May 2021 05:25:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F3D661028 for ; Fri, 14 May 2021 05:25:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F3D661028 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E2006EE0A; Fri, 14 May 2021 05:25:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C18198970B for ; Fri, 14 May 2021 05:25:45 +0000 (UTC) IronPort-SDR: 4Wv6gHbOqEAzyhhstnVB5MYo3I8dempOEXGHu1FHbo4ellHYa4gPiMMYiy3RhNZp+8K9hJDzgN F86Uen34oOug== X-IronPort-AV: E=McAfee;i="6200,9189,9983"; a="179714752" X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="179714752" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 IronPort-SDR: SnwgUKwvuGnaxKZ5Y16txcHdm40acirYKskORmnVsij2eOTB4KA9G1DsJjlKSkz9TOd7kNu5SO oyQGRsx5rLRg== X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="626679115" Received: from thoang1-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.122]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 13 May 2021 22:28:42 -0700 Message-Id: <20210514052843.9456-3-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210514052843.9456-1-jose.souza@intel.com> References: <20210514052843.9456-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Replace intel_dp_set_infoframes() enable calls by dig_port->set_infoframes() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" intel_dp_set_infoframes() and set_infoframes() hook had some code overlapping that makes sense us try to drop it. set_infoframes() is called during the pre_enable phase while intel_dp_set_infoframes() was being called in the enable phase but it was only enabling DP_SDP_VSC and HDMI_PACKET_TYPE_GAMUT_METADATA infoframes, that were added back to hsw_set_infoframes() and lspcon_set_infoframes(). Did not found any information about why this difference of phase but if it is not supported our CI will probably catch it. As hsw_set_infoframes() will now be called during the fastset updates the assert_hdmi_transcoder_func_disabled() check needed to be dropped. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++----- drivers/gpu/drm/i915/display/intel_dp.c | 36 ++------------------- drivers/gpu/drm/i915/display/intel_dp.h | 6 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 ++++------- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++ 5 files changed, 17 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ba2f98881638..04cf7815da2f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2762,9 +2762,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, conn_state); /* FIXME precompute everything properly */ - if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) - dig_port->set_infoframes(encoder, true, crtc_state, - conn_state); + dig_port->set_infoframes(encoder, true, crtc_state, conn_state); } } @@ -3033,7 +3031,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) @@ -3042,9 +3039,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, intel_edp_backlight_on(crtc_state, conn_state); intel_psr_enable(intel_dp, crtc_state, conn_state); - if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); - intel_edp_drrs_enable(intel_dp, crtc_state); if (crtc_state->has_audio) @@ -3245,12 +3239,13 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state, conn_state); - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + dig_port->set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_update(intel_dp, crtc_state); intel_panel_update_backlight(state, encoder, crtc_state, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 861409bc210d..270d9d7ac614 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2757,9 +2757,9 @@ intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_in return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; } -static void intel_write_dp_sdp(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type) +void intel_write_dp_sdp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2808,36 +2808,6 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, &sdp, len); } -void intel_dp_set_infoframes(struct intel_encoder *encoder, - bool enable, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); - u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | - VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | - VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; - u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; - - /* TODO: Add DSC case (DIP_ENABLE_PPS) */ - /* When PSR is enabled, this routine doesn't disable VSC DIP */ - if (!crtc_state->has_psr) - val &= ~VIDEO_DIP_ENABLE_VSC_HSW; - - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); - - if (!enable) - return; - - /* When PSR is enabled, VSC SDP is handled by PSR routine */ - if (!crtc_state->has_psr) - intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); - - intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); -} - static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, const void *buffer, size_t size) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 680631b5b437..be5ad619d573 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -99,9 +99,9 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc); -void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state); +void intel_write_dp_sdp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type); void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 4b970587067d..fd656370053b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -71,16 +71,6 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) "HDMI port enabled, expecting disabled\n"); } -static void -assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, - enum transcoder cpu_transcoder) -{ - drm_WARN(&dev_priv->drm, - intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & - TRANS_DDI_FUNC_ENABLE, - "HDMI transcoder function enabled, expecting disabled\n"); -} - static u32 g4x_infoframe_index(unsigned int type) { switch (type) { @@ -1209,9 +1199,6 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); u32 val = intel_de_read(dev_priv, reg); - assert_hdmi_transcoder_func_disabled(dev_priv, - crtc_state->cpu_transcoder); - val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | @@ -1241,6 +1228,12 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_DRM, &crtc_state->infoframes.drm); + + /* When PSR is enabled, VSC SDP is handled by PSR routine */ + if (!crtc_state->has_psr) + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 05d2d750fa53..e4105156822b 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -565,6 +565,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, buf, ret); + + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) From patchwork Fri May 14 05:28:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12257141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55F66C43461 for ; Fri, 14 May 2021 05:25:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18F5561407 for ; Fri, 14 May 2021 05:25:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18F5561407 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CA266EE0C; Fri, 14 May 2021 05:25:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD88F6EE07 for ; Fri, 14 May 2021 05:25:45 +0000 (UTC) IronPort-SDR: dIbygecbBLRazs0BEBYhNvtEcfb5OF5ZY36FEp7FxttE/PxoSUKUCDWpiPdqtBvl+7qtaY8Rjf GOIlEMm8QlIg== X-IronPort-AV: E=McAfee;i="6200,9189,9983"; a="179714753" X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="179714753" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:45 -0700 IronPort-SDR: 3cP68RtarKWtAlamkANcHcfb9CV90jn8R7K1a3/ROAF2eApyJVud1uRDzgZMlGXtzPZko6XwkE WeP22Yd0YDfw== X-IronPort-AV: E=Sophos;i="5.82,299,1613462400"; d="scan'208";a="626679118" Received: from thoang1-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.1.122]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 22:25:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 13 May 2021 22:28:43 -0700 Message-Id: <20210514052843.9456-4-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210514052843.9456-1-jose.souza@intel.com> References: <20210514052843.9456-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Fix fastsets involving PSR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") is not allowing fastsets to happen when PSR states changes but PSR is a feature that can be enabled and disabled during fastsets. So here moving the PSR pipe conf checks to a block that is only executed when checking if HW state matches with requested state, not during the phase where it checks if fastset is possible or not. There still a state mismatch not allowing fastsets between states turning off or on PSR because of crtc_state->infoframes.enable BIT(DP_SDP_VSC) but at least for now it will allow a fastset between PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not work with PSR2, but the remaning issue will be fixed in a future patch. Cc: Gwan-gyeong Mun Cc: Radhakrishna Sripada Reported-by: Ville Syrjälä Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1be88c3a0eea..e9f1665c6d4b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8546,6 +8546,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); + + PIPE_CONF_CHECK_BOOL(has_psr); + PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); + PIPE_CONF_CHECK_I(dc3co_exitline); } PIPE_CONF_CHECK_BOOL(double_wide); @@ -8629,11 +8634,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.flipline); PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); - PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); - PIPE_CONF_CHECK_I(dc3co_exitline); - #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL