From patchwork Tue Nov 27 17:38:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10701121 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A52FD14BD for ; Tue, 27 Nov 2018 17:39:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BA7F2C139 for ; Tue, 27 Nov 2018 17:39:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7FD0E2C69B; Tue, 27 Nov 2018 17:39:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0B4802C139 for ; Tue, 27 Nov 2018 17:39:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90D1A6E2AD; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F2556E062 for ; Tue, 27 Nov 2018 17:39:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2018 09:39:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,287,1539673200"; d="scan'208";a="93929967" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga008.fm.intel.com with ESMTP; 27 Nov 2018 09:39:15 -0800 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id F38288400D5; Tue, 27 Nov 2018 19:38:48 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Nov 2018 19:38:43 +0200 Message-Id: <20181127173845.17403-1-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Make csb entry count variable in preparation for larger CSB status FIFO size found on gen11+ hardware. Cc: Chris Wilson Cc: Joonas Lahtinen Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++++++++------- drivers/gpu/drm/i915/intel_lrc.c | 24 +++++++++++++++++------- drivers/gpu/drm/i915/intel_lrc.h | 9 +++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 15 +++++++++------ 4 files changed, 40 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 759c0fd58f8c..218ef817da1d 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1347,27 +1347,29 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, unsigned int idx; u8 read, write; - drm_printf(m, "\tExeclist status: 0x%08x %08x\n", + drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n", I915_READ(RING_EXECLIST_STATUS_LO(engine)), - I915_READ(RING_EXECLIST_STATUS_HI(engine))); + I915_READ(RING_EXECLIST_STATUS_HI(engine)), + execlists->csb_entries); read = execlists->csb_head; write = READ_ONCE(*execlists->csb_write); drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n", read, write, - GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))), + I915_READ(RING_CONTEXT_STATUS_PTR(engine)) & + GEN11_CSB_WRITE_PTR_MASK, yesno(test_bit(TASKLET_STATE_SCHED, &engine->execlists.tasklet.state)), enableddisabled(!atomic_read(&engine->execlists.tasklet.count))); - if (read >= GEN8_CSB_ENTRIES) + if (read >= execlists->csb_entries) read = 0; - if (write >= GEN8_CSB_ENTRIES) + if (write >= execlists->csb_entries) write = 0; if (read > write) - write += GEN8_CSB_ENTRIES; + write += execlists->csb_entries; while (read < write) { - idx = ++read % GEN8_CSB_ENTRIES; + idx = ++read % execlists->csb_entries; drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n", idx, hws[idx * 2], diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 08fd9b12e4d7..5487fe496bb6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -767,6 +767,7 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) static void reset_csb_pointers(struct intel_engine_execlists *execlists) { + u32 reset_val; /* * After a reset, the HW starts writing into CSB entry [0]. We * therefore have to set our HEAD pointer back one entry so that @@ -776,8 +777,19 @@ static void reset_csb_pointers(struct intel_engine_execlists *execlists) * inline comparison of our cached head position against the last HW * write works even before the first interrupt. */ - execlists->csb_head = execlists->csb_write_reset; - WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset); + execlists->csb_head = execlists->csb_entries - 1; + + if (execlists_mmio_mode(execlists)) { + const u32 mask = execlists->csb_entries == GEN8_CSB_ENTRIES ? + GEN8_CSB_WRITE_PTR_MASK : + GEN11_CSB_WRITE_PTR_MASK; + + reset_val = _MASKED_FIELD(mask, execlists->csb_head); + } else { + reset_val = execlists->csb_head; + } + + WRITE_ONCE(*execlists->csb_write, reset_val); } static void nop_submission_tasklet(unsigned long data) @@ -895,7 +907,7 @@ static void process_csb(struct intel_engine_cs *engine) unsigned int status; unsigned int count; - if (++head == GEN8_CSB_ENTRIES) + if (++head == execlists->csb_entries) head = 0; /* @@ -2264,6 +2276,8 @@ static int logical_ring_init(struct intel_engine_cs *engine) upper_32_bits(ce->lrc_desc); } + execlists->csb_entries = GEN8_CSB_ENTRIES; + execlists->csb_read = i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); if (csb_force_mmio(i915)) { @@ -2271,16 +2285,12 @@ static int logical_ring_init(struct intel_engine_cs *engine) (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); execlists->csb_write = (u32 __force *)execlists->csb_read; - execlists->csb_write_reset = - _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK, - GEN8_CSB_ENTRIES - 1); } else { execlists->csb_status = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; execlists->csb_write = &engine->status_page.page_addr[intel_hws_csb_write_index(i915)]; - execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1; } reset_csb_pointers(execlists); diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index f5a5502ecf70..e865cba43a26 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -55,10 +55,11 @@ #define GEN8_CSB_PTR_MASK 0x7 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) -#define GEN8_CSB_WRITE_PTR(csb_status) \ - (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0) -#define GEN8_CSB_READ_PTR(csb_status) \ - (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) + +#define GEN11_CSB_ENTRIES 12 +#define GEN11_CSB_PTR_MASK 0xf +#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) +#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) enum { INTEL_CONTEXT_SCHEDULE_IN = 0, diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8a2270b209b0..d9520a52fe29 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -339,13 +339,9 @@ struct intel_engine_execlists { u32 preempt_complete_status; /** - * @csb_write_reset: reset value for CSB write pointer - * - * As the CSB write pointer maybe either in HWSP or as a field - * inside an mmio register, we want to reprogram it slightly - * differently to avoid later confusion. + * @csb_entries: number of CSB entries */ - u32 csb_write_reset; + u8 csb_entries; /** * @csb_head: context status buffer head @@ -714,6 +710,13 @@ execlists_is_active(const struct intel_engine_execlists *execlists, return test_bit(bit, (unsigned long *)&execlists->active); } +static inline bool +execlists_mmio_mode(const struct intel_engine_execlists * const execlists) +{ + return (unsigned long)execlists->csb_read == + (unsigned long)execlists->csb_write; +} + void execlists_user_begin(struct intel_engine_execlists *execlists, const struct execlist_port *port); void execlists_user_end(struct intel_engine_execlists *execlists); From patchwork Tue Nov 27 17:38:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10701119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C3DA14BD for ; Tue, 27 Nov 2018 17:39:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4463F2C139 for ; Tue, 27 Nov 2018 17:39:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 38C642C69B; Tue, 27 Nov 2018 17:39:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E38162C139 for ; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFF986E062; Tue, 27 Nov 2018 17:39:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C3D96E03B for ; Tue, 27 Nov 2018 17:39:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2018 09:39:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,287,1539673200"; d="scan'208";a="91135704" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga007.fm.intel.com with ESMTP; 27 Nov 2018 09:39:15 -0800 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 0157B84005B; Tue, 27 Nov 2018 19:38:48 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Nov 2018 19:38:44 +0200 Message-Id: <20181127173845.17403-2-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127173845.17403-1-mika.kuoppala@linux.intel.com> References: <20181127173845.17403-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Switch to using 12 deep CSB status FIFO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now when we can support variable csb fifo sizes, disable legacy mode. By disabling legacy we hope to get better hw testing coverage by assuming everyone else have switched over. References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108315 Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Daniele Ceraolo Spurio Cc: Kelvin Gardiner Cc: Paulo Zanoni Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5487fe496bb6..107244ab09ef 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1603,17 +1603,9 @@ static void enable_execlists(struct intel_engine_cs *engine) I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); - /* - * Make sure we're not enabling the new 12-deep CSB - * FIFO as that requires a slightly updated handling - * in the ctx switch irq. Since we're currently only - * using only 2 elements of the enhanced execlists the - * deeper FIFO it's not needed and it's not worth adding - * more statements to the irq handler to support it. - */ if (INTEL_GEN(dev_priv) >= 11) I915_WRITE(RING_MODE_GEN7(engine), - _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); + _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); else I915_WRITE(RING_MODE_GEN7(engine), _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); @@ -2276,10 +2268,14 @@ static int logical_ring_init(struct intel_engine_cs *engine) upper_32_bits(ce->lrc_desc); } - execlists->csb_entries = GEN8_CSB_ENTRIES; - execlists->csb_read = i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); + + if (INTEL_GEN(engine->i915) >= 11) + execlists->csb_entries = GEN11_CSB_ENTRIES; + else + execlists->csb_entries = GEN8_CSB_ENTRIES; + if (csb_force_mmio(i915)) { execlists->csb_status = (u32 __force *) (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); From patchwork Tue Nov 27 17:38:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10701117 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AB6E13AD for ; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5308E2C139 for ; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 475F32C69B; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 026F52C139 for ; Tue, 27 Nov 2018 17:39:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E1CF6E03B; Tue, 27 Nov 2018 17:39:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3002B6E03B for ; Tue, 27 Nov 2018 17:39:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2018 09:39:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,287,1539673200"; d="scan'208";a="91135699" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga007.fm.intel.com with ESMTP; 27 Nov 2018 09:39:15 -0800 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 03523840734; Tue, 27 Nov 2018 19:38:49 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Nov 2018 19:38:45 +0200 Message-Id: <20181127173845.17403-3-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127173845.17403-1-mika.kuoppala@linux.intel.com> References: <20181127173845.17403-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Assert the csb tail is within bounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Make sure that the tail we get from hardware fits within the bounds dictated by our count of csb entries. Cc: Chris Wilson Cc: Joonas Lahtinen Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 107244ab09ef..1a34e91c1305 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -888,6 +888,7 @@ static void process_csb(struct intel_engine_cs *engine) */ head = execlists->csb_head; tail = READ_ONCE(*execlists->csb_write); + GEM_DEBUG_BUG_ON(tail >= execlists->csb_entries); GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); if (unlikely(head == tail)) return;