From patchwork Wed May 19 05:04:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12266233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC3BC433ED for ; Wed, 19 May 2021 05:05:52 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 188516135B for ; Wed, 19 May 2021 05:05:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 188516135B Authentication-Results: mail.kernel.org; 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Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljEOe-00F8ZS-5Y for linux-riscv@lists.infradead.org; Wed, 19 May 2021 05:05:29 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4401E61364; Wed, 19 May 2021 05:05:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621400727; bh=Mc4hZG1Zr7Tnoyw/Uvexi2F7Qpbq/iGh58EZtVvBeAI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I4jJGnA5e17WivC5h1/FZT2i6/Or1dFr3+vaoIvac6qtpJQT36d+n/Pn5b0ez3kos 9gg1htVsfY+qbUxZD9z75CfsUdfK1zzz+PSU1IpXxHsFlRQO5ITwpdEAcI4lBEHten XuAFJXgDK/eUPKZXYPQbrHsaS3mS349sOheRzMDObKnwyIO4ZtFba96Rd6Vad01lx2 hKzvhmTCaQhq8iQuwpgimSRWMRYFGXKla9gJ+d6JtOahOEB7y9eNCk9UtyzFM+F+Zm AYoeLfBEz+Lgz2mgpGCNhpUNwAE+lUJwFWHbKlloQVNi+vId5mK4+JsFZy1bH0Enil 0SINvKMDVdhEg== From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, drew@beagleboard.org, hch@lst.de, wefu@redhat.com, lazyparser@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren , Arnd Bergmann Subject: [PATCH RFC 1/3] riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage Date: Wed, 19 May 2021 05:04:14 +0000 Message-Id: <1621400656-25678-2-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621400656-25678-1-git-send-email-guoren@kernel.org> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_220528_265252_EA79BA49 X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren '& _PAGE_CHG_MASK' should masks all attributes BITS then '>> _PAGE_PFN_SHIFT' get the final correct PFN value. '& _PAGE_CHG_MASK' makes the code semantics more accurate. Signed-off-by: Guo Ren Cc: Anup Patel Cc: Arnd Bergmann Cc: Christoph Hellwig Cc: Drew Fustini Cc: Palmer Dabbelt Cc: Wei Fu Cc: Wei Wu --- arch/riscv/include/asm/pgtable-64.h | 8 +++++--- arch/riscv/include/asm/pgtable.h | 6 +++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index f3b0da6..cbf9acf 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -62,12 +62,14 @@ static inline void pud_clear(pud_t *pudp) static inline unsigned long pud_page_vaddr(pud_t pud) { - return (unsigned long)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT); + return (unsigned long)pfn_to_virt( + (pud_val(pud) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT); } static inline struct page *pud_page(pud_t pud) { - return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT); + return pfn_to_page( + (pud_val(pud) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT); } static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) @@ -77,7 +79,7 @@ static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) static inline unsigned long _pmd_pfn(pmd_t pmd) { - return pmd_val(pmd) >> _PAGE_PFN_SHIFT; + return (pmd_val(pmd) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT; } #define pmd_ERROR(e) \ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 9469f46..869d6bf 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -216,12 +216,12 @@ static inline unsigned long _pgd_pfn(pgd_t pgd) static inline struct page *pmd_page(pmd_t pmd) { - return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); + return pfn_to_page((pmd_val(pmd) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT); } static inline unsigned long pmd_page_vaddr(pmd_t pmd) { - return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); + return (unsigned long)pfn_to_virt((pmd_val(pmd) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT); } static inline pte_t pmd_pte(pmd_t pmd) @@ -232,7 +232,7 @@ static inline pte_t pmd_pte(pmd_t pmd) /* Yields the page frame number (PFN) of a page table entry */ static inline unsigned long pte_pfn(pte_t pte) { - return (pte_val(pte) >> _PAGE_PFN_SHIFT); + return ((pte_val(pte) & _PAGE_CHG_MASK) >> _PAGE_PFN_SHIFT); } #define pte_page(x) pfn_to_page(pte_pfn(x)) From patchwork Wed May 19 05:04:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12266235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DEF3C433B4 for ; Wed, 19 May 2021 05:05:57 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9BA9B6135B for ; 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Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljEOj-00F8Zw-Oy for linux-riscv@lists.infradead.org; Wed, 19 May 2021 05:05:35 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id D0E54613AE; Wed, 19 May 2021 05:05:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621400733; bh=sYN05bC53EDVyET7U5IMlzdjAkaiTBtrJ259CHygA2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fvDTItlkZj5gI9AXS4AQXNPjQLrTpx/5B2e1rmH39FXvYEC3cMJFrlw+zJ0AaPMWD T6YWvUc8hG4FVJL8ZDwTN9Io+YQKOSrxlTlROygKIi3oF0XwzV/L4k0VQb2UNYSRlO 0lX+aqj1IIoL95XmXz7mMsLBr0YBv+iOzKj3zM4nq06mIVU4sqNrSUvzpjJ8WRMme+ f9pv6GgC2egWvVQbVfgbHF2uKNX88Yh1xsk55L55JvhN9MopdCkXLgnMZ6rbs35c4D wBPGC/enieQxXgHBFiJYPZBSbR+1y760gO6AekeHeiLfQtRvtHpODZ9rNBpdhAE2yL USUjp+Avm1iYw== From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, drew@beagleboard.org, hch@lst.de, wefu@redhat.com, lazyparser@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren , Arnd Bergmann Subject: [PATCH RFC 2/3] riscv: Add DMA_COHERENT for custom PTE attributes Date: Wed, 19 May 2021 05:04:15 +0000 Message-Id: <1621400656-25678-3-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621400656-25678-1-git-send-email-guoren@kernel.org> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_220533_873393_8142CE0B X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let vendors define the custom properties of memory regions in PTE. That means address attributes would use PTE entry not PMA to meet the different requirements of IO/mem. The patch helps SOC vendors to support their own custom interconnect coherent solution with PTE attributes. Signed-off-by: Guo Ren Cc: Anup Patel Cc: Arnd Bergmann Cc: Christoph Hellwig Cc: Drew Fustini Cc: Palmer Dabbelt Cc: Wei Fu Cc: Wei Wu --- arch/riscv/Kconfig | 27 +++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable-bits.h | 13 ++++++++++++- arch/riscv/include/asm/pgtable.h | 7 ++++--- 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a8ad8eb..632fac5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -376,6 +376,33 @@ config FPU If you don't know what to do here, say Y. +config RISCV_DMA_COHERENT + bool "Custom DMA coherent support" + depends on MMU + help + Help SOC vendors to support their own custom interconnect coherent + solution with PTE attributes. + + The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let + vendors define the custom properties of memory regions in PTE. + + If you don't know what to do here, say N. + +config RISCV_PAGE_DMA_MASK + hex "Custom DMA attributes' mask bits in pte" + depends on RISCV_DMA_COHERENT + default "0x0" + +config RISCV_PAGE_CACHE + hex "Custom CACHE attribute bits in pte" + depends on RISCV_DMA_COHERENT + default "0x0" + +config RISCV_PAGE_DMA_NONCACHE + hex "Custom NONCACHE attribute bits in pte" + depends on RISCV_DMA_COHERENT + default "0x0" + endmenu menu "Kernel features" diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index bbaeb5d..071c5dc 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -24,6 +24,16 @@ #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */ #define _PAGE_SOFT (1 << 8) /* Reserved for software */ +#ifdef CONFIG_RISCV_DMA_COHERENT +#define _PAGE_DMA_MASK CONFIG_RISCV_PAGE_DMA_MASK +#define _PAGE_CACHE CONFIG_RISCV_PAGE_CACHE +#define _PAGE_DMA_NONCACHE CONFIG_RISCV_PAGE_DMA_NONCACHE +#else +#define _PAGE_DMA_MASK (0UL) +#define _PAGE_CACHE (0UL) +#define _PAGE_DMA_NONCACHE (0UL) +#endif + #define _PAGE_SPECIAL _PAGE_SOFT #define _PAGE_TABLE _PAGE_PRESENT @@ -38,6 +48,7 @@ /* Set of bits to preserve across pte_modify() */ #define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL)) + _PAGE_USER | _PAGE_GLOBAL | \ + _PAGE_DMA_MASK)) #endif /* _ASM_RISCV_PGTABLE_BITS_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 869d6bf..f822f22 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -114,7 +114,7 @@ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) /* Page protection bits */ -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) +#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER | _PAGE_CACHE) #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) @@ -134,7 +134,8 @@ | _PAGE_WRITE \ | _PAGE_PRESENT \ | _PAGE_ACCESSED \ - | _PAGE_DIRTY) + | _PAGE_DIRTY \ + | _PAGE_CACHE) #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) @@ -148,7 +149,7 @@ * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't * change the properties of memory regions. */ -#define _PAGE_IOREMAP _PAGE_KERNEL +#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_DMA_MASK) | _PAGE_DMA_NONCACHE) extern pgd_t swapper_pg_dir[]; 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Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljEOp-00F8aL-EH for linux-riscv@lists.infradead.org; Wed, 19 May 2021 05:05:41 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1A0A1613AF; Wed, 19 May 2021 05:05:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621400739; bh=O5me3KriTfnRrUMwzojIEzCyeiCkU9kaY8kiucTa9NQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I5JmJoIiGQY8iSyyH7ddcMiyrYAG37qi6GSZeU5ddzUPwSNM1fOtxwLep1V9NuF3r GBksLSBytYT0i/4UoNDZR3AnHUNvl2S/nmnhVd5VG6xRCEaLo4Gjs+sOa2Ied8iphy 80Xk4dFmGJO6m0RWEWzcg1bbvhPZa0kWCD36HqwDzV/OJ8CD5Rw1yyDcSNHbTC7tOk Lv89PbAcDdhsP1tnzTUQCeYlbtHJ05qzDwxoUMPYp8FDdHIC0ln7WXQrv6+VWc3PBk UBNuCdHzUzbUURDl6nRa8NSFAucyx+BtEK5bwpoyQsDuPneD9hxO2L646lCEONh59m qlDp2dtgYSJvg== From: guoren@kernel.org To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com, drew@beagleboard.org, hch@lst.de, wefu@redhat.com, lazyparser@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren , Arnd Bergmann Subject: [PATCH RFC 3/3] riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT Date: Wed, 19 May 2021 05:04:16 +0000 Message-Id: <1621400656-25678-4-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621400656-25678-1-git-send-email-guoren@kernel.org> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_220539_547384_94F55021 X-CRM114-Status: GOOD ( 19.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren To support DMA device in a non-coherent interconnect SOC system, we need the below facilities: - Change a memory region attributes from cacheable to strong. It would be used in DMA descriptors. - Sync the cache with memory before DMA start and after DMA end. It would be used for DMA data transfer buffers. This patch enables kernel dma/direct.c coherent infrastructure and a new sbi_ecall API for dma_sync. Signed-off-by: Guo Ren Cc: Anup Patel Cc: Arnd Bergmann Cc: Christoph Hellwig Cc: Drew Fustini Cc: Palmer Dabbelt Cc: Wei Fu Cc: Wei Wu --- arch/riscv/Kconfig | 4 ++++ arch/riscv/include/asm/pgtable.h | 13 +++++++++++++ arch/riscv/include/asm/sbi.h | 16 ++++++++++++++++ arch/riscv/kernel/sbi.c | 19 +++++++++++++++++++ arch/riscv/mm/Makefile | 4 ++++ arch/riscv/mm/dma-mapping.c | 41 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 97 insertions(+) create mode 100644 arch/riscv/mm/dma-mapping.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 632fac5..94a736a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,6 +20,9 @@ config RISCV select ARCH_HAS_DEBUG_VM_PGTABLE select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DEBUG_WX + select ARCH_HAS_DMA_PREP_COHERENT if RISCV_DMA_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_CPU if RISCV_DMA_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_DEVICE if RISCV_DMA_COHERENT select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GIGANTIC_PAGE @@ -41,6 +44,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select DMA_DIRECT_REMAP if RISCV_DMA_COHERENT select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index f822f22..8994d58 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -465,6 +465,19 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, return ptep_test_and_clear_young(vma, address, ptep); } +#ifdef CONFIG_RISCV_DMA_COHERENT +#define pgprot_noncached pgprot_noncached +static inline pgprot_t pgprot_noncached(pgprot_t _prot) +{ + unsigned long prot = pgprot_val(_prot); + + prot &= ~_PAGE_DMA_MASK; + prot |= _PAGE_DMA_NONCACHE; + + return __pgprot(prot); +} +#endif + /* * Encode and decode a swap entry * diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 0d42693..08b4244 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -27,6 +27,7 @@ enum sbi_ext_id { SBI_EXT_IPI = 0x735049, SBI_EXT_RFENCE = 0x52464E43, SBI_EXT_HSM = 0x48534D, + SBI_EXT_DMA = 0xAB150401, }; enum sbi_ext_base_fid { @@ -37,6 +38,7 @@ enum sbi_ext_base_fid { SBI_EXT_BASE_GET_MVENDORID, SBI_EXT_BASE_GET_MARCHID, SBI_EXT_BASE_GET_MIMPID, + SBI_EXT_RFENCE_REMOTE_DMA_SYNC, }; enum sbi_ext_time_fid { @@ -63,6 +65,17 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_STATUS, }; +enum sbi_ext_dma_fid { + SBI_DMA_SYNC = 0, +}; + +enum sbi_dma_sync_data_direction { + SBI_DMA_BIDIRECTIONAL = 0, + SBI_DMA_TO_DEVICE = 1, + SBI_DMA_FROM_DEVICE = 2, + SBI_DMA_NONE = 3, +}; + enum sbi_hsm_hart_status { SBI_HSM_HART_STATUS_STARTED = 0, SBI_HSM_HART_STATUS_STOPPED, @@ -128,6 +141,9 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask, unsigned long size, unsigned long asid); int sbi_probe_extension(int ext); +void sbi_dma_sync(unsigned long start, + unsigned long size, + enum sbi_dma_sync_data_direction dir); /* Check if current SBI specification version is 0.1 or not */ static inline int sbi_spec_is_0_1(void) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 7402a41..ff8e18b 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -521,6 +521,25 @@ int sbi_probe_extension(int extid) } EXPORT_SYMBOL(sbi_probe_extension); +void sbi_dma_sync(unsigned long start, + unsigned long size, + enum sbi_dma_sync_data_direction dir) +{ +#if 0 + sbi_ecall(SBI_EXT_DMA, SBI_DMA_SYNC, start, size, dir, + 0, 0, 0); +#else + /* Just for try, it should be in sbi ecall and will be removed before merged */ + register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1); + + for (; i < (start + size); i += L1_CACHE_BYTES) + __asm__ __volatile__(".long 0x02b5000b"); + + __asm__ __volatile__(".long 0x01b0000b"); +#endif +} +EXPORT_SYMBOL(sbi_dma_sync); + static long __sbi_base_ecall(int fid) { struct sbiret ret; diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 7ebaef1..b67d956 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -14,6 +14,10 @@ obj-$(CONFIG_MMU) += fault.o pageattr.o obj-y += cacheflush.o obj-y += context.o +ifeq ($(CONFIG_RISCV_DMA_COHERENT), y) +obj-y += dma-mapping.o +endif + ifeq ($(CONFIG_MMU),y) obj-$(CONFIG_SMP) += tlbflush.o endif diff --git a/arch/riscv/mm/dma-mapping.c b/arch/riscv/mm/dma-mapping.c new file mode 100644 index 00000000..f5db60b --- /dev/null +++ b/arch/riscv/mm/dma-mapping.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +void arch_dma_prep_coherent(struct page *page, size_t size) +{ + void *ptr = page_address(page); + + memset(ptr, 0, size); + sbi_dma_sync(page_to_phys(page), size, SBI_DMA_BIDIRECTIONAL); +} + +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + switch (dir) { + case DMA_TO_DEVICE: + case DMA_FROM_DEVICE: + case DMA_BIDIRECTIONAL: + sbi_dma_sync(paddr, size, dir); + break; + default: + BUG(); + } +} + +void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, + enum dma_data_direction dir) +{ + switch (dir) { + case DMA_TO_DEVICE: + return; + case DMA_FROM_DEVICE: + case DMA_BIDIRECTIONAL: + sbi_dma_sync(paddr, size, dir); + break; + default: + BUG(); + } +}