From patchwork Wed May 19 07:48:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12266543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1A73C433ED for ; Wed, 19 May 2021 07:51:44 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64DAB6112F for ; Wed, 19 May 2021 07:51:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 64DAB6112F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Kp4sHLseGZfUE1AzYfflw4RNEW8z8qiLZxaFb6I0sAw=; b=iQ3uohRY/YLy4tOvZYilKKa5SN XaRBbYMrKbNa4zUxYtLWGU4kkNasZ19ZijcZ+N65MuP6ivVvYICm0JtU/nWkybhJQwiqNF2iNqnvw hs0PqRzYgDYTvD3eEpCKMUgRmwJXK8qPNPSIsQ7nccMZWmVZFvoTiuqaNZSWj9yWaZ0P+ZW8DCmOc XqDSj6i+1hvB2ZWjDAsh5xOmNO+HVuuNbUfBg+BQC2I+yQykZ5c34G39oFTAi1fQeoIMEP9oSNH67 HlSWP+GphQ1ukHzRkMIxCJIKAqLLdEDjmzxT5iqnOn7mkKpxewADJFDiBFr3l6sp+IGWrGNvmifuL lAxhHt/A==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1ljGxL-003E1f-22; Wed, 19 May 2021 07:49:27 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljGwz-003Dzg-Sp for linux-arm-kernel@desiato.infradead.org; Wed, 19 May 2021 07:49:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:In-Reply-To:References; bh=ftt92Xpj0pYW9VSYF7rL5TbLItZBy/IVrtsy6Jfi0Q4=; b=hp1IYyvoGBFqEUGLYOMHbQ0HI4 I8x0gPpLsd2cLhOdRs4E9MEiozLk6Jg8ylb1EtyXNodiFNDIi/S0oBA4mK7Mqw17e/KDNDrJmiLPo TtZx5iGGcy/WRBW+DYcfklOMxGFZdP6JUScBm0s3vWp8kp3JaO9BvGIUxWS6bx+sOUEUrBUNVvLj4 inv5TGGlVy5D0FUmRlsJw/A7XVzFw2GJUaMa+HtKR2FIYR3dtnDYEQfDbEY079TxrgLE7Jnp98PrZ ifFb8fL9cPkdWO6lIBLgmZqwYFQUKLsC/IkAWodeGPQ6VUON/MV8Uh9gkb4mP3vWQtcrVZ02XbRvz SpCPBEIQ==; Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljGwv-00FEVZ-DY for linux-arm-kernel@lists.infradead.org; Wed, 19 May 2021 07:49:04 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 8FDFE440909; Wed, 19 May 2021 10:48:40 +0300 (IDT) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones Cc: Baruch Siach , Andy Gross , Bjorn Andersson , Balaji Prakash J , Rob Herring , Robert Marko , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] pwm: driver for qualcomm ipq6018 pwm block Date: Wed, 19 May 2021 10:48:44 +0300 Message-Id: <70ced827689b7ab35d8f3b07db8d9ccd1489e3e2.1621410526.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_004901_968684_41619198 X-CRM114-Status: GOOD ( 28.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ6010 based hardware. Signed-off-by: Baruch Siach --- drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 263 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 276 insertions(+) create mode 100644 drivers/pwm/pwm-ipq.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 9a4f66ae8070..54ef62a27bdc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -260,6 +260,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 6374d3b1d6f3..73eb955dea1d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) += pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 000000000000..885cf885fcf6 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define CLK_SRC_FREQ (100*1000*1000) +#define MAX_PWM_DEVICES 4 + +/* The default period and duty cycle values to be configured. */ +#define DEFAULT_PERIOD_NS 10 +#define DEFAULT_DUTY_CYCLE_NS 5 + +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to reflect the changed divider and high duration + * values in register. + */ +#define PWM_ENABLE 0x80000000 +#define PWM_UPDATE 0x40000000 + +/* The frequency range supported is 1Hz to 100MHz */ +#define MIN_PERIOD_NS 10 +#define MAX_PERIOD_NS 1000000000 + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field + */ +#define MAX_PWM_CFG 0xFFFF + +#define PWM_CTRL_HI_SHIFT 16 + +#define PWM_CFG_REG0 0 /*PWM_DIV PWM_HI*/ +#define PWM_CFG_REG1 1 /*ENABLE UPDATE PWM_PRE_DIV*/ + +struct ipq_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *mem; +}; + +static struct ipq_pwm_chip *to_ipq_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct ipq_pwm_chip, chip); +} + +static unsigned ipq_pwm_reg_offset(struct pwm_device *pwm, unsigned reg) +{ + return ((pwm->hwpwm * 2) + reg) * 4; +} + +static void config_div_and_duty(struct pwm_device *pwm, int pre_div, + unsigned long long pwm_div, unsigned long period_ns, + unsigned long long duty_ns) +{ + unsigned long hi_dur; + unsigned long long quotient; + unsigned long val = 0; + struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip); + + /* + * high duration = pwm duty * ( pwm div + 1) + * pwm duty = duty_ns / period_ns + */ + quotient = (pwm_div + 1) * duty_ns; + do_div(quotient, period_ns); + hi_dur = quotient; + + val |= ((hi_dur & MAX_PWM_CFG) << PWM_CTRL_HI_SHIFT); + val |= (pwm_div & MAX_PWM_CFG); + writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG0)); + val = pre_div & MAX_PWM_CFG; + writel(val, ipq_chip->mem + ipq_pwm_reg_offset(pwm, PWM_CFG_REG1)); +} + +static int ipq_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip); + unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1); + unsigned long val; + + val = readl(ipq_chip->mem + offset); + val |= (PWM_ENABLE | PWM_UPDATE); + writel(val, ipq_chip->mem + offset); + + return 0; +} + +static void ipq_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(pwm->chip); + unsigned offset = ipq_pwm_reg_offset(pwm, PWM_CFG_REG1); + unsigned long val; + + val = readl(ipq_chip->mem + offset); + val |= PWM_UPDATE; + val &= ~PWM_ENABLE; + writel(val, ipq_chip->mem + offset); +} + +static int ipq_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct ipq_pwm_chip *ipq_chip = to_ipq_pwm_chip(chip); + unsigned long freq; + int pre_div, close_pre_div, close_pwm_div; + int pwm_div; + long long diff; + unsigned long rate = clk_get_rate(ipq_chip->clk); + unsigned long min_diff = rate; + uint64_t fin_ps; + + if (period_ns > MAX_PERIOD_NS || period_ns < MIN_PERIOD_NS) { + pr_err("PWM Frequency range supported is %dHz to %dHz\n" + "Switching to default configuration values\n", + (int)NSEC_PER_SEC / MAX_PERIOD_NS, + (int)NSEC_PER_SEC / MIN_PERIOD_NS); + period_ns = DEFAULT_PERIOD_NS; + duty_ns = DEFAULT_DUTY_CYCLE_NS; + pwm->state.period = period_ns; + pwm->state.duty_cycle = duty_ns; + } + + /* freq in Hz for period in nano second*/ + freq = NSEC_PER_SEC / period_ns; + fin_ps = (uint64_t)NSEC_PER_SEC * 1000; + do_div(fin_ps, rate); + close_pre_div = MAX_PWM_CFG; + close_pwm_div = MAX_PWM_CFG; + + ipq_pwm_disable(chip, pwm); + + for (pre_div = 0; pre_div <= MAX_PWM_CFG; pre_div++) { + pwm_div = DIV_ROUND_CLOSEST_ULL((uint64_t)period_ns * 1000, + fin_ps * (pre_div + 1)); + pwm_div--; + if (pwm_div <= MAX_PWM_CFG) { + diff = (uint64_t)rate - ((uint64_t)freq * (pre_div + 1) * (pwm_div + 1)); + + if (diff < 0) + diff = -diff; + if (!diff) { + close_pre_div = pre_div; + close_pwm_div = pwm_div; + break; + } + if (diff < min_diff) { + min_diff = diff; + close_pre_div = pre_div; + close_pwm_div = pwm_div; + } + } + } + + /* config divider values for the closest possible frequency */ + config_div_and_duty(pwm, close_pre_div, close_pwm_div, + period_ns, duty_ns); + if (pwm->state.enabled) + ipq_pwm_enable(chip, pwm); + + return 0; +} + +static int ipq_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + pwm->state.period = DEFAULT_PERIOD_NS; + pwm->state.duty_cycle = DEFAULT_DUTY_CYCLE_NS; + + ipq_pwm_config(chip, pwm, pwm->state.duty_cycle, pwm->state.period); + + return 0; +} + +static void ipq_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + ipq_pwm_disable(chip, pwm); +} + +static struct pwm_ops ipq_pwm_ops = { + .request = ipq_pwm_request, + .free = ipq_pwm_free, + .config = ipq_pwm_config, + .enable = ipq_pwm_enable, + .disable = ipq_pwm_disable, + .owner = THIS_MODULE, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct ipq_pwm_chip *pwm; + struct device *dev; + int ret; + + dev = &pdev->dev; + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) { + dev_err(dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, pwm); + + pwm->mem = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return PTR_ERR(pwm->mem); + + pwm->clk = devm_clk_get(dev, "core"); + if (!IS_ERR(pwm->clk)) { + ret = clk_set_rate(pwm->clk, CLK_SRC_FREQ); + if (ret) + return ret; + ret = clk_prepare_enable(pwm->clk); + if (ret) + return ret; + } + + pwm->chip.dev = dev; + pwm->chip.ops = &ipq_pwm_ops; + pwm->chip.npwm = MAX_PWM_DEVICES; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) { + dev_err(dev, "pwmchip_add() failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int ipq_pwm_remove(struct platform_device *pdev) +{ + struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev); + + return pwmchip_remove(&pwm->chip); +} + +static const struct of_device_id pwm_ipq_dt_match[] = { + { .compatible = "qcom,pwm-ipq6018", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver = { + .driver = { + .name = "ipq-pwm", + .owner = THIS_MODULE, + .of_match_table = pwm_ipq_dt_match, + }, + .probe = ipq_pwm_probe, + .remove = ipq_pwm_remove, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("Dual BSD/GPL"); From patchwork Wed May 19 07:48:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12266539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA7E1C433B4 for ; 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bh=KV9lnI7+i0BU727exizEDmuOFV6fBuIFouwArLeNjE0=; b=PLieDj5XyPoqA1WewX4p5WXGg+ 1TvqBYDniVAQbGdNQgjwEAlay1hQEJArdZqLkAzWvVRhMiTRF0icLWfHx/LpTKqJbY0yOEhS8NyEZ 2TGInVfuBdIEIVGEsGnT+qRqxQnnICSKW2C5vSt7xTX8EWMhCpX1j6d1OjeHTlPi35qs4mpyxteJO ugQdpEu2E21C9wDkel/VlpFCtSukr6XTCsQO+YrM3hzoyqdcGSvGQqCmKkByid/k4Aejm7g1+3p2V kYFmS695x8JJqZcu1RjGQRBIstRCf0FaZELXCoeesvPXXoRutlmCVkBegEQZZmnWvFUnJod7EoO0e 4l+OWRXg==; Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljGwu-00FEVa-Tk for linux-arm-kernel@lists.infradead.org; Wed, 19 May 2021 07:49:02 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id ABF41440DDE; Wed, 19 May 2021 10:48:41 +0300 (IDT) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones Cc: Baruch Siach , Andy Gross , Bjorn Andersson , Balaji Prakash J , Rob Herring , Robert Marko , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] dt-bindings: pwm: add IPQ6018 binding Date: Wed, 19 May 2021 10:48:45 +0300 Message-Id: <12137bb3caf68d43e7fbbb60d9f600145eb78507.1621410526.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.30.2 In-Reply-To: <70ced827689b7ab35d8f3b07db8d9ccd1489e3e2.1621410526.git.baruch@tkos.co.il> References: <70ced827689b7ab35d8f3b07db8d9ccd1489e3e2.1621410526.git.baruch@tkos.co.il> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_004901_235171_B9560867 X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DT binding for the PWM block in Qualcomm IPQ6018 SoC. Signed-off-by: Baruch Siach --- .../devicetree/bindings/pwm/ipq-pwm.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml new file mode 100644 index 000000000000..a98f20664702 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + "#pwm-cells": + description: | + Should be set to 2. + + compatible: + const: qcom,pwm-ipq6018 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: core + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pwm@1941010 { + #pwm-cells = <2>; + compatible = "qcom,pwm-ipq6018"; + reg = <0x0 0x1941010 0x0 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + clock-names = "core"; + }; + }; From patchwork Wed May 19 07:48:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12266541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 338E2C433ED for ; Wed, 19 May 2021 07:51:25 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB36A60FDC for ; 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Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljGwv-00FEVY-LZ for linux-arm-kernel@lists.infradead.org; Wed, 19 May 2021 07:49:04 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 81B25440DF6; Wed, 19 May 2021 10:48:42 +0300 (IDT) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones Cc: Baruch Siach , Andy Gross , Bjorn Andersson , Balaji Prakash J , Rob Herring , Robert Marko , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] arm64: dts: ipq6018: add pwm node Date: Wed, 19 May 2021 10:48:46 +0300 Message-Id: <645bfb28f93e475e354b4763f932f16d712ad600.1621410526.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.30.2 In-Reply-To: <70ced827689b7ab35d8f3b07db8d9ccd1489e3e2.1621410526.git.baruch@tkos.co.il> References: <70ced827689b7ab35d8f3b07db8d9ccd1489e3e2.1621410526.git.baruch@tkos.co.il> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_004901_950172_A9E0C01A X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Describe the PWM block on IPQ6018. Signed-off-by: Baruch Siach --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 6ee7b99c21ec..2da75bb558ff 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -355,6 +355,15 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ status = "disabled"; }; + pwm: pwm@1941010 { + #pwm-cells = <2>; + compatible = "qcom,pwm-ipq6018"; + reg = <0x0 0x1941010 0x0 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + clock-names = "core"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07984000 0x0 0x1a000>;