From patchwork Wed Nov 28 10:14:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 10702257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D4E513A4 for ; Wed, 28 Nov 2018 10:15:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 592772CE23 for ; Wed, 28 Nov 2018 10:15:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A93E2CFBE; Wed, 28 Nov 2018 10:15:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C4E6C2CE23 for ; Wed, 28 Nov 2018 10:15:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ikBHLZXiUgaKkkcWS+AdjoJfILV8GUMJmkfT/cYG3YM=; b=bo5IKXpQWOiQcl vZ9ztRuRk1x46ooz1y5qcZHKIbtz2PpLlu29l7O8ebh0Nr4/tooUHiFzHfQPUIm4O2kBNmPt2BiVT C92rlbLxzzYDS4NlGwlN+cOwbIpsxJ27dYxj3IbdPxFkNbHJFJVTnWJX2V3bbSH1K8dXUCgxrNDe3 ICxq8dY8pkryXNRzqUUtresvJ5Nb9zBOhNfENbNgV4II/1DYvXXna//Xd1K7qt31MMqeXjZNnwBnd Q0E7emma/B5XKGWD37FypWaARzSDFhxIOM6YC+YW94cU0unFbhPeSLKp9/coiocKvGAIaDs22G+eX zs9QeF4VAp9K2KRinJdA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRwse-00021F-Ht; Wed, 28 Nov 2018 10:15:40 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRws5-0008V7-HP for linux-arm-kernel@lists.infradead.org; Wed, 28 Nov 2018 10:15:12 +0000 Received: by mail-wr1-x442.google.com with SMTP id x10so25667792wrs.8 for ; Wed, 28 Nov 2018 02:14:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mKR+qCFZ4t4UF8syT2wjRtjd8ffQldwnoE8EhYxIgKU=; b=a1RBO/5s/LwtCvPf6B2Lav6AawFet6quRxhrRh+4GkDxmhYxA52debpOy4CjkZ/NL7 b5Yhzmj0/qO6EvUZ6qHWtzIQZCWkLt+GooYDpcNto/rzUiVYQ2joigZVpSAUySke1Xkq 1fnodaylyYu9XQABT/JdCRmkAop1ougdcKYFw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mKR+qCFZ4t4UF8syT2wjRtjd8ffQldwnoE8EhYxIgKU=; b=RKPC0RYO+7TRQgipx3YLXGsbjlbSvpvk/d06UATs1piICVZ5SmDOTZGvdSKW290pWB mNj5FmuWaTaB79VLkqHjuyFuotP603HVe8SBUaq/iRtHluLkAdSQ++e3uOHRy6XbgAvk Flndos2srtMPSLvgE7VhRiCVJM4gYLjKsQR1N58msnOYS4TYEU3aN5U0ScwCQeaV211i fluGcllUaZmy+/h4fOeVK4D6IOwSshmz5t8345EYgGktViVkVrjKuvRTL8pSS+eNhsZp jI/ZTls2NnJTIlCXD8T4n/FFlsPuYMFxrRAceUs9oOcsYKslqN/a2FJzLcPXusAHj0ku LssQ== X-Gm-Message-State: AA+aEWaMYlr/qwatvuS1bRFFIE+/qZz68GCS2+gmMCCfJVakUrvZX/1M 8EBQarlMKfskMkfHxhgxXAsBgw== X-Google-Smtp-Source: AFSGD/Uah9m0HdPXxzZ+rB005AGgQvaHPys3BcmhkfDcpZWG3IoyplC5//3W/zB9DQjwbZnCODpOMQ== X-Received: by 2002:adf:e488:: with SMTP id i8mr31853944wrm.10.1543400094444; Wed, 28 Nov 2018 02:14:54 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id w16sm8852108wrp.1.2018.11.28.02.14.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 02:14:53 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 1/3] drivers: amba: Updates to component identification for driver matching. Date: Wed, 28 Nov 2018 10:14:21 +0000 Message-Id: <20181128101423.15961-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181128101423.15961-1-mike.leach@linaro.org> References: <20181128101423.15961-1-mike.leach@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_021505_583922_37744D0A X-CRM114-Status: GOOD ( 20.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components. The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID. Bits 11:8 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required. The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching. CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose --- drivers/amba/bus.c | 49 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-) diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..387ee8f7720b 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,40 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data; + + /* no table data - return match on periphid */ + if (!uci) + return 1; + + if (uci->devarch) { + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + } else { + /* devtype only if devarch set to 0 */ + ret = dev->uci.devtype == uci->devtype; + } + return ret; +} +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; } static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +420,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev); - if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + } if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..ff0ce0587ee9 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d +/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 11:8 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/* + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; +}; + +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk; struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; }; From patchwork Wed Nov 28 10:14:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 10702255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90F4D13A4 for ; Wed, 28 Nov 2018 10:15:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 800442CE23 for ; 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Wed, 28 Nov 2018 02:14:55 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id w16sm8852108wrp.1.2018.11.28.02.14.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 02:14:54 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 2/3] coresight: etmv4: Update ID register table to add UCI support Date: Wed, 28 Nov 2018 10:14:22 +0000 Message-Id: <20181128101423.15961-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181128101423.15961-1-mike.leach@linaro.org> References: <20181128101423.15961-1-mike.leach@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_021507_256053_6662AB15 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code. Signed-off-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ } +static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, + } +}; + +#define ETM4x_AMBA_UCI_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_id_etm4, \ + } + static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, }; 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Test only - not intended for upstream. Signed-off-by: Mike Leach --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++ drivers/amba/bus.c | 13 ++++++++++++- drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a1..c8b503a63b2c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1368,6 +1368,15 @@ }; }; + /* add an as yet unsupported CTI for UCI test - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 387ee8f7720b..ccc2bb4a98b8 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -32,19 +32,30 @@ amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; struct amba_cs_uci_id *uci; + struct device *adev; /* device for test logging */ uci = table->data; + adev = &dev->dev; /* no table data - return match on periphid */ - if (!uci) + if (!uci) { + dev_info(adev, "uci_match: no UCI, use periphID\n"); return 1; + } if (uci->devarch) { ret = (dev->uci.devtype == uci->devtype) && ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + dev_info(adev, "device: devtype[%x]; devarch[%x];\n", + dev->uci.devtype, dev->uci.devarch); + dev_info(adev, "uci_match: devtype[%x]; devarch[%x]; (%s)\n", + uci->devtype, uci->devarch, + ret ? "match" : "no match"); } else { /* devtype only if devarch set to 0 */ ret = dev->uci.devtype == uci->devtype; + dev_info(adev, "uci_match: devtype-only[%x]; (%s)\n", + uci->devtype, ret ? "match" : "no match"); } return ret; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 2fb8054e43ab..4dfc41c37447 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1090,11 +1090,12 @@ static struct amba_cs_uci_id uci_id_etm4[] = { } static const struct amba_id etm4_ids[] = { - ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ + ETM4x_AMBA_UCI_ID(0x000bb95d), /* C-A53 - UCI optional for test */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9a8), /* CTI PID A53 - test fail UCI match */ {}, };