From patchwork Fri May 21 07:25:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 12272311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA8AC433B4 for ; Fri, 21 May 2021 07:29:58 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03C5E613C4 for ; Fri, 21 May 2021 07:29:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03C5E613C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=3+XUZOFA+7CO9a1twMpiVcagtq5xVCUoXV3A0typhAs=; b=d7ICPcU6+rC57OOTZ7f/prgMnd hZ0fpeuDr+89/6qzz9hesQiqBw2YLNAEhgVrkXnh5IKWTxrKkAV4TGFPLdU0SADpvuBBBjdvaDWVJ OpVIB321Sab+dNHwzgStjQDUOPSVjTIsosyT3fFG96X9MdeEMFBVejfL2O8LEdm4M22edTpQEYtYM fFTnzHhPswpnTK8AUBuJ6PlAIS64G+fftso6p9lW2emLWHHFrTmyEV5ru24stZQIZxUKHZE5FL/6w 3IZm/cNvUWa0kgp/Qo659hTnFs6myczF1tLHkJs6cJ2kkC81uEZ90xhNjiK4DjBbwvScCP/bo9KcT Q4Ugp9iQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ljzXs-004C8H-DR; Fri, 21 May 2021 07:26:08 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ljzXn-004C7A-7L for linux-arm-kernel@desiato.infradead.org; Fri, 21 May 2021 07:26:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type:MIME-Version:Message-ID: Date:Subject:CC:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:In-Reply-To:References; bh=uJBddDwDIV8H+z836wfSCzLFTqTUJ3B36Lz4+mgL2nE=; b=T32pJep8BCTBL6Bqy3gPViRh4/ NQaVqmObZ7Q7IngJjH6V4SHCi4047sIbIxGOqDu206QkSfCffMJacrp4ABMPuaNC1+1upemCAIA83 FmOXtBa5+8vW8bi+dTPA9QV9wtayhOdmHLCLjBybaaw1a7XnAS/KrkeRuyJ3stzSuVSA7Lqx8SO01 zZeLF/zBW6rfGYykqToKMW5D8nMkQRhWTu7gOxJIO2jY2uRIR3jfxjHFy9GHKXbU2UBsEfCZ46zxT +L4+X07uCUhzkbX3X8NvlWi2oWdUourjhBfGWZDF7veOp57cE/F8A8HX+DqTLCI6kBr8bimFHVlUZ 0o5ZI7pA==; Received: from szxga07-in.huawei.com ([45.249.212.35]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1ljzXj-00GuYj-Qu for linux-arm-kernel@lists.infradead.org; Fri, 21 May 2021 07:26:01 +0000 Received: from dggems701-chm.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4FmdP20vlDzCvPk; Fri, 21 May 2021 15:23:02 +0800 (CST) Received: from dggpeml500023.china.huawei.com (7.185.36.114) by dggems701-chm.china.huawei.com (10.3.19.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 21 May 2021 15:25:50 +0800 Received: from localhost.localdomain (10.69.192.56) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 21 May 2021 15:25:49 +0800 From: Shaokun Zhang To: CC: Shaokun Zhang , Will Deacon , Mark Rutland Subject: [PATCH] arm64: perf: Add more support on caps under sysfs Date: Fri, 21 May 2021 15:25:44 +0800 Message-ID: <1621581944-17381-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210521_002600_232834_ED33D822 X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Armv8.7 has introduced BUS_SLOTS and BUS_WIDTH in PMMIR_EL1 register, add two entries in caps for bus_slots and bus_width under sysfs. It will return the true slots and width if the information is available, otherwise it will return 0. Cc: Will Deacon Cc: Mark Rutland Signed-off-by: Shaokun Zhang --- arch/arm64/include/asm/perf_event.h | 5 +++ arch/arm64/kernel/perf_event.c | 64 +++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index 60731f602d3e..4ef6f19331f9 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -239,6 +239,11 @@ /* PMMIR_EL1.SLOTS mask */ #define ARMV8_PMU_SLOTS_MASK 0xff +#define ARMV8_PMU_BUS_SLOTS_SHIFT 8 +#define ARMV8_PMU_BUS_SLOTS_MASK 0xff +#define ARMV8_PMU_BUS_WIDTH_SHIFT 16 +#define ARMV8_PMU_BUS_WIDTH_MASK 0xf + #ifdef CONFIG_PERF_EVENTS struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index f594957e29bd..f0847e4f48a9 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -317,8 +317,72 @@ static ssize_t slots_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RO(slots); +static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, + char *page) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); + u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT) + & ARMV8_PMU_BUS_SLOTS_MASK; + + return snprintf(page, PAGE_SIZE, "0x%08x\n", bus_slots); +} + +static DEVICE_ATTR_RO(bus_slots); + +static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, + char *page) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); + u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT) + & ARMV8_PMU_BUS_WIDTH_MASK; + u32 val; + + switch (bus_width) { + case 3: + val = 4; + break; + case 4: + val = 8; + break; + case 5: + val = 16; + break; + case 6: + val = 32; + break; + case 7: + val = 64; + break; + case 8: + val = 128; + break; + case 9: + val = 256; + break; + case 10: + val = 512; + break; + case 11: + val = 1024; + break; + case 12: + val = 2048; + break; + default: + val = 0; + } + + return snprintf(page, PAGE_SIZE, "0x%08x\n", val); +} + +static DEVICE_ATTR_RO(bus_width); + static struct attribute *armv8_pmuv3_caps_attrs[] = { &dev_attr_slots.attr, + &dev_attr_bus_slots.attr, + &dev_attr_bus_width.attr, NULL, };