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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id z6sm2787292oiz.39.2021.05.24.09.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:27:43 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org, hao.wu@intel.com, michal.simek@xilinx.com Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tom Rix Subject: [PATCH v3 1/6] fpga: generalize updating the card Date: Mon, 24 May 2021 09:27:40 -0700 Message-Id: <20210524162740.2221114-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix There is a need to update the whole card. An fpga can contain non-fpga components whose firmware needs to be updated at the same time as the fpga rtl images and may need to be handled differently from the existing fpga reconfiguration in the fpga manager. Move the write_* ops out of fpga_manager_ops and into a new fpga_manager_update_ops struct. Add two update_ops back to fpga_manager_ops, reconfig for the exiting functionality and reimage for the new functionity. Rewire fpga devs to use reconfig ops Signed-off-by: Tom Rix --- drivers/fpga/altera-cvp.c | 8 ++++---- drivers/fpga/altera-pr-ip-core.c | 8 ++++---- drivers/fpga/altera-ps-spi.c | 8 ++++---- drivers/fpga/dfl-fme-mgr.c | 10 +++++----- drivers/fpga/fpga-mgr.c | 23 ++++++++++++----------- drivers/fpga/ice40-spi.c | 8 ++++---- drivers/fpga/machxo2-spi.c | 8 ++++---- drivers/fpga/socfpga-a10.c | 10 +++++----- drivers/fpga/socfpga.c | 8 ++++---- drivers/fpga/stratix10-soc.c | 8 ++++---- drivers/fpga/ts73xx-fpga.c | 8 ++++---- drivers/fpga/xilinx-spi.c | 8 ++++---- drivers/fpga/zynq-fpga.c | 10 +++++----- drivers/fpga/zynqmp-fpga.c | 8 ++++---- include/linux/fpga/fpga-mgr.h | 32 +++++++++++++++++++++----------- 15 files changed, 88 insertions(+), 77 deletions(-) diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 4e0edb60bfba6..e107651f89bbd 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -516,10 +516,10 @@ static int altera_cvp_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops altera_cvp_ops = { - .state = altera_cvp_state, - .write_init = altera_cvp_write_init, - .write = altera_cvp_write, - .write_complete = altera_cvp_write_complete, + .state = altera_cvp_state, + .reconfig.write_init = altera_cvp_write_init, + .reconfig.write = altera_cvp_write, + .reconfig.write_complete = altera_cvp_write_complete, }; static const struct cvp_priv cvp_priv_v1 = { diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c index 5b130c4d98829..3385587679d5b 100644 --- a/drivers/fpga/altera-pr-ip-core.c +++ b/drivers/fpga/altera-pr-ip-core.c @@ -167,10 +167,10 @@ static int alt_pr_fpga_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops alt_pr_ops = { - .state = alt_pr_fpga_state, - .write_init = alt_pr_fpga_write_init, - .write = alt_pr_fpga_write, - .write_complete = alt_pr_fpga_write_complete, + .state = alt_pr_fpga_state, + .reconfig.write_init = alt_pr_fpga_write_init, + .reconfig.write = alt_pr_fpga_write, + .reconfig.write_complete = alt_pr_fpga_write_complete, }; int alt_pr_register(struct device *dev, void __iomem *reg_base) diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c index 23bfd4d1ad0f7..2b01a3c53d374 100644 --- a/drivers/fpga/altera-ps-spi.c +++ b/drivers/fpga/altera-ps-spi.c @@ -231,10 +231,10 @@ static int altera_ps_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops altera_ps_ops = { - .state = altera_ps_state, - .write_init = altera_ps_write_init, - .write = altera_ps_write, - .write_complete = altera_ps_write_complete, + .state = altera_ps_state, + .reconfig.write_init = altera_ps_write_init, + .reconfig.write = altera_ps_write, + .reconfig.write_complete = altera_ps_write_complete, }; static const struct altera_ps_data *id_to_data(const struct spi_device_id *id) diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index d5861d13b3069..89913d27d877c 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -265,11 +265,11 @@ static u64 fme_mgr_status(struct fpga_manager *mgr) } static const struct fpga_manager_ops fme_mgr_ops = { - .write_init = fme_mgr_write_init, - .write = fme_mgr_write, - .write_complete = fme_mgr_write_complete, - .state = fme_mgr_state, - .status = fme_mgr_status, + .state = fme_mgr_state, + .status = fme_mgr_status, + .reconfig.write_init = fme_mgr_write_init, + .reconfig.write = fme_mgr_write, + .reconfig.write_complete = fme_mgr_write_complete, }; static void fme_mgr_get_compat_id(void __iomem *fme_pr, diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index b85bc47c91a9a..e3fc1b0bd7181 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -83,9 +83,9 @@ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, mgr->state = FPGA_MGR_STATE_WRITE_INIT; if (!mgr->mops->initial_header_size) - ret = mgr->mops->write_init(mgr, info, NULL, 0); + ret = mgr->mops->reconfig.write_init(mgr, info, NULL, 0); else - ret = mgr->mops->write_init( + ret = mgr->mops->reconfig.write_init( mgr, info, buf, min(mgr->mops->initial_header_size, count)); if (ret) { @@ -147,7 +147,7 @@ static int fpga_mgr_write_complete(struct fpga_manager *mgr, int ret; mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE; - ret = mgr->mops->write_complete(mgr, info); + ret = mgr->mops->reconfig.write_complete(mgr, info); if (ret) { dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR; @@ -187,14 +187,14 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, /* Write the FPGA image to the FPGA. */ mgr->state = FPGA_MGR_STATE_WRITE; - if (mgr->mops->write_sg) { - ret = mgr->mops->write_sg(mgr, sgt); + if (mgr->mops->reconfig.write_sg) { + ret = mgr->mops->reconfig.write_sg(mgr, sgt); } else { struct sg_mapping_iter miter; sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); while (sg_miter_next(&miter)) { - ret = mgr->mops->write(mgr, miter.addr, miter.length); + ret = mgr->mops->reconfig.write(mgr, miter.addr, miter.length); if (ret) break; } @@ -224,7 +224,7 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, * Write the FPGA image to the FPGA. */ mgr->state = FPGA_MGR_STATE_WRITE; - ret = mgr->mops->write(mgr, buf, count); + ret = mgr->mops->reconfig.write(mgr, buf, count); if (ret) { dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); mgr->state = FPGA_MGR_STATE_WRITE_ERR; @@ -264,7 +264,7 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr, * contiguous kernel buffer and the driver doesn't require SG, non-SG * drivers will still work on the slow path. */ - if (mgr->mops->write) + if (mgr->mops->reconfig.write) return fpga_mgr_buf_load_mapped(mgr, info, buf, count); /* @@ -568,9 +568,10 @@ struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, struct fpga_manager *mgr; int id, ret; - if (!mops || !mops->write_complete || !mops->state || - !mops->write_init || (!mops->write && !mops->write_sg) || - (mops->write && mops->write_sg)) { + if (!mops || !mops->reconfig.write_complete || !mops->state || + !mops->reconfig.write_init || (!mops->reconfig.write && + !mops->reconfig.write_sg) || + (mops->reconfig.write && mops->reconfig.write_sg)) { dev_err(dev, "Attempt to register without fpga_manager_ops\n"); return NULL; } diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c index 69dec5af23c36..3bdc3fe8ece97 100644 --- a/drivers/fpga/ice40-spi.c +++ b/drivers/fpga/ice40-spi.c @@ -126,10 +126,10 @@ static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops ice40_fpga_ops = { - .state = ice40_fpga_ops_state, - .write_init = ice40_fpga_ops_write_init, - .write = ice40_fpga_ops_write, - .write_complete = ice40_fpga_ops_write_complete, + .state = ice40_fpga_ops_state, + .reconfig.write_init = ice40_fpga_ops_write_init, + .reconfig.write = ice40_fpga_ops_write, + .reconfig.write_complete = ice40_fpga_ops_write_complete, }; static int ice40_fpga_probe(struct spi_device *spi) diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 114a64d2b7a4d..8b860e9a19c92 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -350,10 +350,10 @@ static int machxo2_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops machxo2_ops = { - .state = machxo2_spi_state, - .write_init = machxo2_write_init, - .write = machxo2_write, - .write_complete = machxo2_write_complete, + .state = machxo2_spi_state, + .reconfig.write_init = machxo2_write_init, + .reconfig.write = machxo2_write, + .reconfig.write_complete = machxo2_write_complete, }; static int machxo2_spi_probe(struct spi_device *spi) diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c index 573d88bdf7307..e60bf844b4c40 100644 --- a/drivers/fpga/socfpga-a10.c +++ b/drivers/fpga/socfpga-a10.c @@ -458,11 +458,11 @@ static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr) } static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = { - .initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4, - .state = socfpga_a10_fpga_state, - .write_init = socfpga_a10_fpga_write_init, - .write = socfpga_a10_fpga_write, - .write_complete = socfpga_a10_fpga_write_complete, + .initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4, + .state = socfpga_a10_fpga_state, + .reconfig.write_init = socfpga_a10_fpga_write_init, + .reconfig.write = socfpga_a10_fpga_write, + .reconfig.write_complete = socfpga_a10_fpga_write_complete, }; static int socfpga_a10_fpga_probe(struct platform_device *pdev) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 1f467173fc1f3..cc752a3f742c2 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -534,10 +534,10 @@ static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr) } static const struct fpga_manager_ops socfpga_fpga_ops = { - .state = socfpga_fpga_ops_state, - .write_init = socfpga_fpga_ops_configure_init, - .write = socfpga_fpga_ops_configure_write, - .write_complete = socfpga_fpga_ops_configure_complete, + .state = socfpga_fpga_ops_state, + .reconfig.write_init = socfpga_fpga_ops_configure_init, + .reconfig.write = socfpga_fpga_ops_configure_write, + .reconfig.write_complete = socfpga_fpga_ops_configure_complete, }; static int socfpga_fpga_probe(struct platform_device *pdev) diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 657a70c5fc996..37e90ec0704c6 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -394,10 +394,10 @@ static enum fpga_mgr_states s10_ops_state(struct fpga_manager *mgr) } static const struct fpga_manager_ops s10_ops = { - .state = s10_ops_state, - .write_init = s10_ops_write_init, - .write = s10_ops_write, - .write_complete = s10_ops_write_complete, + .state = s10_ops_state, + .reconfig.write_init = s10_ops_write_init, + .reconfig.write = s10_ops_write, + .reconfig.write_complete = s10_ops_write_complete, }; static int s10_probe(struct platform_device *pdev) diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c index 101f016c6ed8c..ab799aa05b9a2 100644 --- a/drivers/fpga/ts73xx-fpga.c +++ b/drivers/fpga/ts73xx-fpga.c @@ -98,10 +98,10 @@ static int ts73xx_fpga_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops ts73xx_fpga_ops = { - .state = ts73xx_fpga_state, - .write_init = ts73xx_fpga_write_init, - .write = ts73xx_fpga_write, - .write_complete = ts73xx_fpga_write_complete, + .state = ts73xx_fpga_state, + .reconfig.write_init = ts73xx_fpga_write_init, + .reconfig.write = ts73xx_fpga_write, + .reconfig.write_complete = ts73xx_fpga_write_complete, }; static int ts73xx_fpga_probe(struct platform_device *pdev) diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c index fee4d0abf6bfe..4d092f30bf700 100644 --- a/drivers/fpga/xilinx-spi.c +++ b/drivers/fpga/xilinx-spi.c @@ -214,10 +214,10 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr, } static const struct fpga_manager_ops xilinx_spi_ops = { - .state = xilinx_spi_state, - .write_init = xilinx_spi_write_init, - .write = xilinx_spi_write, - .write_complete = xilinx_spi_write_complete, + .state = xilinx_spi_state, + .reconfig.write_init = xilinx_spi_write_init, + .reconfig.write = xilinx_spi_write, + .reconfig.write_complete = xilinx_spi_write_complete, }; static int xilinx_spi_probe(struct spi_device *spi) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 07fa8d9ec6750..dde10f1ce1f57 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -543,11 +543,11 @@ static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) } static const struct fpga_manager_ops zynq_fpga_ops = { - .initial_header_size = 128, - .state = zynq_fpga_ops_state, - .write_init = zynq_fpga_ops_write_init, - .write_sg = zynq_fpga_ops_write, - .write_complete = zynq_fpga_ops_write_complete, + .initial_header_size = 128, + .state = zynq_fpga_ops_state, + .reconfig.write_init = zynq_fpga_ops_write_init, + .reconfig.write_sg = zynq_fpga_ops_write, + .reconfig.write_complete = zynq_fpga_ops_write_complete, }; static int zynq_fpga_probe(struct platform_device *pdev) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index 125743c9797ff..3bb9824a2a881 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -84,10 +84,10 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) } static const struct fpga_manager_ops zynqmp_fpga_ops = { - .state = zynqmp_fpga_ops_state, - .write_init = zynqmp_fpga_ops_write_init, - .write = zynqmp_fpga_ops_write, - .write_complete = zynqmp_fpga_ops_write_complete, + .state = zynqmp_fpga_ops_state, + .reconfig.write_init = zynqmp_fpga_ops_write_init, + .reconfig.write = zynqmp_fpga_ops_write, + .reconfig.write_complete = zynqmp_fpga_ops_write_complete, }; static int zynqmp_fpga_probe(struct platform_device *pdev) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 2bc3030a69e54..50a9fea3c47ef 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -106,14 +106,29 @@ struct fpga_image_info { }; /** - * struct fpga_manager_ops - ops for low level fpga manager drivers - * @initial_header_size: Maximum number of bytes that should be passed into write_init - * @state: returns an enum value of the FPGA's state - * @status: returns status of the FPGA, including reconfiguration error code + * struct fpga_manager_update_ops - ops updating fpga * @write_init: prepare the FPGA to receive confuration data * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA * @write_complete: set FPGA to operating state after writing is done + */ +struct fpga_manager_update_ops { + int (*write_init)(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count); + int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); + int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); + int (*write_complete)(struct fpga_manager *mgr, + struct fpga_image_info *info); +}; + +/** + * struct fpga_manager_ops - ops for low level fpga manager drivers + * @initial_header_size: Maximum number of bytes that should be passed into write_init + * @state: returns an enum value of the FPGA's state + * @status: returns status of the FPGA, including reconfiguration error code + * @partial_update: ops for doing partial reconfiguration + * @full_update: ops for doing a full card update, user,shell,fw ie. the works * @fpga_remove: optional: Set FPGA into a specific state during driver remove * @groups: optional attribute groups. * @@ -125,13 +140,8 @@ struct fpga_manager_ops { size_t initial_header_size; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); - int (*write_init)(struct fpga_manager *mgr, - struct fpga_image_info *info, - const char *buf, size_t count); - int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); - int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); - int (*write_complete)(struct fpga_manager *mgr, - struct fpga_image_info *info); + struct fpga_manager_update_ops reconfig; + struct fpga_manager_update_ops reimage; void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; From patchwork Mon May 24 16:27:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rix X-Patchwork-Id: 12276577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE4D2C04FF3 for ; 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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id b8sm3145797ots.6.2021.05.24.09.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:27:56 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Rix Subject: [PATCH v3 2/6] fpga: add FPGA_MGR_REIMAGE flag Date: Mon, 24 May 2021 09:27:52 -0700 Message-Id: <20210524162752.2221245-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix If this flag is set the reimage ops will be used otherwise the reconfig ops will be used to write the image Signed-off-by: Tom Rix --- include/linux/fpga/fpga-mgr.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 50a9fea3c47ef..bb11b18527326 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -67,12 +67,15 @@ enum fpga_mgr_states { * %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first * * %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed + * + * %FPGA_MGR_REIMAGE: Reimage the whole card, fpga bs and other device fw */ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) +#define FPGA_MGR_REIMAGE BIT(5) /** * struct fpga_image_info - information specific to a FPGA image From patchwork Mon May 24 16:28:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rix X-Patchwork-Id: 12276579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35486C04FF3 for ; Mon, 24 May 2021 16:28:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10992613CC for ; Mon, 24 May 2021 16:28:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233781AbhEXQ3m (ORCPT ); Mon, 24 May 2021 12:29:42 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:48412 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233159AbhEXQ3k (ORCPT ); Mon, 24 May 2021 12:29:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1621873692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=/bPnMh8D9HEJogKStb+MSo8WLoMkx+68yj+/mcrE5vw=; b=Ncj89Y63eIy4J9mxBhNJGsGNbOxgL6qalHoDKKy3dDumWoigqstMelxRFDdMvI2mK57F09 N1Dv4KgwFbQ7ByKDC/NM2FckKdd6dv1sCVPq/OkW/tTyTxdYS3713haJOC1Thwv/WRhxB5 ZoEs5kKZTq1qVqkHx3G+u0i+mifIqeI= Received: from mail-oo1-f72.google.com (mail-oo1-f72.google.com [209.85.161.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-336-diWn2h4bOvyoVbGi7VcFsg-1; Mon, 24 May 2021 12:28:10 -0400 X-MC-Unique: diWn2h4bOvyoVbGi7VcFsg-1 Received: by mail-oo1-f72.google.com with SMTP id u3-20020a4ad0c30000b02901fef88716cfso18332783oor.3 for ; Mon, 24 May 2021 09:28:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/bPnMh8D9HEJogKStb+MSo8WLoMkx+68yj+/mcrE5vw=; b=oOo6LIzYwH+njgXymhlw9vATLoanzILKh1GiFhk+0mKHoHQqPZlRO2bhIbDJweipYe 9BcyrJZRpOb/Ssz7wMOkb5XwvhNsnI4hHEYc1Ag7k1C8kd1yxnAH4sfF4fTCTWOu9jC7 7j5SSUciRbeloAz7jlqMa6FSNLqHYwe13vLrNxbwLmJZcvFMiFwyXdu8HHfNJL3FrFCO DAeEvZil+nmdnHjfzzDLYWEwgtcp2LzbUj2+JQu3ZO6N7OcsgXf4Ys9B/44KlTt+3uX/ N1nUnX0dJnnMlAW6kNbg6Y09It9tK5DN3dEXDkEAgoaDrqVeYk4H+6udx9GENHpeRpw9 Lmxw== X-Gm-Message-State: AOAM532tu7CY0tyVS8HwMGANzkq+n9lMM0R6r6npjmkMFNLr5hC6ehjW qJkgZlq8OZVM4a+Haf2GawI0Ti0o7Y3tqHlm2k1AwVVdEhFb8Ozfimu1F3TiVmzeX1VL3l0LqVm iM3FrK2pPGnUNwSbBWuqClw== X-Received: by 2002:a54:4d8b:: with SMTP id y11mr11248015oix.26.1621873689668; Mon, 24 May 2021 09:28:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxX3ed3rDvLKYSHOItIJT1bkLEuVLcaI5L5DaEegq62jGmP0UCGxQZdtyfVbl2T8BsTbjltpQ== X-Received: by 2002:a54:4d8b:: with SMTP id y11mr11248002oix.26.1621873689445; Mon, 24 May 2021 09:28:09 -0700 (PDT) Received: from localhost.localdomain.com (075-142-250-213.res.spectrum.com. [75.142.250.213]) by smtp.gmail.com with ESMTPSA id 73sm2676487oty.40.2021.05.24.09.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:28:08 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Rix Subject: [PATCH v3 3/6] fpga: pass fpga_manager_update_ops to the fpga_manager_write functions Date: Mon, 24 May 2021 09:28:05 -0700 Message-Id: <20210524162805.2221361-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix Refactor fpga_manager_write* functions for reimaging, pass the update_ops as a parameter. Only do the reconfig ops. Signed-off-by: Tom Rix --- drivers/fpga/fpga-mgr.c | 57 ++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 23 deletions(-) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index e3fc1b0bd7181..4263c9e94949d 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -77,16 +77,17 @@ EXPORT_SYMBOL_GPL(fpga_image_info_free); */ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, const char *buf, size_t count) { int ret; mgr->state = FPGA_MGR_STATE_WRITE_INIT; if (!mgr->mops->initial_header_size) - ret = mgr->mops->reconfig.write_init(mgr, info, NULL, 0); + ret = uops->write_init(mgr, info, NULL, 0); else - ret = mgr->mops->reconfig.write_init( - mgr, info, buf, min(mgr->mops->initial_header_size, count)); + ret = uops->write_init( + mgr, info, buf, min(mgr->mops->initial_header_size, count)); if (ret) { dev_err(&mgr->dev, "Error preparing FPGA for writing\n"); @@ -99,6 +100,7 @@ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, struct sg_table *sgt) { struct sg_mapping_iter miter; @@ -107,7 +109,7 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, int ret; if (!mgr->mops->initial_header_size) - return fpga_mgr_write_init_buf(mgr, info, NULL, 0); + return fpga_mgr_write_init_buf(mgr, info, uops, NULL, 0); /* * First try to use miter to map the first fragment to access the @@ -116,7 +118,7 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); if (sg_miter_next(&miter) && miter.length >= mgr->mops->initial_header_size) { - ret = fpga_mgr_write_init_buf(mgr, info, miter.addr, + ret = fpga_mgr_write_init_buf(mgr, info, uops, miter.addr, miter.length); sg_miter_stop(&miter); return ret; @@ -130,7 +132,7 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, mgr->mops->initial_header_size); - ret = fpga_mgr_write_init_buf(mgr, info, buf, len); + ret = fpga_mgr_write_init_buf(mgr, info, uops, buf, len); kfree(buf); @@ -142,12 +144,13 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, * finish and set the FPGA into operating mode. */ static int fpga_mgr_write_complete(struct fpga_manager *mgr, - struct fpga_image_info *info) + struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops) { int ret; mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE; - ret = mgr->mops->reconfig.write_complete(mgr, info); + ret = uops->write_complete(mgr, info); if (ret) { dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR; @@ -162,6 +165,7 @@ static int fpga_mgr_write_complete(struct fpga_manager *mgr, * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list * @mgr: fpga manager * @info: fpga image specific information + * @uops: which update ops to use * @sgt: scatterlist table * * Step the low level fpga manager through the device-specific steps of getting @@ -177,24 +181,25 @@ static int fpga_mgr_write_complete(struct fpga_manager *mgr, */ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, struct sg_table *sgt) { int ret; - ret = fpga_mgr_write_init_sg(mgr, info, sgt); + ret = fpga_mgr_write_init_sg(mgr, info, uops, sgt); if (ret) return ret; /* Write the FPGA image to the FPGA. */ mgr->state = FPGA_MGR_STATE_WRITE; - if (mgr->mops->reconfig.write_sg) { - ret = mgr->mops->reconfig.write_sg(mgr, sgt); + if (uops->write_sg) { + ret = uops->write_sg(mgr, sgt); } else { struct sg_mapping_iter miter; sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); while (sg_miter_next(&miter)) { - ret = mgr->mops->reconfig.write(mgr, miter.addr, miter.length); + ret = uops->write(mgr, miter.addr, miter.length); if (ret) break; } @@ -207,16 +212,17 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, return ret; } - return fpga_mgr_write_complete(mgr, info); + return fpga_mgr_write_complete(mgr, info, uops); } static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, const char *buf, size_t count) { int ret; - ret = fpga_mgr_write_init_buf(mgr, info, buf, count); + ret = fpga_mgr_write_init_buf(mgr, info, uops, buf, count); if (ret) return ret; @@ -224,20 +230,21 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, * Write the FPGA image to the FPGA. */ mgr->state = FPGA_MGR_STATE_WRITE; - ret = mgr->mops->reconfig.write(mgr, buf, count); + ret = uops->write(mgr, buf, count); if (ret) { dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); mgr->state = FPGA_MGR_STATE_WRITE_ERR; return ret; } - return fpga_mgr_write_complete(mgr, info); + return fpga_mgr_write_complete(mgr, info, uops); } /** * fpga_mgr_buf_load - load fpga from image in buffer * @mgr: fpga manager * @info: fpga image info + * @uops: which update ops to use * @buf: buffer contain fpga image * @count: byte count of buf * @@ -250,6 +257,7 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, */ static int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, const char *buf, size_t count) { struct page **pages; @@ -264,8 +272,8 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr, * contiguous kernel buffer and the driver doesn't require SG, non-SG * drivers will still work on the slow path. */ - if (mgr->mops->reconfig.write) - return fpga_mgr_buf_load_mapped(mgr, info, buf, count); + if (uops->write) + return fpga_mgr_buf_load_mapped(mgr, info, uops, buf, count); /* * Convert the linear kernel pointer into a sg_table of pages for use @@ -300,7 +308,7 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr, if (rc) return rc; - rc = fpga_mgr_buf_load_sg(mgr, info, &sgt); + rc = fpga_mgr_buf_load_sg(mgr, info, uops, &sgt); sg_free_table(&sgt); return rc; @@ -322,6 +330,7 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr, */ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, struct fpga_image_info *info, + const struct fpga_manager_update_ops *uops, const char *image_name) { struct device *dev = &mgr->dev; @@ -339,7 +348,7 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, return ret; } - ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size); + ret = fpga_mgr_buf_load(mgr, info, uops, fw->data, fw->size); release_firmware(fw); @@ -358,12 +367,14 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, */ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) { + const struct fpga_manager_update_ops *uops = &mgr->mops->reconfig; + if (info->sgt) - return fpga_mgr_buf_load_sg(mgr, info, info->sgt); + return fpga_mgr_buf_load_sg(mgr, info, uops, info->sgt); if (info->buf && info->count) - return fpga_mgr_buf_load(mgr, info, info->buf, info->count); + return fpga_mgr_buf_load(mgr, info, uops, info->buf, info->count); if (info->firmware_name) - return fpga_mgr_firmware_load(mgr, info, info->firmware_name); + return fpga_mgr_firmware_load(mgr, info, uops, info->firmware_name); return -EINVAL; } EXPORT_SYMBOL_GPL(fpga_mgr_load); From patchwork Mon May 24 16:28:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rix X-Patchwork-Id: 12276581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98913C2B9F7 for ; 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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id w13sm2691232otp.10.2021.05.24.09.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:28:24 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Rix Subject: [PATCH v3 4/6] fpga: defer checking for update ops until they are used Date: Mon, 24 May 2021 09:28:20 -0700 Message-Id: <20210524162820.2221474-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix Which update ops need to be used will depend on the FPGA_MGR_REIMAGE bit in the fpga_image_info flags. reimaging is optional, no drv that does not need to remimage should be forced to provide stub functions. Signed-off-by: Tom Rix --- drivers/fpga/fpga-mgr.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 4263c9e94949d..5247703a3743d 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -369,6 +369,14 @@ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) { const struct fpga_manager_update_ops *uops = &mgr->mops->reconfig; + if (!uops->write_complete || + !uops->write_init || + (!uops->write && !uops->write_sg) || + (uops->write && uops->write_sg)) { + dev_err(&mgr->dev, "Attempt to load an image without fpga_manager_update_ops\n"); + return -EOPNOTSUPP; + } + if (info->sgt) return fpga_mgr_buf_load_sg(mgr, info, uops, info->sgt); if (info->buf && info->count) @@ -579,10 +587,7 @@ struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, struct fpga_manager *mgr; int id, ret; - if (!mops || !mops->reconfig.write_complete || !mops->state || - !mops->reconfig.write_init || (!mops->reconfig.write && - !mops->reconfig.write_sg) || - (mops->reconfig.write && mops->reconfig.write_sg)) { + if (!mops || !mops->state) { dev_err(dev, "Attempt to register without fpga_manager_ops\n"); return NULL; } From patchwork Mon May 24 16:28:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rix X-Patchwork-Id: 12276583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A533FC04FF3 for ; Mon, 24 May 2021 16:28:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 89FC161402 for ; Mon, 24 May 2021 16:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233257AbhEXQaQ (ORCPT ); Mon, 24 May 2021 12:30:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:54250 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233026AbhEXQaQ (ORCPT ); Mon, 24 May 2021 12:30:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1621873728; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=rzVWT+hgucJulWTbb27JAU0YdQhBiQeXz3Y6dtzUOvc=; b=CKiOwBs86tuCfvZ7SLf2moKR38PHq5qGHiZvKIS4I0HbdKErjWSIIDZWzFHOU2MyJisjQ9 opBa9uLXzW2UQgjil33c67UhdLJ+EPdY0Cit1KdQhvU4fU2MtrYZvXC0MhdjKp4U0EPTU7 U79H4O4nBi0l3+NXGAdng1oxHu75g3Y= Received: from mail-ot1-f72.google.com (mail-ot1-f72.google.com [209.85.210.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-425-H0hom3wrMcyywE93bf6aIw-1; Mon, 24 May 2021 12:28:46 -0400 X-MC-Unique: H0hom3wrMcyywE93bf6aIw-1 Received: by mail-ot1-f72.google.com with SMTP id h8-20020a9d6a480000b02902edb9406104so20104563otn.5 for ; Mon, 24 May 2021 09:28:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rzVWT+hgucJulWTbb27JAU0YdQhBiQeXz3Y6dtzUOvc=; b=kP962BbKUHeM8/RHNjnbzRCuGz7L9zDIaNBmgkTnzILRHdtDE1NuxdNOenxUEw2dWd aDVr8XYm0SJbk5VJ0bkUVjCbgjTQxhAcYpOPBmck77h5oi2lj9txFvPOAxaNhZN4VzCP zzg0HdZ1FkJ8alnMFCkdYo99oUVeXm0TS/0ocSLNk8f5ftRbJ6j6bQv6GhGD+yG64xwb VwKEVmifHNDoBAnfRG5bBQuz/N/+blQ9qMLJcYMP2seeR9v+vysIIZSQ9LcHV+1P2pca ACwQa/EeC7Qa1iOOs/xY6yhIehNKHvrIM3uxO9imWnKMw6+ZgChgl+KZ0oSsgK2KZCOa f7sQ== X-Gm-Message-State: AOAM532lgJcUjBzwUI6CpJ2A61Ft2EdPOvTccXW3BNmdTL0kMCga52Dx b2Dq1jGp0yD7mpcj58WvcXQs7nJnMaskLRb5u8zXLzrJmXpt94INbu9P3T5TiQEUFZv80blvtIt 0ef62BfDdAOI9bhFpto62hw== X-Received: by 2002:aca:b3d5:: with SMTP id c204mr11039794oif.17.1621873725927; Mon, 24 May 2021 09:28:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZCllVamKPDAcqNe9vkFb8F/MCgjRAEAJeL9eXqfRMBxwbIVKkyvMaaHJTDZ2qwSv/+R2VXg== X-Received: by 2002:aca:b3d5:: with SMTP id c204mr11039784oif.17.1621873725765; Mon, 24 May 2021 09:28:45 -0700 (PDT) Received: from localhost.localdomain.com (075-142-250-213.res.spectrum.com. [75.142.250.213]) by smtp.gmail.com with ESMTPSA id q26sm3111066otn.0.2021.05.24.09.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:28:44 -0700 (PDT) From: trix@redhat.com To: mdf@kernel.org Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Rix Subject: [PATCH v3 5/6] fpga: use reimage ops in fpga_mgr_load() Date: Mon, 24 May 2021 09:28:37 -0700 Message-Id: <20210524162837.2221590-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix If the fpga_image_info flags FPGA_MGR_REIMAGE bit is set swap out the reconfig ops for the reimage ops and do the load. Signed-off-by: Tom Rix --- drivers/fpga/fpga-mgr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 5247703a3743d..34d251e87ca6c 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -369,6 +369,9 @@ int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) { const struct fpga_manager_update_ops *uops = &mgr->mops->reconfig; + if (info->flags & FPGA_MGR_REIMAGE) + uops = &mgr->mops->reimage; + if (!uops->write_complete || !uops->write_init || (!uops->write && !uops->write_sg) || From patchwork Mon May 24 16:28:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rix X-Patchwork-Id: 12276585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E157C04FF3 for ; Mon, 24 May 2021 16:29:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50E5561074 for ; Mon, 24 May 2021 16:29:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233903AbhEXQad (ORCPT ); Mon, 24 May 2021 12:30:33 -0400 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:54549 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233102AbhEXQac (ORCPT ); Mon, 24 May 2021 12:30:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1621873743; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=iuHQv14n2tXxpqovyIKwtgyxu4mGC8IYavS7rpI9Oy4=; b=DA5NPzozmIeyY29B9mE/7jLYvX/3SDOEfOWhF5QRXqWsSvS0BsWYEpX3WtK94EZ3UgE+aN bIEijKy1F8kbNkGgmNsb/AF+wBPmqzLBb0U2PMwgXk+hGrLkothqewLZnLDXqbPxK3hqki afCT2JMi+bJA47aAjambhkH1Tzzz/Po= Received: from mail-oo1-f69.google.com (mail-oo1-f69.google.com [209.85.161.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-409-y7to9ujTOnifJDU_4Fyyvw-1; Mon, 24 May 2021 12:29:02 -0400 X-MC-Unique: y7to9ujTOnifJDU_4Fyyvw-1 Received: by mail-oo1-f69.google.com with SMTP id e17-20020a4a55110000b029020eb08e4aedso12183810oob.20 for ; Mon, 24 May 2021 09:29:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=iuHQv14n2tXxpqovyIKwtgyxu4mGC8IYavS7rpI9Oy4=; b=N0VuWJdmK5oSb7JcWXieD18Kbtg5cOf3owrzfF/GqOaLTSwgBL5uQ5CVaIkQQKhW98 ybfhCnrU6/g8kJUNvvLGEWCnQJW/elOeMZjzd6eOFYFqaQi0smIoY7VvRjIX8Vtj0NuJ nW94QBd7vMykQ7Kmyyp4njHcQcHhxGRdme2ug4gy5dj+RjwZjexfxSZ0vmQmy/vBIsWO 9xo762S+p5ljhP811LKq93ul4YBoZ4nGn+DkXaeFiVTpgiZOC+MZvO4XQyuuuxGxlcHU /bJy4OTsfr6GZa8ZzOtr5M9LH5v+DySEz+Gus6lcp0E6tJoKkp56ProjMn/PeyElx2SB uCWA== X-Gm-Message-State: AOAM531lBDARUrZOiq5QJSj+Bq7/91Dbbp3zOb97PzEOOwTTmr4mKapX p+Z68RTn9yJ7MCgwC5H7F7StyAanL7CuU96Bh+sptSmMtwAj4v57Fo7TeGID8+dODCYHK5f1bmo d9GR9+GYfVD0ITJqYLVPTIg== X-Received: by 2002:a4a:b98e:: with SMTP id e14mr18812792oop.82.1621873741269; Mon, 24 May 2021 09:29:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTmqHUIDdCVBZGE0EV8HjMVsRSwgrvsrfeyd6RwEoiTCTj5mTJVeexy7zoapTfCbMk2Q2JwA== X-Received: by 2002:a4a:b98e:: with SMTP id e14mr18812775oop.82.1621873741071; Mon, 24 May 2021 09:29:01 -0700 (PDT) Received: from localhost.localdomain.com (075-142-250-213.res.spectrum.com. [75.142.250.213]) by smtp.gmail.com with ESMTPSA id v28sm2976981ood.27.2021.05.24.09.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:28:59 -0700 (PDT) From: trix@redhat.com To: hao.wu@intel.com, mdf@kernel.org Cc: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Rix Subject: [PATCH v3 6/6] fpga: dfl: stub in reimaging Date: Mon, 24 May 2021 09:28:55 -0700 Message-Id: <20210524162855.2221757-1-trix@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tom Rix Generalize the pr writer to handle reimaging. Rename the input structure and add the DFL_FPGA_FME_REIMAGE ioctl. Stub in reimage.write* ops Signed-off-by: Tom Rix --- drivers/fpga/dfl-fme-mgr.c | 28 ++++++++++++++++++++++++ drivers/fpga/dfl-fme-pr.c | 40 +++++++++++++++++++++-------------- include/uapi/linux/fpga-dfl.h | 18 +++++++++++++--- 3 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index 89913d27d877c..84bf431583005 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -252,6 +252,31 @@ static int fme_mgr_write_complete(struct fpga_manager *mgr, return 0; } +static int fme_mgr_reimage_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct device *dev = &mgr->dev; + + if (!(info->flags & FPGA_MGR_REIMAGE)) { + dev_err(dev, "only supports reimaging.\n"); + return -EINVAL; + } + return -EOPNOTSUPP; +} + +static int fme_mgr_reimage_write(struct fpga_manager *mgr, + const char *buf, size_t count) +{ + return -EOPNOTSUPP; +} + +static int fme_mgr_reimage_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return -EOPNOTSUPP; +} + static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr) { return FPGA_MGR_STATE_UNKNOWN; @@ -270,6 +295,9 @@ static const struct fpga_manager_ops fme_mgr_ops = { .reconfig.write_init = fme_mgr_write_init, .reconfig.write = fme_mgr_write, .reconfig.write_complete = fme_mgr_write_complete, + .reimage.write_init = fme_mgr_reimage_write_init, + .reimage.write = fme_mgr_reimage_write, + .reimage.write_complete = fme_mgr_reimage_write_complete, }; static void fme_mgr_get_compat_id(void __iomem *fme_pr, diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c index 1194c0e850e07..2fc3ad92c8036 100644 --- a/drivers/fpga/dfl-fme-pr.c +++ b/drivers/fpga/dfl-fme-pr.c @@ -63,11 +63,11 @@ static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id) return region; } -static int fme_pr(struct platform_device *pdev, unsigned long arg) +static int fme_image(struct platform_device *pdev, unsigned long arg, bool pr) { struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); void __user *argp = (void __user *)arg; - struct dfl_fpga_fme_port_pr port_pr; + struct dfl_fpga_fme_image image; struct fpga_image_info *info; struct fpga_region *region; void __iomem *fme_hdr; @@ -78,12 +78,12 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) int ret = 0; u64 v; - minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address); + minsz = offsetofend(struct dfl_fpga_fme_image, buffer_address); - if (copy_from_user(&port_pr, argp, minsz)) + if (copy_from_user(&image, argp, minsz)) return -EFAULT; - if (port_pr.argsz < minsz || port_pr.flags) + if (image.argsz < minsz || image.flags) return -EINVAL; /* get fme header region */ @@ -91,25 +91,27 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) FME_FEATURE_ID_HEADER); /* check port id */ - v = readq(fme_hdr + FME_HDR_CAP); - if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) { - dev_dbg(&pdev->dev, "port number more than maximum\n"); - return -EINVAL; + if (pr) { + v = readq(fme_hdr + FME_HDR_CAP); + if (image.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) { + dev_dbg(&pdev->dev, "port number more than maximum\n"); + return -EINVAL; + } } /* * align PR buffer per PR bandwidth, as HW ignores the extra padding * data automatically. */ - length = ALIGN(port_pr.buffer_size, 4); + length = ALIGN(image.buffer_size, 4); buf = vmalloc(length); if (!buf) return -ENOMEM; if (copy_from_user(buf, - (void __user *)(unsigned long)port_pr.buffer_address, - port_pr.buffer_size)) { + (void __user *)(unsigned long)image.buffer_address, + image.buffer_size)) { ret = -EFAULT; goto free_exit; } @@ -121,7 +123,10 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) goto free_exit; } - info->flags |= FPGA_MGR_PARTIAL_RECONFIG; + if (pr) + info->flags |= FPGA_MGR_PARTIAL_RECONFIG; + else + info->flags |= FPGA_MGR_REIMAGE; mutex_lock(&pdata->lock); fme = dfl_fpga_pdata_get_private(pdata); @@ -131,7 +136,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) goto unlock_exit; } - region = dfl_fme_region_find(fme, port_pr.port_id); + region = dfl_fme_region_find(fme, pr ? image.port_id : 0); if (!region) { ret = -EINVAL; goto unlock_exit; @@ -141,7 +146,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) info->buf = buf; info->count = length; - info->region_id = port_pr.port_id; + info->region_id = image.port_id; region->info = info; ret = fpga_region_program_fpga(region); @@ -457,7 +462,10 @@ static long fme_pr_ioctl(struct platform_device *pdev, switch (cmd) { case DFL_FPGA_FME_PORT_PR: - ret = fme_pr(pdev, arg); + ret = fme_image(pdev, arg, true); + break; + case DFL_FPGA_FME_REIMAGE: + ret = fme_image(pdev, arg, false); break; default: ret = -ENODEV; diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h index 1621b077bf212..2f633ca859763 100644 --- a/include/uapi/linux/fpga-dfl.h +++ b/include/uapi/linux/fpga-dfl.h @@ -214,7 +214,7 @@ struct dfl_fpga_irq_set { /** * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, - * struct dfl_fpga_fme_port_pr) + * struct dfl_fpga_fme_image) * * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) * provided by caller. @@ -224,13 +224,13 @@ struct dfl_fpga_irq_set { * from the status of FME's fpga manager. */ -struct dfl_fpga_fme_port_pr { +struct dfl_fpga_fme_image { /* Input */ __u32 argsz; /* Structure length */ __u32 flags; /* Zero for now */ __u32 port_id; __u32 buffer_size; - __u64 buffer_address; /* Userspace address to the buffer for PR */ + __u64 buffer_address; /* Userspace address to the buffer for image */ }; #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) @@ -276,4 +276,16 @@ struct dfl_fpga_fme_port_pr { DFL_FME_BASE + 4, \ struct dfl_fpga_irq_set) +/** + * DFL_FPGA_FME_REIMAGE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 5, + * struct dfl_fpga_fme_image) + * + * Driver reimages the whole board with the Buffer (Image) provided by caller. + * Return: 0 on success, -errno on failure. + * If DFL_FPGA_FME_REIMAGE returns -EIO, that indicates the HW has detected + * some errors during PR, under this case, the user can fetch HW error info + * from the status of FME's fpga manager. + */ +#define DFL_FPGA_FME_REIMAGE _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 5) + #endif /* _UAPI_LINUX_FPGA_DFL_H */