From patchwork Wed May 26 05:17:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Upadhyay X-Patchwork-Id: 12280651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A0D9C2B9F7 for ; Wed, 26 May 2021 05:26:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3585861184 for ; Wed, 26 May 2021 05:26:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3585861184 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F9D06E48C; Wed, 26 May 2021 05:26:43 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 43E436E47B for ; Wed, 26 May 2021 05:26:41 +0000 (UTC) IronPort-SDR: YbB7JqVEay/9W0u4xwvlKp42WdRrFAzWNofYUH4jPizhd4okQ8GDPAMDAjysus/FD9+TKt99IT pI7/0aBrNQ7A== X-IronPort-AV: E=McAfee;i="6200,9189,9995"; a="182024461" X-IronPort-AV: E=Sophos;i="5.82,330,1613462400"; d="scan'208";a="182024461" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2021 22:26:39 -0700 IronPort-SDR: hCnQ4J2zRHi+HsiaeE+Cto6xYGWVD/TTUBmDNgXMDEgxLcgtzfc4GmQFz9Ced3F/4XhmiP0IYS +wuu5DlJ/Uiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,330,1613462400"; d="scan'208";a="630589096" Received: from tejas-system-product-name.iind.intel.com ([10.145.162.130]) by fmsmga006.fm.intel.com with ESMTP; 25 May 2021 22:26:37 -0700 From: Tejas Upadhyay To: intel-gfx@lists.freedesktop.org, mahesh.meena@intel.com Date: Wed, 26 May 2021 10:47:10 +0530 Message-Id: <20210526051710.332081-2-tejaskumarx.surendrakumar.upadhyay@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210526051710.332081-1-tejaskumarx.surendrakumar.upadhyay@intel.com> References: <20210526051710.332081-1-tejaskumarx.surendrakumar.upadhyay@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 1/1] drm/i915/gt: Declare when we enabled timeslicing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING V3: %s/TIMESLICE_BIT/HAS_TIMESLICES v2: Only declare timeslicing if we can safely preempt userspace. Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + include/uapi/drm/i915_drm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 3cca7ea2d6ea..5123cc02efdb 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) MAP(HAS_PREEMPTION, PREEMPTION), MAP(HAS_SEMAPHORES, SEMAPHORES), MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), + MAP(HAS_TIMESLICES, TIMESLICING), #undef MAP }; struct intel_engine_cs *engine; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index c2c7759b7d2e..af2212d6113c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) #define I915_PARAM_HUC_STATUS 42