From patchwork Sat May 29 19:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288021 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C48D1C47082 for ; Sat, 29 May 2021 19:25:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9699B610CC for ; Sat, 29 May 2021 19:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229795AbhE2T1S (ORCPT ); Sat, 29 May 2021 15:27:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229849AbhE2T1R (ORCPT ); Sat, 29 May 2021 15:27:17 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AA30C061574; Sat, 29 May 2021 12:25:39 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id v13so3206607ple.9; Sat, 29 May 2021 12:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vAZTeFvhwbvSe7oF4PDVTYIaZK2+/OwW66DCRQJ9boA=; b=Vd92Bkyd3QML0z9CXBD6CZyzIHIq01DaEjEQpW5akC/q7FZgElSvWEDhq/apDLXRfq dmDj6lAltQPInYhLYn1t5R+aT+OWDJoHkZZOxXJQdnBV6G60Zw6Im5tkNNDEH5VrziHF xiOL5NCfnTilWFi7OXZe1lSsnwLZbwulJl7XRzOMYviGA6HNE1tn9MHvLp1TQsNz1D+d 5Djp7IUMDL1nv97J0mAV08DuWsojuBZrpTq7qElRnXSpD5t59Lc7Xc6wDTYw80aEJhUR +MX13tq0C4q0UzSbQgHfEOpMiPPaZIf7Tb5DNKCQW4LWb5nOvxvj87xZPr39DszdaHnU WqqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vAZTeFvhwbvSe7oF4PDVTYIaZK2+/OwW66DCRQJ9boA=; b=Ce11tch/uP9wi42oqfo1DFmdJQ4pUlC7SEV1jwobJhtgSzlCZ8QKf/zoJDy9RU9rIe kvbFKvaqyfoZVHl1vAWl6AEdlloCq23oWlyj1N+cHBCzrQ90hyHas4HKkU+7vzvD98+V Z45EU7yyZqTaYiIUUnUFoywWWS2Fb/x6Ov+KeoAmF+590loAwsEwaB6NX3nfMjE7xfip pmT2EOLw0lCzjMXK6dnz1PHKHQeoD9hctw67VCNvR68iaRwRvyj3tjPd0zIr7AEe6w+6 GDJgLalkx/jXCdHHDMQHx5FhzfKeb3Ye99Ig7JGR3oCF1jnxpLimypf1Xv31UTP1654Z UuPg== X-Gm-Message-State: AOAM530kSig5dR2KCWmT1pezaNfrg/iQ2laQvuYFPVQcRpMqvRkfmzq8 kJ+Ed5abypUtwzsR1rFewl4= X-Google-Smtp-Source: ABdhPJzl6sknRO/oljiEcver3cwsm0lw4qfSb1Ex5Olx2yp8hG8XcJA+x91WW9F9FfHcxvo0vA2bbw== X-Received: by 2002:a17:902:e04f:b029:eb:66b0:6d08 with SMTP id x15-20020a170902e04fb02900eb66b06d08mr13602989plx.50.1622316338539; Sat, 29 May 2021 12:25:38 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:38 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v5 1/7] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Date: Sun, 30 May 2021 00:55:21 +0530 Message-Id: <20210529192527.2708-2-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently there is separate function pcie_has_flr to probe if pcie flr is supported by the device which does not match the calling convention followed by reset methods which use second function argument to decide whether to probe or not. Add new function pcie_reset_flr that follows the calling convention of reset methods. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +- drivers/pci/pci.c | 62 ++++++++++++---------- drivers/pci/pcie/aer.c | 12 ++--- drivers/pci/quirks.c | 9 ++-- include/linux/pci.h | 2 +- 5 files changed, 43 insertions(+), 46 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index facc8e6bc..15d6c8452 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - /* check flr support */ - if (pcie_has_flr(pdev)) - pcie_flr(pdev); + pcie_reset_flr(pdev, 0); pci_restore_state(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 452351025..3bf36924c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4611,32 +4611,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -/** - * pcie_has_flr - check if a device supports function level resets - * @dev: device to check - * - * Returns true if the device advertises support for PCIe function level - * resets. - */ -bool pcie_has_flr(struct pci_dev *dev) -{ - u32 cap; - - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) - return false; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; -} -EXPORT_SYMBOL_GPL(pcie_has_flr); - /** * pcie_flr - initiate a PCIe function level reset * @dev: device to reset * - * Initiate a function level reset on @dev. The caller should ensure the - * device supports FLR before calling this function, e.g. by using the - * pcie_has_flr() helper. + * Initiate a function level reset unconditionally on @dev without + * checking any flags and DEVCAP */ int pcie_flr(struct pci_dev *dev) { @@ -4659,6 +4639,31 @@ int pcie_flr(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pcie_flr); +/** + * pcie_reset_flr - initiate a PCIe function level reset + * @dev: device to reset + * @probe: If set, only check if the device can be reset this way. + * + * Initiate a function level reset on @dev. + */ +int pcie_reset_flr(struct pci_dev *dev, int probe) +{ + u32 cap; + + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) + return -ENOTTY; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (!(cap & PCI_EXP_DEVCAP_FLR)) + return -ENOTTY; + + if (probe) + return 0; + + return pcie_flr(dev); +} +EXPORT_SYMBOL_GPL(pcie_reset_flr); + static int pci_af_flr(struct pci_dev *dev, int probe) { int pos; @@ -5139,11 +5144,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 0); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - if (rc != -ENOTTY) - return rc; - } + rc = pcie_reset_flr(dev, 0); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) return rc; @@ -5174,8 +5177,9 @@ int pci_probe_reset_function(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 1); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) - return 0; + rc = pcie_reset_flr(dev, 1); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 1); if (rc != -ENOTTY) return rc; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ec943cee5..98077595a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,13 +1405,11 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - pci_info(dev, "has been reset (%d)\n", rc); - } else { - pci_info(dev, "not reset (no FLR support)\n"); - rc = -ENOTTY; - } + rc = pcie_reset_flr(dev, 0); + if (!rc) + pci_info(dev, "has been reset\n"); + else + pci_info(dev, "not reset (no FLR support: %d)\n", rc); } else { rc = pci_bus_error_reset(dev); pci_info(dev, "%s Port link has been reset (%d)\n", diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d85914afe..f977ba79a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3819,7 +3819,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) return -ENOTTY; if (probe) @@ -3888,13 +3888,10 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) */ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) { - if (!pcie_has_flr(dev)) - return -ENOTTY; + int ret = pcie_reset_flr(dev, probe); if (probe) - return 0; - - pcie_flr(dev); + return ret; msleep(250); diff --git a/include/linux/pci.h b/include/linux/pci.h index c20211e59..20b90c205 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1225,7 +1225,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -bool pcie_has_flr(struct pci_dev *dev); +int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Sat May 29 19:25:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288023 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7A87C47090 for ; Sat, 29 May 2021 19:25:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A552D610FC for ; Sat, 29 May 2021 19:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229864AbhE2T1T (ORCPT ); Sat, 29 May 2021 15:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbhE2T1S (ORCPT ); Sat, 29 May 2021 15:27:18 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3501AC061574; Sat, 29 May 2021 12:25:42 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id v12so3207089plo.10; Sat, 29 May 2021 12:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=29N2RGXp6yuyHENFWANA6iVksXjLMoovSI9EBMet6jE=; b=OATYX1Xznn/Z8EYaEU56WkkSxAY2+siL83yezmAu5YOi1Luh0lKcEESEuQmNpgLqWc s/fyfB+cFA1mHYdHcnux7ocACgzl6BJbesnwvMamMWAlvSc6OJIYVQzkZbBET9B8Wbg0 2t2zV472BodEl3XAqchojeL3mYs5RDE+naiufHLSBeekO/BW45ysgq3jkF1cjcJIFLoH x2KcCXhWLHRF6vdC9dLdsiX0ElRwyQ32M1uB6YBd79XL/WSUl4d95wHggAcMaLlHCPYu N+hcZkV70o7A9nI2aa1V3bpMNg8boWwPXPkULa0AmmFzcBPyMcvZzmsKy3OhmHEX484L hlKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=29N2RGXp6yuyHENFWANA6iVksXjLMoovSI9EBMet6jE=; b=bLpsI/FMk/v61YL1gI0YpPgz2t5wQoi4cXYlUbk6qSolY/m6O1inj2jLQaSbY+1VIx ECckfHLJVUxQt6AJfp2/0nkjAAo8P2FL06gSiu2/3gO+3W9v6lO3i7wYB+kp2kVru9pY KlHM0jdQHbL/i8KW1Y+vYdEezFZVHr4QueUa4mfum8E1kyUvL6xT4VZRKbLnGgQoEzBp c2ppftWjELc7CQWSgyu89fTZg+16WdApH2k8AQml9c9IOYiyYq/iBgNLvTdPmHCTsQv7 kTohG8P4d3m/JfwRpWUm5mwpsm6Dc8eHlsHGffvAKTAvmxZB+JEHh+7lH1YPjege3KO2 UB8w== X-Gm-Message-State: AOAM5304WfawbCS6s8oXcdUv3NTp2alyP3VSeWTCqzB7Pz7jPm/AMjX0 l6Oifz0CxUOBJWti0wR2OF0= X-Google-Smtp-Source: ABdhPJxM1PFXpBMFFB4CBIcZZoJfPFo3nFjsFVPS8z2T7dCO+KRMJmWaB/038tStp89+2I8XS4ILfQ== X-Received: by 2002:a17:902:d507:b029:f2:c88c:5b45 with SMTP id b7-20020a170902d507b02900f2c88c5b45mr13849798plg.66.1622316341718; Sat, 29 May 2021 12:25:41 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:41 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v5 2/7] PCI: Add new array for keeping track of ordering of reset methods Date: Sun, 30 May 2021 00:55:22 +0530 Message-Id: <20210529192527.2708-3-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new array reset_methods in struct pci_dev to keep track of reset mechanisms supported by the device and their ordering. Also refactor probing and reset functions to take advantage of calling convention of reset functions. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Tested-by: Shanker Donthineni --- drivers/pci/pci.c | 107 ++++++++++++++++++++++++++------------------ drivers/pci/pci.h | 8 +++- drivers/pci/probe.c | 5 +-- include/linux/pci.h | 7 +++ 4 files changed, 80 insertions(+), 47 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 3bf36924c..67a2605d4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -72,6 +72,14 @@ static void pci_dev_d3_sleep(struct pci_dev *dev) msleep(delay); } +bool pci_reset_supported(struct pci_dev *dev) +{ + u8 null_reset_methods[PCI_RESET_METHODS_NUM] = { 0 }; + + return memcmp(null_reset_methods, + dev->reset_methods, PCI_RESET_METHODS_NUM); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -5107,6 +5115,19 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/* + * The ordering for functions in pci_reset_fn_methods + * is required for reset_methods byte array defined + * in struct pci_dev. + */ +const struct pci_reset_fn_method pci_reset_fn_methods[] = { + { &pci_dev_specific_reset, .name = "device_specific" }, + { &pcie_reset_flr, .name = "flr" }, + { &pci_af_flr, .name = "af_flr" }, + { &pci_pm_reset, .name = "pm" }, + { &pci_reset_bus_function, .name = "bus" }, +}; + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5129,65 +5150,65 @@ static void pci_dev_restore(struct pci_dev *dev) */ int __pci_reset_function_locked(struct pci_dev *dev) { - int rc; + int i, rc = -ENOTTY; + u8 prio; might_sleep(); - /* - * A reset method returns -ENOTTY if it doesn't support this device - * and we should try the next method. - * - * If it returns 0 (success), we're finished. If it returns any - * other error, we're also finished: this indicates that further - * reset mechanisms might be broken on the device. - */ - rc = pci_dev_specific_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_reset_bus_function(dev, 0); + for (prio = PCI_RESET_METHODS_NUM; prio; prio--) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (dev->reset_methods[i] == prio) { + /* + * A reset method returns -ENOTTY if it doesn't support this device + * and we should try the next method. + * + * If it returns 0 (success), we're finished. If it returns any + * other error, we're also finished: this indicates that further + * reset mechanisms might be broken on the device. + */ + rc = pci_reset_fn_methods[i].reset_fn(dev, 0); + if (rc != -ENOTTY) + return rc; + break; + } + } + if (i == PCI_RESET_METHODS_NUM) + break; + } + return rc; } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); /** - * pci_probe_reset_function - check whether the device can be safely reset - * @dev: PCI device to reset + * pci_init_reset_methods - check whether device can be safely reset + * and store supported reset mechanisms. + * @dev: PCI device to check for reset mechanisms * * Some devices allow an individual function to be reset without affecting * other functions in the same device. The PCI device must be responsive - * to PCI config space in order to use this function. + * to reads and writes to its PCI config space in order to use this function. * - * Returns 0 if the device function can be reset or negative if the - * device doesn't support resetting a single function. + * Stores reset mechanisms supported by device in reset_methods byte array + * which is a member of struct pci_dev. */ -int pci_probe_reset_function(struct pci_dev *dev) +void pci_init_reset_methods(struct pci_dev *dev) { - int rc; + int i, rc; + u8 prio = PCI_RESET_METHODS_NUM; + u8 reset_methods[PCI_RESET_METHODS_NUM] = { 0 }; - might_sleep(); + BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_RESET_METHODS_NUM); - rc = pci_dev_specific_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; + might_sleep(); - return pci_reset_bus_function(dev, 1); + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + if (!rc) + reset_methods[i] = prio--; + else if (rc != -ENOTTY) + break; + } + memcpy(dev->reset_methods, reset_methods, sizeof(reset_methods)); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 37c913bbc..13ec6bd6f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -33,7 +33,7 @@ enum pci_mmap_api { int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, enum pci_mmap_api mmap_api); -int pci_probe_reset_function(struct pci_dev *dev); +void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); @@ -606,6 +606,12 @@ struct pci_dev_reset_methods { int (*reset)(struct pci_dev *dev, int probe); }; +struct pci_reset_fn_method { + int (*reset_fn)(struct pci_dev *pdev, int probe); + char *name; +}; + +extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_reset(struct pci_dev *dev, int probe); #else diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3a62d09b8..8cf532681 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2404,9 +2404,8 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - - if (pci_probe_reset_function(dev) == 0) - dev->reset_fn = 1; + pci_init_reset_methods(dev); + dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 20b90c205..0955246f8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,6 +49,8 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) +#define PCI_RESET_METHODS_NUM 5 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -505,6 +507,10 @@ struct pci_dev { char *driver_override; /* Driver name to force a match */ unsigned long priv_flags; /* Private flags for the PCI driver */ + /* + * See pci_reset_fn_methods array in pci.c for ordering. + */ + u8 reset_methods[PCI_RESET_METHODS_NUM]; /* Reset methods ordered by priority */ }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) @@ -1227,6 +1233,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, void pcie_print_link_status(struct pci_dev *dev); int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); +bool pci_reset_supported(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); int pci_reset_function_locked(struct pci_dev *dev); From patchwork Sat May 29 19:25:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288025 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA4FAC47091 for ; Sat, 29 May 2021 19:25:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCFD9610FC for ; Sat, 29 May 2021 19:25:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229902AbhE2T1Z (ORCPT ); Sat, 29 May 2021 15:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbhE2T1X (ORCPT ); Sat, 29 May 2021 15:27:23 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DC04C061760; Sat, 29 May 2021 12:25:45 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id ot16so4377494pjb.3; Sat, 29 May 2021 12:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5gbH+EkegZ9klFCOPnjCh9VGgD5fmMtWOgu8Ht+xJEI=; b=hb/4h3ZDpYFUbhzImSKp0+kdhvjhFoqum9bpCoiM9MtfpWBdAsndYS1N+vQMWGN3J6 csod1L6ViFhmEsIWPldfvdNG1hotqNpc0kzI88Vzp9cEdLuj1oUIRCn5GFB1elvsk6oT T+0WFzJA0a3ZU1a8kxtc9K44RpJAMMYUGtNuPX0Ux8EzEjyebapaQOaUcm48xoAW+LBg R8W9kjifxtjx/Wh1NeRrsedS5iFFSlF4aSp4/0M6SWgGNEOWjDLECzlEDmCTdwr0BrN4 g5gjJ3u1UDtl/ZugUvPtvlRcRrG0ciU9Zjn8h8aPdY8KFlIWNJaJD8bBjOuc9D9KuRfF H1+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5gbH+EkegZ9klFCOPnjCh9VGgD5fmMtWOgu8Ht+xJEI=; b=cDILAqm2I+6XbjGqx3tvB1PSwotSl6RupKRx5r7+uZ2/AoY2NaE/sNKY+z1xstIXLg TqdLHf6hExB3uP+8dcVXL+/4lMR2LrbOdTmzbqSjZzX+kfpDCHBbruo+J0K7J6QItfW2 Ih+N9S48BNCeZWn2mcnMsYVeHrExlTxW5Io7UiZI4dJJH1BWYvml5Qj13MSeGGB4aZNV PdXXamnBuYC40VE5rF/m7D86er0/WS28nivMv4Fd6XeujbIP8AHV7oCsJak4KyocBP6o ELupWhGHGL9x///yWkr/8IYOX2/kDIEnsgzmPm6pHRbkaZXR/w55nvdRoILQ/7cBnWHt 12iQ== X-Gm-Message-State: AOAM5315Kz2GMjhSPOInW+4dkn/sQsBLuXwScz5Keheq5pG5gJOAR0a/ LrzO9fRZsP6taI1if43307I= X-Google-Smtp-Source: ABdhPJwMq3QNQFcQbpge39ElWOodmxtNsPV3i7u+GcdC1pCXAaDnA02ft/fgai1eSDvoR43dmj2zpg== X-Received: by 2002:a17:902:9886:b029:f9:c8d6:4cee with SMTP id s6-20020a1709029886b02900f9c8d64ceemr13435850plp.82.1622316344872; Sat, 29 May 2021 12:25:44 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:44 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v5 3/7] PCI: Remove reset_fn field from pci_dev Date: Sun, 30 May 2021 00:55:23 +0530 Message-Id: <20210529192527.2708-4-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org reset_fn field is used to indicate whether the device supports any reset mechanism or not. Deprecate use of reset_fn in favor of new reset_methods array which can be used to keep track of all supported reset mechanisms of a device and their ordering. The octeon driver is incorrectly using reset_fn field to detect if the device supports FLR or not. Use pcie_reset_flr to probe whether it supports FLR or not. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Tested-by: Shanker Donthineni --- drivers/net/ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 6 +++--- drivers/pci/probe.c | 1 - drivers/pci/quirks.c | 2 +- drivers/pci/remove.c | 1 - include/linux/pci.h | 1 - 7 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 516f166ce..336d149ee 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (oct->pci_dev->reset_fn) + if (!pcie_reset_flr(oct->pci_dev, 1)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index beb8d1f4f..316f70c3e 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1367,7 +1367,7 @@ static umode_t pci_dev_reset_attr_is_visible(struct kobject *kobj, { struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); - if (!pdev->reset_fn) + if (!pci_reset_supported(pdev)) return 0; return a->mode; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 67a2605d4..bbed852d9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5231,7 +5231,7 @@ int pci_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_lock(dev); @@ -5267,7 +5267,7 @@ int pci_reset_function_locked(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_save_and_disable(dev); @@ -5290,7 +5290,7 @@ int pci_try_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; if (!pci_dev_trylock(dev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8cf532681..90fd4f61f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2405,7 +2405,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pcie_report_downtraining(dev); pci_init_reset_methods(dev); - dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f977ba79a..e86cf4a3b 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5589,7 +5589,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || pdev->subsystem_device != 0x222e || - !pdev->reset_fn) + !pci_reset_supported(pdev)) return; if (pci_enable_device_mem(pdev)) diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index dd12c2fcc..4c54c7505 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -19,7 +19,6 @@ static void pci_stop_dev(struct pci_dev *dev) pci_pme_active(dev, false); if (pci_dev_is_added(dev)) { - dev->reset_fn = 0; device_release_driver(&dev->dev); pci_proc_detach_device(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 0955246f8..6e9bc4f9c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -429,7 +429,6 @@ struct pci_dev { unsigned int state_saved:1; unsigned int is_physfn:1; unsigned int is_virtfn:1; - unsigned int reset_fn:1; unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ From patchwork Sat May 29 19:25:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288027 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E827C47093 for ; Sat, 29 May 2021 19:25:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59C8D6113E for ; Sat, 29 May 2021 19:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229928AbhE2T12 (ORCPT ); Sat, 29 May 2021 15:27:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229905AbhE2T10 (ORCPT ); Sat, 29 May 2021 15:27:26 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 851D4C061574; Sat, 29 May 2021 12:25:48 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id p39so5852074pfw.8; Sat, 29 May 2021 12:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9MvIdKhfq+0Mdk+szDC0tPoyoxwUROEYUAQaW6Hav6U=; b=hwN4ZdnjqDq5XpqauPc1yVGso8hRDB5GFuQuIng3qX4nIdWH71G/9tGKPYD6LZ5omu 7AWbZUEE8szBScckodxmrcjbKz9O8UOHTBfyveJwSvkPGwMcUdFUVbEEnRc4YlbQvj28 rhz+1yaC3VJmpIzaEVQe2+LaNzj7polJ4c+nE8Wmv2Kdunpht2gXK9UA0QFbnYRxz0cN ABSvZXITZMGo+DgLQBPnJq/zuTFowyYpWh6TTV7+z8wzPgpwKcz7QhaOykVCMfkhePco U4sV1WvNce/xvFRyIUuUgelPNxegso0kStdr/MeRQs73VSyq20iFWgxNR/+Oo67IsdSF KIAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9MvIdKhfq+0Mdk+szDC0tPoyoxwUROEYUAQaW6Hav6U=; b=CSM+nz0HTDRYZNXLJvLR+qOur5x6uaDjEn8U8Cu/7zb6m0EvYqDxBAf/wamGMSz65/ JvsSTffU+R47v+KFLpvlybS/OtRuRwVsnvYEw3RJ3nyfo4497kZAqMbvrSiRD7C57l5p ZVICy+sAlV6dufRrXsMhDGKB6gNPTqdDrpeV7B7Yq2oHgLUQGD3gIlU6WDN1y/Gmg+dL 1wn7NGSiP12lFnBvSz+Y9FiGnUJMzX/EkgggAwruRvG5I+hIFpbExF4dgP1+g4J767Jd WcJyK4FQKuzaepmQfXWjChUAdvchpA2uDALVCQoRa9XIFOZFD26qu3OezpU9Shk6dxzg MuMQ== X-Gm-Message-State: AOAM530IUjj2pxPD1fF36nmzOTV5k6kLNE6F4Mh64yU3q6RPvRNeq6dq 1p477fgxDiYjN3WHX7TUY8o= X-Google-Smtp-Source: ABdhPJyU22Er6YJCWflyaqNxjxaU6VtBu4ZlxRf/dj7qptIoAL7+HL+sw91s/Kxd3xDWYEkH90uxuw== X-Received: by 2002:a62:860b:0:b029:28e:d45b:4d2e with SMTP id x11-20020a62860b0000b029028ed45b4d2emr9928353pfd.70.1622316348062; Sat, 29 May 2021 12:25:48 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:47 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v5 4/7] PCI/sysfs: Allow userspace to query and set device reset mechanism Date: Sun, 30 May 2021 00:55:24 +0530 Message-Id: <20210529192527.2708-5-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add reset_method sysfs attribute to enable user to query and set user preferred device reset methods and their ordering. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Tested-by: Shanker Donthineni --- Documentation/ABI/testing/sysfs-bus-pci | 16 ++++ drivers/pci/pci-sysfs.c | 105 ++++++++++++++++++++++++ 2 files changed, 121 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index ef00fada2..cf6dbbb3c 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -121,6 +121,22 @@ Description: child buses, and re-discover devices removed earlier from this part of the device tree. +What: /sys/bus/pci/devices/.../reset_method +Date: March 2021 +Contact: Amey Narkhede +Description: + Some devices allow an individual function to be reset + without affecting other functions in the same slot. + For devices that have this support, a file named reset_method + will be present in sysfs. Reading this file will give names + of the device supported reset methods and their ordering. + Writing the name or comma separated list of names of any of + the device supported reset methods to this file will set the + reset methods and their ordering to be used when resetting + the device. Writing empty string to this file will disable + ability to reset the device and writing "default" will return + to the original value. + What: /sys/bus/pci/devices/.../reset Date: July 2009 Contact: Michael S. Tsirkin diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 316f70c3e..04b3d6565 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1334,6 +1334,110 @@ static const struct attribute_group pci_dev_rom_attr_group = { .is_bin_visible = pci_dev_rom_attr_is_visible, }; +static ssize_t reset_method_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + ssize_t len = 0; + int i, prio; + + for (prio = PCI_RESET_METHODS_NUM; prio; prio--) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (prio == pdev->reset_methods[i]) { + len += sysfs_emit_at(buf, len, "%s%s", + len ? "," : "", + pci_reset_fn_methods[i].name); + break; + } + } + + if (i == PCI_RESET_METHODS_NUM) + break; + } + + return len; +} + +static ssize_t reset_method_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 reset_methods[PCI_RESET_METHODS_NUM]; + struct pci_dev *pdev = to_pci_dev(dev); + u8 prio = PCI_RESET_METHODS_NUM; + char *name; + int i; + + /* + * Initialize reset_method such that 0xff indicates + * supported but not currently enabled reset methods + * as we only use priority values which are within + * the range of PCI_RESET_FN_METHODS array size + */ + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) + reset_methods[i] = pdev->reset_methods[i] ? 0xff : 0; + + if (sysfs_streq(buf, "")) { + pci_warn(pdev, "All device reset methods disabled by user"); + goto set_reset_methods; + } + + if (sysfs_streq(buf, "default")) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) + reset_methods[i] = reset_methods[i] ? prio-- : 0; + goto set_reset_methods; + } + + while ((name = strsep((char **)&buf, ",")) != NULL) { + if (sysfs_streq(name, "")) + continue; + + name = strim(name); + + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (reset_methods[i] && + sysfs_streq(name, pci_reset_fn_methods[i].name)) { + reset_methods[i] = prio--; + break; + } + } + if (i == PCI_RESET_METHODS_NUM) + return -EINVAL; + } + + if (reset_methods[0] && + reset_methods[0] != PCI_RESET_METHODS_NUM) + pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); + +set_reset_methods: + memcpy(pdev->reset_methods, reset_methods, sizeof(reset_methods)); + return count; +} + +static DEVICE_ATTR_RW(reset_method); + +static struct attribute *pci_dev_reset_method_attrs[] = { + &dev_attr_reset_method.attr, + NULL, +}; + +static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); + + if (!pci_reset_supported(pdev)) + return 0; + + return a->mode; +} + +static const struct attribute_group pci_dev_reset_method_attr_group = { + .attrs = pci_dev_reset_method_attrs, + .is_visible = pci_dev_reset_method_attr_is_visible, +}; + static ssize_t reset_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1491,6 +1595,7 @@ const struct attribute_group *pci_dev_groups[] = { &pci_dev_config_attr_group, &pci_dev_rom_attr_group, &pci_dev_reset_attr_group, + &pci_dev_reset_method_attr_group, &pci_dev_vpd_attr_group, #ifdef CONFIG_DMI &pci_dev_smbios_attr_group, From patchwork Sat May 29 19:25:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288029 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11D4FC47090 for ; Sat, 29 May 2021 19:25:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E964F610CC for ; Sat, 29 May 2021 19:25:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229947AbhE2T1c (ORCPT ); Sat, 29 May 2021 15:27:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229894AbhE2T12 (ORCPT ); Sat, 29 May 2021 15:27:28 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70D6CC061761; Sat, 29 May 2021 12:25:51 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id f3-20020a17090a4a83b02901619627235bso2260791pjh.1; Sat, 29 May 2021 12:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VonPpqeifCpx/rhRuWJbeDZ8TUbllujK6CrQIjhpWII=; b=Vge6YOWL7wF4rp7Ah5iEVuABfZWkEX9Vj1czcDauD6rbyXB2B9A9lAqmezQH+cN9IU IPLVQ4hpQ8T4msKdagDdbTLi9QWpkLzar0jAbCbvY+uDG30mquf1ppRpY+tXh34O7nhU BZtVvbNnyFGUh7ITOrH5+oAl6Of4AqUQInNZSlcJsnU9YJMi/2JcFuFacuvon1bZoyRL yvaaoo4i7grrKmVVVsIY7PEerahOK6XKAcWypEXpiAv8AacxXsXRstWLapyAp3uyDB2F mEINSVdZ3348KXB7g25doXnkoeuGKZStmDidMF7Cuq0YiuYS5yO0Gi6hai0k5zxm0qMm PDBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VonPpqeifCpx/rhRuWJbeDZ8TUbllujK6CrQIjhpWII=; b=OjdJOoOOmTifq5gO1ejngHADQrePVkQupS3bGPSmXV1BzuywCGtkl59Wfieim7uh0B dDd9AipcsM870BuS0DXzn3yGv35TUATzDXb6VbpEYf4EE3pKjD7ILrAee61CjZSxzg/F VUfaaBbvOq8A5Epql7vFeMvTp+Ag8/Ehgq3oD/94md3crXvaDhjvSKzqOqnay1698kUI DYZXNt5X8LFArbZNXx6It+WYwTZaWyghhrGJ7WM+PS82GwmrTHIeXsRNPaMtg6o3Iaml tDr0Npf8NP8FTAfY5DjGmU38tdZO52qEPVE9+sEA1ECe/hPxo8AHewoXpZRfLQtV/gF/ Tckg== X-Gm-Message-State: AOAM5337NeIF6tkuCMxZEKF5rz/jOBz/rkSRhAejJdE3td02tgw76m1U uBB9KPreC2z4DIv+8VZ54/SZiRu56gwgUw== X-Google-Smtp-Source: ABdhPJzWOCtEW8eDeZOfb181fTEjC1J7EUg2hUWokvbKaB2iBxYJ5fe8vjbjmE/fyyob/OKocSaYew== X-Received: by 2002:a17:90a:ea10:: with SMTP id w16mr10533853pjy.46.1622316351067; Sat, 29 May 2021 12:25:51 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:50 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya Subject: [PATCH v5 5/7] PCI: Add support for a function level reset based on _RST method Date: Sun, 30 May 2021 00:55:25 +0530 Message-Id: <20210529192527.2708-6-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The ACPI binding information is available only after calling device_add(). To consider _RST method, move pci_init_reset_methods() to end of pci_device_add() and craete two sysfs entries reset & reset_methond from pci_create_sysfs_dev_files() The default priority of the acpi reset is set to below device-specific and above hardware resets. Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya --- drivers/pci/pci-sysfs.c | 23 ++++++++++++++++++++--- drivers/pci/pci.c | 30 ++++++++++++++++++++++++++++++ drivers/pci/probe.c | 2 +- include/linux/pci.h | 2 +- 4 files changed, 52 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 04b3d6565..b332d7923 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1482,12 +1482,30 @@ static const struct attribute_group pci_dev_reset_attr_group = { .is_visible = pci_dev_reset_attr_is_visible, }; +const struct attribute_group *pci_dev_reset_groups[] = { + &pci_dev_reset_attr_group, + &pci_dev_reset_method_attr_group, + NULL, +}; + int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) { + int retval; + if (!sysfs_initialized) return -EACCES; - return pci_create_resource_files(pdev); + retval = pci_create_resource_files(pdev); + if (retval) + return retval; + + retval = device_add_groups(&pdev->dev, pci_dev_reset_groups); + if (retval) { + pci_remove_resource_files(pdev); + return retval; + } + + return 0; } /** @@ -1501,6 +1519,7 @@ void pci_remove_sysfs_dev_files(struct pci_dev *pdev) if (!sysfs_initialized) return; + device_remove_groups(&pdev->dev, pci_dev_reset_groups); pci_remove_resource_files(pdev); } @@ -1594,8 +1613,6 @@ const struct attribute_group *pci_dev_groups[] = { &pci_dev_group, &pci_dev_config_attr_group, &pci_dev_rom_attr_group, - &pci_dev_reset_attr_group, - &pci_dev_reset_method_attr_group, &pci_dev_vpd_attr_group, #ifdef CONFIG_DMI &pci_dev_smbios_attr_group, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index bbed852d9..4a7019d0b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5115,6 +5115,35 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ +#ifdef CONFIG_ACPI + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + /* Return -ENOTTY if _RST method is not included in the dev context */ + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + /* Return 0 for probe phase indicating that we can reset this device */ + if (probe) + return 0; + + /* Invoke _RST() method to perform a function level reset */ + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "Failed to reset the device\n"); + return -EINVAL; + } + return 0; +#else + return -ENOTTY; +#endif +} + /* * The ordering for functions in pci_reset_fn_methods * is required for reset_methods byte array defined @@ -5122,6 +5151,7 @@ static void pci_dev_restore(struct pci_dev *dev) */ const struct pci_reset_fn_method pci_reset_fn_methods[] = { { &pci_dev_specific_reset, .name = "device_specific" }, + { &pci_dev_acpi_reset, .name = "acpi" }, { &pcie_reset_flr, .name = "flr" }, { &pci_af_flr, .name = "af_flr" }, { &pci_pm_reset, .name = "pm" }, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 90fd4f61f..eeab791a0 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2404,7 +2404,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - pci_init_reset_methods(dev); } /* @@ -2495,6 +2494,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev->match_driver = false; ret = device_add(&dev->dev); WARN_ON(ret < 0); + pci_init_reset_methods(dev); } struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) diff --git a/include/linux/pci.h b/include/linux/pci.h index 6e9bc4f9c..a7f063da2 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,7 +49,7 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) -#define PCI_RESET_METHODS_NUM 5 +#define PCI_RESET_METHODS_NUM 6 /* * The PCI interface treats multi-function devices as independent From patchwork Sat May 29 19:25:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288031 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F76C47091 for ; Sat, 29 May 2021 19:25:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 744CD610FC for ; Sat, 29 May 2021 19:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229926AbhE2T1e (ORCPT ); Sat, 29 May 2021 15:27:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbhE2T1b (ORCPT ); Sat, 29 May 2021 15:27:31 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5539BC061763; Sat, 29 May 2021 12:25:54 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id q15so5151276pgg.12; Sat, 29 May 2021 12:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IWfL/IMqwLqFbs476iJcEczTrUNwgxx26bfBJrumYEY=; b=hrM9B0oQ+o1TsEFqlrsfljdnpCyJ40+Nbn4MTHMvNrobuJRIHIwYgsWEAJxwNMhgE0 5SUdmlDAUPgLyeGx3nr4uwKzgw9pqkmOknGqhLkBHjMr1zAJKKrKoHmpoA9Ajm127O0F nwe+LPNVyRWGd90iv44FB9zYzUzJVyqBl0Nz/lkbEBCfCKFKHbJ5puqPgG09Na+9ggJD gHJh9H+gTDj4EvRXE0WKHFAI+ZXb/lwzYDexd4jwNkU443CVJtjMQElbE7roZmSQWrj6 E+2AEpSdxRI2yfNQpahPBMpQpRp/XCgK6o2x9gYfAry9GNdGghYaiRZah6L1F9P5SUps ybsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IWfL/IMqwLqFbs476iJcEczTrUNwgxx26bfBJrumYEY=; b=aZYyfYhlpaJcSUNo8p3wcQMOf7jprIuQrrDw8rDnjL4kok/gAE1ZQ3pHcnkbI4T32Y 44NZi9IA1PyPZhiU0Xe2eJAwGSfyk4NMe/zj5aaiqXI4VZ9hBvtwmKL54/m8nF8nKjGC o5fFXbnePu8NknAmZId7Cyf1mgO9rfnf4l5XFg8TOMqD+HO5ODqS2LEJUmC5geYhUQ34 22oHY35CIQbIYx5GkW7usYLO4kXtYEIaHvB9ug8AQKJS4Q+VuGsG0s2WWCBiNjpdMDJR jHWK+wQP6ex6ClymCwoJaVs0eKtonPgTzd2BjH47k0+hRyB0sE8EWgmmtfeEezTJQsp8 eDow== X-Gm-Message-State: AOAM532nd3/96Bg5MeclOsSfp+/QegStkea+CMIcDNNlrkfKLEwdEKeR 8GUwz1ZXQILN8l4U48PfZ3A= X-Google-Smtp-Source: ABdhPJyh+6aY+wJjlfuIfMX8qrwCugaBvQho86c/C3x2Em2HMjcoS0XQLIqq99UMwGi0gwexELrT2g== X-Received: by 2002:a63:5052:: with SMTP id q18mr15042066pgl.349.1622316353977; Sat, 29 May 2021 12:25:53 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:53 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya Subject: [PATCH v5 6/7] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Date: Sun, 30 May 2021 00:55:26 +0530 Message-Id: <20210529192527.2708-7-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni On select platforms, some Nvidia GPU devices do not work with SBR. Triggering SBR would leave the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to fix the issue. This issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya --- drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e86cf4a3b..45a8c3caa 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3546,6 +3546,18 @@ static void quirk_no_bus_reset(struct pci_dev *dev) dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + quirk_no_bus_reset(dev); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + /* * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. * The device will throw a Link Down error on AER-capable systems and From patchwork Sat May 29 19:25:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12288033 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADC1CC47082 for ; Sat, 29 May 2021 19:26:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 898646113B for ; Sat, 29 May 2021 19:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbhE2T1m (ORCPT ); Sat, 29 May 2021 15:27:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbhE2T1f (ORCPT ); Sat, 29 May 2021 15:27:35 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FA8EC061760; Sat, 29 May 2021 12:25:58 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id r1so5155898pgk.8; Sat, 29 May 2021 12:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TnDvHf7F4Ba7n/bfc1FIRIxHHfCMXX7lB+XnUQdNfig=; b=FIzpo4wrxs0mF2VbeZmqZxidABzrUXgxRuiNe694Vx2XLNGfEhyeDM4QHbCT+A+7f4 FMzh9z4LIg13P1641aJ/ZsnM1Epsy5cWOp+dMXYHdQBFOiOP86MaXbt87vg5Sn8yY6lh s6F8+QCFNfqH9+dxXfT3exIpWakpRUqKwWFZE5udXgfPOgdnHYZaogJvdyJSRJj9BOV+ 7qGOJnj3MUYQqATZl+LYC4AnwsU7adqBp874/4gEWbREB5sDR0eJ1Dskm64XKoZCw9+Y 0MohJqwlaX8wLTGqiveNI/trCb5MKMfJSocw3UQ84xJQbw+chmhWRg5W64B4gjqZp/we pe2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TnDvHf7F4Ba7n/bfc1FIRIxHHfCMXX7lB+XnUQdNfig=; b=lS4WEbjCC6r1dCeoAnm3ongl3YDHtACzRx9Lf6sBGKWU4NoXBTDtxTiBBZrPIIRQ9p xG8Xc6fADho9A2X58sNIDgDSmLQ+nx3iQ7Z7mgMgMBAbRiGyuR1BbRO9478jkSpGnjpA MGuHlCa/uIg8z8piSgupOWU7t5r5T/hqT4b62SHp0sdg4a3cEgm6GHkStxzcU5SN8SPk wolpMaX67mCTfvtywnz881R7BIHd9ysKPy9y2OusKIi3oV8Ss8KuT+muFWcngb0PGyEo +yNignxQfr9U8CTQbQODZLdhToL5rIlhVUj1BbhEQLJMwcMgwKdM123FAmpkMvaycb4w Rtjw== X-Gm-Message-State: AOAM5308b9CiPHq4tJIxLOnJHf6RPqc4R9goPOjgu2n7MdEPJi2rJsSo /BViqQUAb1HWZ7QPx5doTlG0rIBHc+6Icw== X-Google-Smtp-Source: ABdhPJxAxHZO0Tq09rAIFbJ0YQXVmwWkhrp5Cu/maG5o0tHx7+QmtMftaFH7pyFu3sUUQXTfoI/zpA== X-Received: by 2002:a63:e709:: with SMTP id b9mr15217962pgi.18.1622316357419; Sat, 29 May 2021 12:25:57 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.172]) by smtp.googlemail.com with ESMTPSA id ge5sm7286754pjb.45.2021.05.29.12.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 12:25:57 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v5 7/7] PCI: Change the type of probe argument in reset functions Date: Sun, 30 May 2021 00:55:27 +0530 Message-Id: <20210529192527.2708-8-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210529192527.2708-1-ameynarkhede03@gmail.com> References: <20210529192527.2708-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new enum pci_reset_mode_t to make the context of probe argument in reset functions clear and the code easier to read. Change the type of probe argument in functions which implement reset methods from int to pci_reset_mode_t to make the intent clear. Add a new line in return statement of pci_reset_bus_function. Suggested-by: Alex Williamson Suggested-by: Krzysztof Wilczyński Signed-off-by: Amey Narkhede Tested-by: Shanker Donthineni --- drivers/crypto/cavium/nitrox/nitrox_main.c | 2 +- .../ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/hotplug/pciehp.h | 2 +- drivers/pci/hotplug/pciehp_hpc.c | 4 +- drivers/pci/pci.c | 94 ++++++++++++------- drivers/pci/pci.h | 8 +- drivers/pci/pcie/aer.c | 2 +- drivers/pci/quirks.c | 37 ++++---- include/linux/pci.h | 8 +- include/linux/pci_hotplug.h | 2 +- 10 files changed, 98 insertions(+), 63 deletions(-) -- 2.31.1 diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index 15d6c8452..f97fa8e99 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,7 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - pcie_reset_flr(pdev, 0); + pcie_reset_flr(pdev, PCI_RESET_DO_RESET); pci_restore_state(pdev); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 336d149ee..6e666be69 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (!pcie_reset_flr(oct->pci_dev, 1)) + if (!pcie_reset_flr(oct->pci_dev, PCI_RESET_PROBE)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 4fd200d8b..87da03adc 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -181,7 +181,7 @@ void pciehp_release_ctrl(struct controller *ctrl); int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot); int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot); -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe); +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode); int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status); int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status); int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index fb3840e22..24b3c8787 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -834,14 +834,14 @@ void pcie_disable_interrupt(struct controller *ctrl) * momentarily, if we see that they could interfere. Also, clear any spurious * events after. */ -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode) { struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; int rc; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; down_write(&ctrl->reset_lock); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4a7019d0b..f2ecdfcf9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4650,14 +4650,17 @@ EXPORT_SYMBOL_GPL(pcie_flr); /** * pcie_reset_flr - initiate a PCIe function level reset * @dev: device to reset - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * Initiate a function level reset on @dev. */ -int pcie_reset_flr(struct pci_dev *dev, int probe) +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode) { u32 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return -ENOTTY; @@ -4665,18 +4668,21 @@ int pcie_reset_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_EXP_DEVCAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pcie_flr(dev); } EXPORT_SYMBOL_GPL(pcie_reset_flr); -static int pci_af_flr(struct pci_dev *dev, int probe) +static int pci_af_flr(struct pci_dev *dev, pci_reset_mode_t mode) { int pos; u8 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + pos = pci_find_capability(dev, PCI_CAP_ID_AF); if (!pos) return -ENOTTY; @@ -4688,7 +4694,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -4719,7 +4725,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) /** * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. * @dev: Device to reset. - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is * unset, it will be reinitialized internally when going from PCI_D3hot to @@ -4731,10 +4737,13 @@ static int pci_af_flr(struct pci_dev *dev, int probe) * by default (i.e. unless the @dev's d3hot_delay field has a different value). * Moreover, only devices in D0 can be reset by this function. */ -static int pci_pm_reset(struct pci_dev *dev, int probe) +static int pci_pm_reset(struct pci_dev *dev, pci_reset_mode_t mode) { u16 csr; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4742,7 +4751,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) if (csr & PCI_PM_CTRL_NO_SOFT_RESET) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (dev->current_state != PCI_D0) @@ -4991,10 +5000,13 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); -static int pci_parent_bus_reset(struct pci_dev *dev, int probe) +static int pci_parent_bus_reset(struct pci_dev *dev, pci_reset_mode_t mode) { struct pci_dev *pdev; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; @@ -5003,44 +5015,47 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe) if (pdev != dev) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pci_bridge_secondary_bus_reset(dev->bus->self); } -static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) +static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, pci_reset_mode_t mode) { int rc = -ENOTTY; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!hotplug || !try_module_get(hotplug->owner)) return rc; if (hotplug->ops->reset_slot) - rc = hotplug->ops->reset_slot(hotplug, probe); + rc = hotplug->ops->reset_slot(hotplug, mode); module_put(hotplug->owner); return rc; } -static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) +static int pci_dev_reset_slot_function(struct pci_dev *dev, pci_reset_mode_t mode) { if (dev->multifunction || dev->subordinate || !dev->slot || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; - return pci_reset_hotplug_slot(dev->slot->hotplug, probe); + return pci_reset_hotplug_slot(dev->slot->hotplug, mode); } -static int pci_reset_bus_function(struct pci_dev *dev, int probe) +static int pci_reset_bus_function(struct pci_dev *dev, pci_reset_mode_t mode) { int rc; - rc = pci_dev_reset_slot_function(dev, probe); + rc = pci_dev_reset_slot_function(dev, mode); if (rc != -ENOTTY) return rc; - return pci_parent_bus_reset(dev, probe); + return pci_parent_bus_reset(dev, mode); } static void pci_dev_lock(struct pci_dev *dev) @@ -5118,19 +5133,22 @@ static void pci_dev_restore(struct pci_dev *dev) /** * pci_dev_acpi_reset - do a function level reset using _RST method * @dev: device to reset - * @probe: check if _RST method is included in the acpi_device context. + * @mode: check if _RST method is included in the acpi_device context. */ -static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +static int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { #ifdef CONFIG_ACPI acpi_handle handle = ACPI_HANDLE(&dev->dev); + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + /* Return -ENOTTY if _RST method is not included in the dev context */ if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; /* Return 0 for probe phase indicating that we can reset this device */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* Invoke _RST() method to perform a function level reset */ @@ -5196,7 +5214,7 @@ int __pci_reset_function_locked(struct pci_dev *dev) * other error, we're also finished: this indicates that further * reset mechanisms might be broken on the device. */ - rc = pci_reset_fn_methods[i].reset_fn(dev, 0); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_DO_RESET); if (rc != -ENOTTY) return rc; break; @@ -5232,7 +5250,7 @@ void pci_init_reset_methods(struct pci_dev *dev) might_sleep(); for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { - rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_PROBE); if (!rc) reset_methods[i] = prio--; else if (rc != -ENOTTY) @@ -5548,21 +5566,24 @@ static void pci_slot_restore_locked(struct pci_slot *slot) } } -static int pci_slot_reset(struct pci_slot *slot, int probe) +static int pci_slot_reset(struct pci_slot *slot, pci_reset_mode_t mode) { int rc; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!slot || !pci_slot_resetable(slot)) return -ENOTTY; - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_lock(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, probe); + rc = pci_reset_hotplug_slot(slot->hotplug, mode); - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_unlock(slot); return rc; @@ -5576,7 +5597,7 @@ static int pci_slot_reset(struct pci_slot *slot, int probe) */ int pci_probe_reset_slot(struct pci_slot *slot) { - return pci_slot_reset(slot, 1); + return pci_slot_reset(slot, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_slot); @@ -5599,14 +5620,14 @@ static int __pci_reset_slot(struct pci_slot *slot) { int rc; - rc = pci_slot_reset(slot, 1); + rc = pci_slot_reset(slot, PCI_RESET_PROBE); if (rc) return rc; if (pci_slot_trylock(slot)) { pci_slot_save_and_disable_locked(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, 0); + rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); pci_slot_restore_locked(slot); pci_slot_unlock(slot); } else @@ -5615,14 +5636,17 @@ static int __pci_reset_slot(struct pci_slot *slot) return rc; } -static int pci_bus_reset(struct pci_bus *bus, int probe) +static int pci_bus_reset(struct pci_bus *bus, pci_reset_mode_t mode) { int ret; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!bus->self || !pci_bus_resetable(bus)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; pci_bus_lock(bus); @@ -5661,14 +5685,14 @@ int pci_bus_error_reset(struct pci_dev *bridge) goto bus_reset; list_for_each_entry(slot, &bus->slots, list) - if (pci_slot_reset(slot, 0)) + if (pci_slot_reset(slot, PCI_RESET_DO_RESET)) goto bus_reset; mutex_unlock(&pci_slot_mutex); return 0; bus_reset: mutex_unlock(&pci_slot_mutex); - return pci_bus_reset(bridge->subordinate, 0); + return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); } /** @@ -5679,7 +5703,7 @@ int pci_bus_error_reset(struct pci_dev *bridge) */ int pci_probe_reset_bus(struct pci_bus *bus) { - return pci_bus_reset(bus, 1); + return pci_bus_reset(bus, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_bus); @@ -5693,7 +5717,7 @@ static int __pci_reset_bus(struct pci_bus *bus) { int rc; - rc = pci_bus_reset(bus, 1); + rc = pci_bus_reset(bus, PCI_RESET_PROBE); if (rc) return rc; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13ec6bd6f..67fb10e50 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -603,19 +603,19 @@ static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) struct pci_dev_reset_methods { u16 vendor; u16 device; - int (*reset)(struct pci_dev *dev, int probe); + int (*reset)(struct pci_dev *dev, pci_reset_mode_t mode); }; struct pci_reset_fn_method { - int (*reset_fn)(struct pci_dev *pdev, int probe); + int (*reset_fn)(struct pci_dev *pdev, pci_reset_mode_t mode); char *name; }; extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS -int pci_dev_specific_reset(struct pci_dev *dev, int probe); +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 98077595a..cfa7a1775 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,7 +1405,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - rc = pcie_reset_flr(dev, 0); + rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); if (!rc) pci_info(dev, "has been reset\n"); else diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 45a8c3caa..60fd101ac 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3681,7 +3681,7 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, * reset a single function if other methods (e.g. FLR, PM D0->D3) are * not available. */ -static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) +static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, pci_reset_mode_t mode) { /* * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf @@ -3691,7 +3691,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) * Thus we must call pcie_flr() directly without first checking if it is * supported. */ - if (!probe) + if (mode == PCI_RESET_DO_RESET) pcie_flr(dev); return 0; } @@ -3703,13 +3703,13 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) #define NSDE_PWR_STATE 0xd0100 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ -static int reset_ivb_igd(struct pci_dev *dev, int probe) +static int reset_ivb_igd(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *mmio_base; unsigned long timeout; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; mmio_base = pci_iomap(dev, 0, 0); @@ -3746,7 +3746,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe) } /* Device-specific reset method for Chelsio T4-based adapters */ -static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) +static int reset_chelsio_generic_dev(struct pci_dev *dev, pci_reset_mode_t mode) { u16 old_command; u16 msix_flags; @@ -3762,7 +3762,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * If this is the "probe" phase, return 0 indicating that we can * reset this device. */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -3824,17 +3824,17 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * Chapter 3: NVMe control registers * Chapter 7.3: Reset behavior */ -static int nvme_disable_and_flr(struct pci_dev *dev, int probe) +static int nvme_disable_and_flr(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *bar; u16 cmd; u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); @@ -3898,11 +3898,13 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) * device too soon after FLR. A 250ms delay after FLR has heuristically * proven to produce reliably working results for device assignment cases. */ -static int delay_250ms_after_flr(struct pci_dev *dev, int probe) +static int delay_250ms_after_flr(struct pci_dev *dev, pci_reset_mode_t mode) { - int ret = pcie_reset_flr(dev, probe); + int ret; + + ret = pcie_reset_flr(dev, mode); - if (probe) + if (ret || mode == PCI_RESET_PROBE) return ret; msleep(250); @@ -3918,13 +3920,13 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ -static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe) +static int reset_hinic_vf_dev(struct pci_dev *pdev, pci_reset_mode_t mode) { unsigned long timeout; void __iomem *bar; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(pdev, 0, 0); @@ -3995,16 +3997,19 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { * because when a host assigns a device to a guest VM, the host may need * to reset the device but probably doesn't have a driver for it. */ -int pci_dev_specific_reset(struct pci_dev *dev, int probe) +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { const struct pci_dev_reset_methods *i; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + for (i = pci_dev_reset_methods; i->reset; i++) { if ((i->vendor == dev->vendor || i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return i->reset(dev, mode); } return -ENOTTY; diff --git a/include/linux/pci.h b/include/linux/pci.h index a7f063da2..c46df52e6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,6 +51,12 @@ #define PCI_RESET_METHODS_NUM 6 +typedef enum pci_reset_mode { + PCI_RESET_DO_RESET, + PCI_RESET_PROBE, + PCI_RESET_MODE_MAX, +} pci_reset_mode_t; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -1230,7 +1236,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -int pcie_reset_flr(struct pci_dev *dev, int probe); +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode); int pcie_flr(struct pci_dev *dev); bool pci_reset_supported(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index b482e42d7..9e8da46e7 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -44,7 +44,7 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*reset_slot) (struct hotplug_slot *slot, int probe); + int (*reset_slot) (struct hotplug_slot *slot, pci_reset_mode_t mode); }; /**