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Mon, 31 May 2021 02:51:54 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] dt-bindings: media: imx8q: add imx video codec bindings Date: Mon, 31 May 2021 10:51:09 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: +se/4jMQypB4kzZRhQap/DSl4xLrqHCX6SC01EnrBvX2pCXDRJEZQVJYW1XIDfP6Dj2+AvcK4aq4joNMf7bQALzjkCDNNtKfVSK1JG+0/g8WPArrcIsGTS+TVZdPQt/Ntotqvs8r19KQkGxY6PV8KKo0NsfnvxZtuZbYsxZxI66vMAljVeo311XYrTvf0NLA9GsIVBnCFEU7hD2HdnOeOpVWXj/Zuqdd8IMkhb/edxIonGJiUa58y+TJvpgDawwJg9ULasf+RnFz15rmonIxE650oeEGugjGZfZ2ATgKgGxs3ZkrMySr9ylZIpAjXcCQo5lSdnkwrDZ/zp2nat7lAOC7cNFocPc4PUQSkZR9Ojhd5GBQd7utAv4axoD6PVFuw6dZe2ETL4IOAhalji1BUDWcWlM/LI6pMX0zT2bD3GH5uBvwNkQ4BWYHk+Ilt8dVuGdHdrqp7gcsGo9NKrcERXwYlTguEue1mouVA79YVqFBbAiaeAwY1+QojP73gdAR+ZO2Sid6oIm+sQG7ciBKz/WMoOtk4SfPF32gizp29HtppNl5wy/GY9hRY202oMVLS1xF+Wha+GxkqlX03lrnsfhf705FY6X61wLnI9Ls5fL2FU/tRSCRvEbPXwGCqEHcdmOvKBlXZBp9Jy01nHdOw4WG7khHovR4Q/Cbt/sP30qNLR2T0XhxQc/2dE9peA8Ah/XB6cszpi//7L29BzEEyu95oLRkSVdmDFlMIOS9yI/yhEc0CQC3CpU1TKoExiIOtiLk9tTvQSGkW51Ep5JVMh21qVCi114gl5TKHiksUmHonB/XwKR58GUL0AGdXIeAZOiP+wJv1Mx0kP3KS+/ocFyzOJhsmlbU+Yf5IFnwN+rg8u/QbWAMXTXsfBn4/pFnaxGdFmHtqZ7MD+AfCR4acrX21kvZuco2txdht2b/KzCdAEx6rYETYr19Qv3VS1TtZJTJ1WS0VxHuWMYnDq4dCYT9UF3JMSkSVd5/fBOTMAGmgAFZTBabofIlxDiVuC3OUCaOzbWyfbsFt+aEyVnie3wUsjwIb2DSRydfMOIdZjJVuZG1tsb2H7bT3YcptE3yxdbOfP0h7v38Z6e8olWaitOU8Do5Zo+xyUysDwLSboDn0/J/WejGE/hu0UcXwdjtob/N8Dq17JIfMTHAXDn79UqcfBgIVLsIJP8CduXWD8mJ2aVovfdrzfKyHtqck21Aqhiw+CkIeWw+6tWQ6rJoR+UqOWaX4Vg5TZ0Ac+zp2HEIpgDzAcZhIFMHZGNU9srCbHPdT2VgTFYqh98sHiVMXdZ0ByZXn+I+1LBSwQhbwtwI4kUL2DuVFw8sQ5S4fj7X X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 38b97f81-2809-4008-1b9d-08d923df0c5f X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 02:51:54.4263 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T83xKe9HOlf+VwkIEYLGuYmgV5kVVe0i1HCEHQiE2wQ7zhNVNpAwsGJcvFPimFH3tw2P1OFkWKlOegTGu50j2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for IMX8Q Video Processing Unit IP Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../bindings/media/nxp,imx8q-vpu.yaml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file mode 100644 index 000000000000..97e428dbfdbe --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - ming_qian + - Shijie Qin + +description: |- + The Amphion MXC video encode and decode accelerators present on NXP i.MX8Q SoCs. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + items: + - enum: + - nxp,imx8qxp-vpu + - nxp,imx8qm-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + memory-region: + description: + Phandle to a node describing reserved memory used by VPU. + (see bindings/reserved-memory/reserved-memory.txt) + + vpu_lpcg: + description: + This is vpu Low-Power Clock Gate (LPCG) module. + + mu_m0: + description: + Each vpu core correspond a MU node, which used for communication between + driver and firmware. Implement via mailbox on driver. + + vpu_core: + type: object + additionalProperties: false + description: + Each core correspond a decoder or encoder, need to configure them + separately. + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + maxItems: 3 + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + + boot-region: + description: + Phandle to a node describing reserved memory used by firmware + loading. + + rpc-region: + description: + Phandle to a node describing reserved memory used by RPC shared + memory between firmware and driver. + + print-offset: + description: + The memory offset from RPC address, used by reserve firmware log. + + id: + description: Index of vpu core. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - boot-region + - rpc-region + - print-offset + - id + + +required: + - compatible + - reg + - power-domains + - memory-region + - vpu_lpcg + - mu_m0 + - vpu_core + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu-bus@2c000000 { + compatible = "nxp,imx8qm-vpu", "simple-bus"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + memory-region = <&vpu_reserved>; + + vpu_lpcg: clock-controller@2c000000 { + compatible = "fsl,imx8qxp-lpcg-vpu"; + reg = <0x2c000000 0x2000000>; + #clock-cells = <1>; + status = "disabled"; + }; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_decoder@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + print-offset = <0x180000>; + id = <0>; + }; + + vpu_core1: vpu_encoder@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + boot-region = <&encoder1_boot>; + rpc-region = <&encoder1_rpc>; + print-offset = <0x80000>; + id = <1>; + }; + + vpu_core2: vpu_encoder@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + boot-region = <&encoder2_boot>; + rpc-region = <&encoder2_rpc>; + id = <2>; + }; + }; + +... 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Mon, 31 May 2021 02:52:03 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/5] media: v4l: add some definition of v4l2 colorspace/xfer_func/ycbcr_encoding Date: Mon, 31 May 2021 10:51:10 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Tnv0tAb8CsjqOH0m1Wh9Ef426uLdPVBLj7nkzwfXI5GUoq8vBEK8W3fJ8QgOXgwfCDzu9y1pVXia8OOTwhSEoOMvZQ2/CMgssveWqq6Y6U1I1VBmRfTaDaLyoPFIcir44VZ9PS/1Y7zyzVK5heoce7WitkDpR7mIgD1AI05tG14Csd5mTJ67c4y5yy++74aVKA0cfquoujlc35Du7DSF4jDMIxAy3cTdHwgCUJV3/0itF1AmkdveglGiIcbBehyDLcEycgS8RtGDbG16JVf60mZmz+zB1cM1o+2ynjKR1Ycvv8hiWiu/BBcEoR/M1eh1wj1Ckoww8VwcNnpTo2lQPvIE61kePnyfz91P+Vyyz3IqpolPxiin89uRiDjsE6jVTLHiiB2E0EpYngpcMPzFqTNubNfLOX3+X9BhT2Toie9WAblT3sXEpnkXW+eer1mchyQViVtGqODChgGHGmmBDEPi4RMECkL6HDxh4ggnF2+vuebf4ZJJaMe0KyuElWK90AidFHOSvSAHsIGzbAuFS/tHgGMJdyCX8XZEnO+Qg7nhqFx08McZlXa7Y8FuJRhHfO+V8cNYzium7WOiL+9GmGS9Cda+SLHQl0/oviVtpCW4jl1HbingsI8C5qf8ydUBSAKWwaZ2Jv82vSLJa+7GSAPoFo6IkbqiF67LKmyRsjV7ecZhqnj6bbdwlyrc3wLVBeMgFQbPRU4dM3l0YCHbCbJzt5mu07vaIFPgZg7clvjTulEbpSLoIq7/3lxUJKzdsjEQYj7bG7ymdiaVLTRxEcpRtMzf8WFIxwOo1032GzAZykJ09nMLSOm1CYXYEHLw/JzEUB1PAKo4qRhYpMdiexGr9Gwm/BRvSTYOPtld/hAWVWp6eRhsaac/KaRmexQ797qpWTD6MIZucA3alKvYWVF2whmJTAODxIaVWuhUK88f5BqFKuJ0f5fYakwT06DUXy3c8ahOYai7OWFt33Gn9wwZoNqoPuSnNTN0iuPucjVpldPgyw3zi2yZGvB4U2fOEQ3Ia/UY8jk1eD0Ruh/hy+b+J2FFWJw2rdOVpDdAKZdFp55XIl+1ZDF39fA+dEh5FO+TjHHLEEv96tAlVrJjILtZv/Jnu3LHecyK4mUogZjd3+jQGyxNlPpC7nQHGvE1z2b+YnwUrioqJ1/UP/Z82ThuffN3JallwId07j6buXSgtZo6ERFnCOT6bhP2Qb1qpOiIoTwM0V/eHf9aCaCxotxzombUiszbOAHUMfMqzA3F6NZoXScbSIQaPrgRppdJ91sQU92gJHsBAH41V6MlS9bXM3brC1giUxwk1QtXUKWXAgTWAKLDiTcWU5+LI9kQ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b496c33d-2e8e-4119-5981-08d923df11ed X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 02:52:03.7301 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: me+5TxSEP6BycPSD0sM3EBQUu+mqN//OXD65Rw9qTHnnDS/LnSvOsiHnYKwA5Vhn0YjClnUdpZNuk8/hlE+eSA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some definition of colorspace/xfer_func/ycbcr_encoding are defined in ISO, but missed in V4L2, so add some definition according VPU driver's requirement Signed-off-by: Ming Qian Reviewed-by: Shijie Qin --- include/uapi/linux/videodev2.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 534eaa4d39bc..545f2c329bc9 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -247,6 +247,12 @@ enum v4l2_colorspace { /* DCI-P3 colorspace, used by cinema projectors */ V4L2_COLORSPACE_DCI_P3 = 12, + + /* Generic film (colour filters using Illuminant C) */ + V4L2_COLORSPACE_GENERIC_FILM = 13, + + /* SMPTE ST 428-1 */ + V4L2_COLORSPACE_ST428 = 14, }; /* @@ -276,6 +282,20 @@ enum v4l2_xfer_func { * V4L2_COLORSPACE_RAW: V4L2_XFER_FUNC_NONE * * V4L2_COLORSPACE_DCI_P3: V4L2_XFER_FUNC_DCI_P3 + * + * V4L2_XFER_FUNC_LINEAR: Linear transfer characteristics + * + * V4L2_XFER_FUNC_GAMMA22: Assumed display gamma 2.2 + * + * V4L2_XFER_FUNC_GAMMA28: Assumed display gamma 2.8 + * + * V4L2_XFER_FUNC_HLG: STD-B67, Rec. ITU-R BT.2100-2 hybrid-log-gamma + * + * V4L2_XFER_FUNC_XVYCC: IEC 61966-2-4 + * + * V4L2_XFER_FUNC_BT1361: Rec. ITU-R BT.1361-0 extended colour gamut + * + * V4L2_XFER_FUNC_ST428: SMPTE ST 428-1 */ V4L2_XFER_FUNC_DEFAULT = 0, V4L2_XFER_FUNC_709 = 1, @@ -285,6 +305,13 @@ enum v4l2_xfer_func { V4L2_XFER_FUNC_NONE = 5, V4L2_XFER_FUNC_DCI_P3 = 6, V4L2_XFER_FUNC_SMPTE2084 = 7, + V4L2_XFER_FUNC_LINEAR = 8, + V4L2_XFER_FUNC_GAMMA22 = 9, + V4L2_XFER_FUNC_GAMMA28 = 10, + V4L2_XFER_FUNC_HLG = 11, + V4L2_XFER_FUNC_XVYCC = 12, + V4L2_XFER_FUNC_BT1361 = 13, + V4L2_XFER_FUNC_ST428 = 14, }; /* @@ -345,6 +372,9 @@ enum v4l2_ycbcr_encoding { /* SMPTE 240M -- Obsolete HDTV */ V4L2_YCBCR_ENC_SMPTE240M = 8, + + /* KR=0.30, KB=0.11 or equivalent */ + V4L2_YCBCR_ENC_BT470_6M = 9, }; /* From patchwork Mon May 31 02:51:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 12288577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC75C47092 for ; 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X-MS-Exchange-AntiSpam-MessageData: ac5OvsklTmYki63RpMDiaNe/Fgu874wlU0UtcCrBXG57n3gMoszlc4joHMAAA5cE6qvb8D9onP8U2eRE7PJUL+buZxPa6q8tJjkxlV/8BspmzqDq/kMuWr7dtqMcMmpFR1hIqD1syfzSdFo77L9yzEtzxH6GY4euH+TOUslwPhQSchvqtriuDnkYA4CV4bouIkqVPFwyxAouG6ZdHUK6u0PAMl6XZE0HDicR8T7L6mEvJJsEAe5BaAGXDI9US/a4iaV5Kdh9dReQYS5kjdtFlgm8MiY73wKSF7KKiFW+AWg9vBAJoJZRlxfDubRkYq+2ZGIJ4aUpGJa92TukHXLJuYLlhlGgdYx7h05FyeLsHuvVSZi+svwoAHHrd0MLtxA0BV+/+pK0P6AWKabO1gkhrsBhd5Uic1uTNYlOtJ6MDcmVmVC6IPKwVaPMx1PwKgBdbCbbCIbjhholkKfeo+WNSYG1gQhtHVZq0gJMm+Szl7HaGmv244QgmGKlQf4JwVPKQw5ejkoznxwQJr7PVkP7SD1l5i/Rtsv0JhSmdYZetvwQSMg5F7KCaOXQmapnEGWOQDGh2GUorU3ZkL6J4rMG8zCjKz0PqZ9aHEK0SiGkHXXS78Se2wivKGSL8sE+tF1eWnnwT3Vu30lFNgnQU5ew+Ceah901S24YZB6KRbljeTZ5VgRrKWylDuorijto8Kx7ui7T3JvgSqekTEn7BL9NP5IKf2OLIK9ft+GPc9z7mE6Lb22pk6cr0BhQU0D36a3b69qtmNqWgLui5N4L3QqsIT8bdIpKb6+OjMb4SI018BDs5lPM+5q0cAzVzki2gTqdcXvl4Ps7eVZ3kwuiijqqsHZNMBoBOaNM8pub7OScJdyhcQrfeodUFo59A2+TkSYqDPoaigdb6ftUtymrYdBZ45wtzJpU+V51abvqobK6MKlOC1nY3NTSamF1jHJFRR2tBMsGJd5PhoQin2roeT6P4ipB9z4uHqu1wR3uDby/GLaSQhxsZkLVWsy3bjQF7i6vsB8CJjQu3LA2Zyg/FmuPXyCjJzEiE1p+ko99jtoZvj911yFaMKCpB7350J5J/lkgjvIgUHexFVm3mufd862xr7CuXfetVoBO+Zmb1cQWcLsRImbMf6NdLLvUyo0N3ufK2KIepstrcjBuuwi8Y9VPDiazTDKoLVcdY17sxE/8CkEgQJhaUPKolcYjDtU7Qd6Fo6zhHUXp9tLj24jh7+vWXMdZB1jrpsEbTRc+1/pCgiylzZcHrBsjVnVlcN6sxslrMHesUzSs4FcJzyfjCo3GBbuYIGFF79hTrCLYuWLkhts4XFrdSmwojT8/0Dqx0iR5 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14620825-b3de-45c0-5ead-08d923df1ad2 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 02:52:18.6588 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PO+n8XCSIrZXtOtAWa+8L8yW09t9VY41F1xHeV8DInBYnrwr1y397Zr/a+Zaqk2pNmXDxtfdvDvikpyw8bXMew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add the Video Processing Unit node for IMX8Q SoC. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 76 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 22 ++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 27 +++++++ 3 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..6e9437f11817 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu-bus@2c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu_decoder@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + id = <0>; + status = "disabled"; + }; + vpu_core1: vpu_encoder@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + id = <1>; + status = "disabled"; + }; + vpu_core2: vpu_encoder@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + id = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 46437d3c7a04..d79eaa0a28ac 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -196,6 +196,28 @@ &usdhc2 { status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu", "simple-bus"; + memory-region = <&vpu_reserved>; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + print-offset = <0x180000>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + print-offset = <0x80000>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index e46faac1fe71..74900686ec37 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -133,10 +133,34 @@ reserved-memory { #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x100000>; + no-map; + }; dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + vpu_reserved: vpu_reserved@94400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x94400000 0 0x800000>; + }; }; pmu { @@ -629,4 +653,7 @@ map0 { }; }; }; + + /* sorted in register address */ + #include "imx8-ss-vpu.dtsi" }; From patchwork Mon May 31 02:51:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 12288579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1239C47095 for ; Mon, 31 May 2021 02:52:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CD0161222 for ; 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dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) by AM5PR0401MB2546.eurprd04.prod.outlook.com (2603:10a6:203:38::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.24; Mon, 31 May 2021 02:52:25 +0000 Received: from AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::c5c1:3625:26e4:4276]) by AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::c5c1:3625:26e4:4276%5]) with mapi id 15.20.4173.030; Mon, 31 May 2021 02:52:25 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Mon, 31 May 2021 10:51:13 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: p0QkDQ3iMQcsaCTxphT5MWvSoPO6CUgJ2M8VV5OANWu1C9JMROV5KsviEpfaUF8/0fMlEpy/Vkg1q752vwsc7KtzvhGnULqpbkHoYnMPeHxtkRGCeeyeDQiEghvUDmohSXB6MEHG6MmkCTnT6T0ORbtHGuedB2Bltr90ZrPtZM22SBznxh+ydmU3MzkkyXuyxqHnKrfyHc15dYXJAoD6CQOy1D/5umAI/Pf8ANjA78Wu39BfqfBlkjISozAO2GDZGEeF8pGt6oClHkAZwNtS4P0goVVhTe5qhrkPYYbHma0QzXF1cl2uNbJOBM7fPMOs0Dl/FbYq/Ucz4FWh9GkbqweaMg/JWRTFbZU4w7AU6/6ZPUcURuOjlHzyyiJxtwEhlfXAIgqB3CLjoidoMmo43kqi2EGV1jUEb+ZWjn4u57OiVXhtvzUE5iawDlqKX07o06S0wsLwa7XZssS4qsEMlZVHmVaE7pAukqYbU9KMVLl0hTcEJ8SBr1RgQbjmXpjtYgnPTyYWEHvRZK2WsEG2NZ187EVV/B73gG6NN/PhkYAmx8ZWRXlrz/osCVDdGpYhTOr4damRlDIaucq9OKcSpY4hWEqg+HA01OxVS2C3VZdLuswg9ENVnbJaeIqAX2gyqAg6F9sH2Sm1hncZDcmF5uZ0dcL0jpjQ8e10dRDgdAmTDniWSmsNsGeFcrug1C2hrAjwbMTccoiA2WfkNPuUMb4o/5vi4e8uR/WPLCxhNRevlsubYv+yv46TxdyabxVii0bWCn7zOGV6zoPQU0TT64ILxLVl30Gt5K7oJth/LiS678SIF8FzQQHW0Esg0HP9tqfMsTPEQ/oXLBrTTh4U/yGjr1uEpot70goIr5WA+vbWr4dQsY5EeYXBt8wQ0wx4XfNiI3W85IOeN25oyLKm0O3OQTA1a6XQTXTRUooiQ15X6pAFs5rTh21ZLbqrybS2piZRFOPNnxn1+HdV4Oyu5LOcX0D45uw3j5/l/StOcpkXnXDBQ/NaUCVfsQ7im8En3LIicGXw+T2yC2d25YMKoSCcsvCS502XtyBU78ZAki3WepoTrLpYTtNRf02z16E9oS/gMX7hzF7xv4zUAh++xxyGq94Sds2mPWTgXHMAYlcBuBpbJvdOmrTM/ZLigDn1AQhaZ6yXBMYWyCY1H2aNrdK9jXpSmNgbvzG2ztxMLKkK/0DdidzHLd21nQIn2E+GMwsUlGmfKzmoC88V1hhkDgoWuUAnnLmVi8ECWM71/Lyt/jFJ9jFZ1y3wHuXQ5VVbKmCv7jkT6nyVpIpOZl8q08rY1+TAhrlD1u3ofJziBCFPvBMAODkRLkkPFYrptvnt X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19f09893-d8bf-48d8-a612-08d923df1eca X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 02:52:25.3710 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 34VQLRozFgvRXiQSijb48lP/W5gPFBYD/tfFNBdHc3rrPYYrQL3xylbglaEJ4tJJFNtJ0+DHsYBFkEoOG+Dn1A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2546 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org the vpu core depends on the mu resources. if they're missed, the vpu can't work. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index af3d6d9ead28..48bcc9355a7c 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -145,6 +145,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },