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Wed, 02 Jun 2021 09:31:33 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 02/12] memory: tegra: Unify struct tegra_mc across SoC generations Date: Wed, 2 Jun 2021 18:32:52 +0200 Message-Id: <20210602163302.120041-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093136_619781_2849F486 X-CRM114-Status: GOOD ( 18.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding As another step towards unifying both the Tegra210 (and earlier) and Tegra186 (and later) memory controller drivers, unify the structures that are used to represent them. Note that this comes at a slight space penalty since some fields are not used on all generations, but the benefits of unifying the driver outweigh the downsides. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 1281 ++++++++++++++++++++----------- include/soc/tegra/mc.h | 18 +- 2 files changed, 852 insertions(+), 447 deletions(-) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index e25c954dde2e..8e77567d1378 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -9,6 +9,8 @@ #include #include +#include + #if defined(CONFIG_ARCH_TEGRA_186_SOC) #include #endif @@ -17,47 +19,26 @@ #include #endif -struct tegra186_mc_client { - const char *name; - unsigned int sid; - struct { - unsigned int override; - unsigned int security; - } regs; -}; - -struct tegra186_mc_soc { - const struct tegra186_mc_client *clients; - unsigned int num_clients; -}; - -struct tegra186_mc { - struct device *dev; - void __iomem *regs; - - const struct tegra186_mc_soc *soc; -}; - -static void tegra186_mc_program_sid(struct tegra186_mc *mc) +static void tegra186_mc_program_sid(struct tegra_mc *mc) { unsigned int i; for (i = 0; i < mc->soc->num_clients; i++) { - const struct tegra186_mc_client *client = &mc->soc->clients[i]; + const struct tegra_mc_client *client = &mc->soc->clients[i]; u32 override, security; - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); + override = readl(mc->regs + client->regs.sid.override); + security = readl(mc->regs + client->regs.sid.security); dev_dbg(mc->dev, "client %s: override: %x security: %x\n", client->name, override, security); dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid, client->name); - writel(client->sid, mc->regs + client->regs.override); + writel(client->sid, mc->regs + client->regs.sid.override); - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); + override = readl(mc->regs + client->regs.sid.override); + security = readl(mc->regs + client->regs.sid.security); dev_dbg(mc->dev, "client %s: override: %x security: %x\n", client->name, override, security); @@ -65,1457 +46,1867 @@ static void tegra186_mc_program_sid(struct tegra186_mc *mc) } #if defined(CONFIG_ARCH_TEGRA_186_SOC) -static const struct tegra186_mc_client tegra186_mc_clients[] = { +static const struct tegra_mc_client tegra186_mc_clients[] = { { .name = "ptcr", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x000, - .security = 0x004, + .sid = { + .override = 0x000, + .security = 0x004, + }, }, }, { .name = "afir", .sid = TEGRA186_SID_AFI, .regs = { - .override = 0x070, - .security = 0x074, + .sid = { + .override = 0x070, + .security = 0x074, + }, }, }, { .name = "hdar", .sid = TEGRA186_SID_HDA, .regs = { - .override = 0x0a8, - .security = 0x0ac, + .sid = { + .override = 0x0a8, + .security = 0x0ac, + }, }, }, { .name = "host1xdmar", .sid = TEGRA186_SID_HOST1X, .regs = { - .override = 0x0b0, - .security = 0x0b4, + .sid = { + .override = 0x0b0, + .security = 0x0b4, + }, }, }, { .name = "nvencsrd", .sid = TEGRA186_SID_NVENC, .regs = { - .override = 0x0e0, - .security = 0x0e4, + .sid = { + .override = 0x0e0, + .security = 0x0e4, + }, }, }, { .name = "satar", .sid = TEGRA186_SID_SATA, .regs = { - .override = 0x0f8, - .security = 0x0fc, + .sid = { + .override = 0x0f8, + .security = 0x0fc, + }, }, }, { .name = "mpcorer", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x138, - .security = 0x13c, + .sid = { + .override = 0x138, + .security = 0x13c, + }, }, }, { .name = "nvencswr", .sid = TEGRA186_SID_NVENC, .regs = { - .override = 0x158, - .security = 0x15c, + .sid = { + .override = 0x158, + .security = 0x15c, + }, }, }, { .name = "afiw", .sid = TEGRA186_SID_AFI, .regs = { - .override = 0x188, - .security = 0x18c, + .sid = { + .override = 0x188, + .security = 0x18c, + }, }, }, { .name = "hdaw", .sid = TEGRA186_SID_HDA, .regs = { - .override = 0x1a8, - .security = 0x1ac, + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, }, }, { .name = "mpcorew", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { - .override = 0x1c8, - .security = 0x1cc, + .sid = { + .override = 0x1c8, + .security = 0x1cc, + }, }, }, { .name = "sataw", .sid = TEGRA186_SID_SATA, .regs = { - .override = 0x1e8, - .security = 0x1ec, + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, }, }, { .name = "ispra", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x220, - .security = 0x224, + .sid = { + .override = 0x220, + .security = 0x224, + }, }, }, { .name = "ispwa", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x230, - .security = 0x234, + .sid = { + .override = 0x230, + .security = 0x234, + }, }, }, { .name = "ispwb", .sid = TEGRA186_SID_ISP, .regs = { - .override = 0x238, - .security = 0x23c, + .sid = { + .override = 0x238, + .security = 0x23c, + }, }, }, { .name = "xusb_hostr", .sid = TEGRA186_SID_XUSB_HOST, .regs = { - .override = 0x250, - .security = 0x254, + .sid = { + .override = 0x250, + .security = 0x254, + }, }, }, { .name = "xusb_hostw", .sid = TEGRA186_SID_XUSB_HOST, .regs = { - .override = 0x258, - .security = 0x25c, + .sid = { + .override = 0x258, + .security = 0x25c, + }, }, }, { .name = "xusb_devr", .sid = TEGRA186_SID_XUSB_DEV, .regs = { - .override = 0x260, - .security = 0x264, + .sid = { + .override = 0x260, + .security = 0x264, + }, }, }, { .name = "xusb_devw", .sid = TEGRA186_SID_XUSB_DEV, .regs = { - .override = 0x268, - .security = 0x26c, + .sid = { + .override = 0x268, + .security = 0x26c, + }, }, }, { .name = "tsecsrd", .sid = TEGRA186_SID_TSEC, .regs = { - .override = 0x2a0, - .security = 0x2a4, + .sid = { + .override = 0x2a0, + .security = 0x2a4, + }, }, }, { .name = "tsecswr", .sid = TEGRA186_SID_TSEC, .regs = { - .override = 0x2a8, - .security = 0x2ac, + .sid = { + .override = 0x2a8, + .security = 0x2ac, + }, }, }, { .name = "gpusrd", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x2c0, - .security = 0x2c4, + .sid = { + .override = 0x2c0, + .security = 0x2c4, + }, }, }, { .name = "gpuswr", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x2c8, - .security = 0x2cc, + .sid = { + .override = 0x2c8, + .security = 0x2cc, + }, }, }, { .name = "sdmmcra", .sid = TEGRA186_SID_SDMMC1, .regs = { - .override = 0x300, - .security = 0x304, + .sid = { + .override = 0x300, + .security = 0x304, + }, }, }, { .name = "sdmmcraa", .sid = TEGRA186_SID_SDMMC2, .regs = { - .override = 0x308, - .security = 0x30c, + .sid = { + .override = 0x308, + .security = 0x30c, + }, }, }, { .name = "sdmmcr", .sid = TEGRA186_SID_SDMMC3, .regs = { - .override = 0x310, - .security = 0x314, + .sid = { + .override = 0x310, + .security = 0x314, + }, }, }, { .name = "sdmmcrab", .sid = TEGRA186_SID_SDMMC4, .regs = { - .override = 0x318, - .security = 0x31c, + .sid = { + .override = 0x318, + .security = 0x31c, + }, }, }, { .name = "sdmmcwa", .sid = TEGRA186_SID_SDMMC1, .regs = { - .override = 0x320, - .security = 0x324, + .sid = { + .override = 0x320, + .security = 0x324, + }, }, }, { .name = "sdmmcwaa", .sid = TEGRA186_SID_SDMMC2, .regs = { - .override = 0x328, - .security = 0x32c, + .sid = { + .override = 0x328, + .security = 0x32c, + }, }, }, { .name = "sdmmcw", .sid = TEGRA186_SID_SDMMC3, .regs = { - .override = 0x330, - .security = 0x334, + .sid = { + .override = 0x330, + .security = 0x334, + }, }, }, { .name = "sdmmcwab", .sid = TEGRA186_SID_SDMMC4, .regs = { - .override = 0x338, - .security = 0x33c, + .sid = { + .override = 0x338, + .security = 0x33c, + }, }, }, { .name = "vicsrd", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x360, - .security = 0x364, + .sid = { + .override = 0x360, + .security = 0x364, + }, }, }, { .name = "vicswr", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x368, - .security = 0x36c, + .sid = { + .override = 0x368, + .security = 0x36c, + }, }, }, { .name = "viw", .sid = TEGRA186_SID_VI, .regs = { - .override = 0x390, - .security = 0x394, + .sid = { + .override = 0x390, + .security = 0x394, + }, }, }, { .name = "nvdecsrd", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "nvdecswr", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x3c8, - .security = 0x3cc, + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, }, }, { .name = "aper", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x3d0, - .security = 0x3d4, + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, }, }, { .name = "apew", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x3d8, - .security = 0x3dc, + .sid = { + .override = 0x3d8, + .security = 0x3dc, + }, }, }, { .name = "nvjpgsrd", .sid = TEGRA186_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "nvjpgswr", .sid = TEGRA186_SID_NVJPG, .regs = { - .override = 0x3f8, - .security = 0x3fc, + .sid = { + .override = 0x3f8, + .security = 0x3fc, + }, }, }, { .name = "sesrd", .sid = TEGRA186_SID_SE, .regs = { - .override = 0x400, - .security = 0x404, + .sid = { + .override = 0x400, + .security = 0x404, + }, }, }, { .name = "seswr", .sid = TEGRA186_SID_SE, .regs = { - .override = 0x408, - .security = 0x40c, + .sid = { + .override = 0x408, + .security = 0x40c, + }, }, }, { .name = "etrr", .sid = TEGRA186_SID_ETR, .regs = { - .override = 0x420, - .security = 0x424, + .sid = { + .override = 0x420, + .security = 0x424, + }, }, }, { .name = "etrw", .sid = TEGRA186_SID_ETR, .regs = { - .override = 0x428, - .security = 0x42c, + .sid = { + .override = 0x428, + .security = 0x42c, + }, }, }, { .name = "tsecsrdb", .sid = TEGRA186_SID_TSECB, .regs = { - .override = 0x430, - .security = 0x434, + .sid = { + .override = 0x430, + .security = 0x434, + }, }, }, { .name = "tsecswrb", .sid = TEGRA186_SID_TSECB, .regs = { - .override = 0x438, - .security = 0x43c, + .sid = { + .override = 0x438, + .security = 0x43c, + }, }, }, { .name = "gpusrd2", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x440, - .security = 0x444, + .sid = { + .override = 0x440, + .security = 0x444, + }, }, }, { .name = "gpuswr2", .sid = TEGRA186_SID_GPU, .regs = { - .override = 0x448, - .security = 0x44c, + .sid = { + .override = 0x448, + .security = 0x44c, + }, }, }, { .name = "axisr", .sid = TEGRA186_SID_GPCDMA_0, .regs = { - .override = 0x460, - .security = 0x464, + .sid = { + .override = 0x460, + .security = 0x464, + }, }, }, { .name = "axisw", .sid = TEGRA186_SID_GPCDMA_0, .regs = { - .override = 0x468, - .security = 0x46c, + .sid = { + .override = 0x468, + .security = 0x46c, + }, }, }, { .name = "eqosr", .sid = TEGRA186_SID_EQOS, .regs = { - .override = 0x470, - .security = 0x474, + .sid = { + .override = 0x470, + .security = 0x474, + }, }, }, { .name = "eqosw", .sid = TEGRA186_SID_EQOS, .regs = { - .override = 0x478, - .security = 0x47c, + .sid = { + .override = 0x478, + .security = 0x47c, + }, }, }, { .name = "ufshcr", .sid = TEGRA186_SID_UFSHC, .regs = { - .override = 0x480, - .security = 0x484, + .sid = { + .override = 0x480, + .security = 0x484, + }, }, }, { .name = "ufshcw", .sid = TEGRA186_SID_UFSHC, .regs = { - .override = 0x488, - .security = 0x48c, + .sid = { + .override = 0x488, + .security = 0x48c, + }, }, }, { .name = "nvdisplayr", .sid = TEGRA186_SID_NVDISPLAY, .regs = { - .override = 0x490, - .security = 0x494, + .sid = { + .override = 0x490, + .security = 0x494, + }, }, }, { .name = "bpmpr", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x498, - .security = 0x49c, + .sid = { + .override = 0x498, + .security = 0x49c, + }, }, }, { .name = "bpmpw", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4a0, - .security = 0x4a4, + .sid = { + .override = 0x4a0, + .security = 0x4a4, + }, }, }, { .name = "bpmpdmar", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4a8, - .security = 0x4ac, + .sid = { + .override = 0x4a8, + .security = 0x4ac, + }, }, }, { .name = "bpmpdmaw", .sid = TEGRA186_SID_BPMP, .regs = { - .override = 0x4b0, - .security = 0x4b4, + .sid = { + .override = 0x4b0, + .security = 0x4b4, + }, }, }, { .name = "aonr", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4b8, - .security = 0x4bc, + .sid = { + .override = 0x4b8, + .security = 0x4bc, + }, }, }, { .name = "aonw", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4c0, - .security = 0x4c4, + .sid = { + .override = 0x4c0, + .security = 0x4c4, + }, }, }, { .name = "aondmar", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4c8, - .security = 0x4cc, + .sid = { + .override = 0x4c8, + .security = 0x4cc, + }, }, }, { .name = "aondmaw", .sid = TEGRA186_SID_AON, .regs = { - .override = 0x4d0, - .security = 0x4d4, + .sid = { + .override = 0x4d0, + .security = 0x4d4, + }, }, }, { .name = "scer", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4d8, - .security = 0x4dc, + .sid = { + .override = 0x4d8, + .security = 0x4dc, + }, }, }, { .name = "scew", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4e0, - .security = 0x4e4, + .sid = { + .override = 0x4e0, + .security = 0x4e4, + }, }, }, { .name = "scedmar", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4e8, - .security = 0x4ec, + .sid = { + .override = 0x4e8, + .security = 0x4ec, + }, }, }, { .name = "scedmaw", .sid = TEGRA186_SID_SCE, .regs = { - .override = 0x4f0, - .security = 0x4f4, + .sid = { + .override = 0x4f0, + .security = 0x4f4, + }, }, }, { .name = "apedmar", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x4f8, - .security = 0x4fc, + .sid = { + .override = 0x4f8, + .security = 0x4fc, + }, }, }, { .name = "apedmaw", .sid = TEGRA186_SID_APE, .regs = { - .override = 0x500, - .security = 0x504, + .sid = { + .override = 0x500, + .security = 0x504, + }, }, }, { .name = "nvdisplayr1", .sid = TEGRA186_SID_NVDISPLAY, .regs = { - .override = 0x508, - .security = 0x50c, + .sid = { + .override = 0x508, + .security = 0x50c, + }, }, }, { .name = "vicsrd1", .sid = TEGRA186_SID_VIC, .regs = { - .override = 0x510, - .security = 0x514, + .sid = { + .override = 0x510, + .security = 0x514, + }, }, }, { .name = "nvdecsrd1", .sid = TEGRA186_SID_NVDEC, .regs = { - .override = 0x518, - .security = 0x51c, + .sid = { + .override = 0x518, + .security = 0x51c, + }, }, }, }; -static const struct tegra186_mc_soc tegra186_mc_soc = { +static const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, }; #endif #if defined(CONFIG_ARCH_TEGRA_194_SOC) -static const struct tegra186_mc_client tegra194_mc_clients[] = { +static const struct tegra_mc_client tegra194_mc_clients[] = { { .name = "ptcr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x000, - .security = 0x004, + .sid = { + .override = 0x000, + .security = 0x004, + }, }, }, { .name = "miu7r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x008, - .security = 0x00c, + .sid = { + .override = 0x008, + .security = 0x00c, + }, }, }, { .name = "miu7w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x010, - .security = 0x014, + .sid = { + .override = 0x010, + .security = 0x014, + }, }, }, { .name = "hdar", .sid = TEGRA194_SID_HDA, .regs = { - .override = 0x0a8, - .security = 0x0ac, + .sid = { + .override = 0x0a8, + .security = 0x0ac, + }, }, }, { .name = "host1xdmar", .sid = TEGRA194_SID_HOST1X, .regs = { - .override = 0x0b0, - .security = 0x0b4, + .sid = { + .override = 0x0b0, + .security = 0x0b4, + }, }, }, { .name = "nvencsrd", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x0e0, - .security = 0x0e4, + .sid = { + .override = 0x0e0, + .security = 0x0e4, + }, }, }, { .name = "satar", .sid = TEGRA194_SID_SATA, .regs = { - .override = 0x0f8, - .security = 0x0fc, + .sid = { + .override = 0x0f8, + .security = 0x0fc, + }, }, }, { .name = "mpcorer", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x138, - .security = 0x13c, + .sid = { + .override = 0x138, + .security = 0x13c, + }, }, }, { .name = "nvencswr", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x158, - .security = 0x15c, + .sid = { + .override = 0x158, + .security = 0x15c, + }, }, }, { .name = "hdaw", .sid = TEGRA194_SID_HDA, .regs = { - .override = 0x1a8, - .security = 0x1ac, + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, }, }, { .name = "mpcorew", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x1c8, - .security = 0x1cc, + .sid = { + .override = 0x1c8, + .security = 0x1cc, + }, }, }, { .name = "sataw", .sid = TEGRA194_SID_SATA, .regs = { - .override = 0x1e8, - .security = 0x1ec, + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, }, }, { .name = "ispra", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x220, - .security = 0x224, + .sid = { + .override = 0x220, + .security = 0x224, + }, }, }, { .name = "ispfalr", .sid = TEGRA194_SID_ISP_FALCON, .regs = { - .override = 0x228, - .security = 0x22c, + .sid = { + .override = 0x228, + .security = 0x22c, + }, }, }, { .name = "ispwa", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x230, - .security = 0x234, + .sid = { + .override = 0x230, + .security = 0x234, + }, }, }, { .name = "ispwb", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x238, - .security = 0x23c, + .sid = { + .override = 0x238, + .security = 0x23c, + }, }, }, { .name = "xusb_hostr", .sid = TEGRA194_SID_XUSB_HOST, .regs = { - .override = 0x250, - .security = 0x254, + .sid = { + .override = 0x250, + .security = 0x254, + }, }, }, { .name = "xusb_hostw", .sid = TEGRA194_SID_XUSB_HOST, .regs = { - .override = 0x258, - .security = 0x25c, + .sid = { + .override = 0x258, + .security = 0x25c, + }, }, }, { .name = "xusb_devr", .sid = TEGRA194_SID_XUSB_DEV, .regs = { - .override = 0x260, - .security = 0x264, + .sid = { + .override = 0x260, + .security = 0x264, + }, }, }, { .name = "xusb_devw", .sid = TEGRA194_SID_XUSB_DEV, .regs = { - .override = 0x268, - .security = 0x26c, + .sid = { + .override = 0x268, + .security = 0x26c, + }, }, }, { .name = "sdmmcra", .sid = TEGRA194_SID_SDMMC1, .regs = { - .override = 0x300, - .security = 0x304, + .sid = { + .override = 0x300, + .security = 0x304, + }, }, }, { .name = "sdmmcr", .sid = TEGRA194_SID_SDMMC3, .regs = { - .override = 0x310, - .security = 0x314, + .sid = { + .override = 0x310, + .security = 0x314, + }, }, }, { .name = "sdmmcrab", .sid = TEGRA194_SID_SDMMC4, .regs = { - .override = 0x318, - .security = 0x31c, + .sid = { + .override = 0x318, + .security = 0x31c, + }, }, }, { .name = "sdmmcwa", .sid = TEGRA194_SID_SDMMC1, .regs = { - .override = 0x320, - .security = 0x324, + .sid = { + .override = 0x320, + .security = 0x324, + }, }, }, { .name = "sdmmcw", .sid = TEGRA194_SID_SDMMC3, .regs = { - .override = 0x330, - .security = 0x334, + .sid = { + .override = 0x330, + .security = 0x334, + }, }, }, { .name = "sdmmcwab", .sid = TEGRA194_SID_SDMMC4, .regs = { - .override = 0x338, - .security = 0x33c, + .sid = { + .override = 0x338, + .security = 0x33c, + }, }, }, { .name = "vicsrd", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x360, - .security = 0x364, + .sid = { + .override = 0x360, + .security = 0x364, + }, }, }, { .name = "vicswr", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x368, - .security = 0x36c, + .sid = { + .override = 0x368, + .security = 0x36c, + }, }, }, { .name = "viw", .sid = TEGRA194_SID_VI, .regs = { - .override = 0x390, - .security = 0x394, + .sid = { + .override = 0x390, + .security = 0x394, + }, }, }, { .name = "nvdecsrd", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "nvdecswr", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x3c8, - .security = 0x3cc, + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, }, }, { .name = "aper", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x3c0, - .security = 0x3c4, + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, }, }, { .name = "apew", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x3d0, - .security = 0x3d4, + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, }, }, { .name = "nvjpgsrd", .sid = TEGRA194_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "nvjpgswr", .sid = TEGRA194_SID_NVJPG, .regs = { - .override = 0x3f0, - .security = 0x3f4, + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, }, }, { .name = "axiapr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x410, - .security = 0x414, + .sid = { + .override = 0x410, + .security = 0x414, + }, }, }, { .name = "axiapw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x418, - .security = 0x41c, + .sid = { + .override = 0x418, + .security = 0x41c, + }, }, }, { .name = "etrr", .sid = TEGRA194_SID_ETR, .regs = { - .override = 0x420, - .security = 0x424, + .sid = { + .override = 0x420, + .security = 0x424, + }, }, }, { .name = "etrw", .sid = TEGRA194_SID_ETR, .regs = { - .override = 0x428, - .security = 0x42c, + .sid = { + .override = 0x428, + .security = 0x42c, + }, }, }, { .name = "axisr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x460, - .security = 0x464, + .sid = { + .override = 0x460, + .security = 0x464, + }, }, }, { .name = "axisw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x468, - .security = 0x46c, + .sid = { + .override = 0x468, + .security = 0x46c, + }, }, }, { .name = "eqosr", .sid = TEGRA194_SID_EQOS, .regs = { - .override = 0x470, - .security = 0x474, + .sid = { + .override = 0x470, + .security = 0x474, + }, }, }, { .name = "eqosw", .sid = TEGRA194_SID_EQOS, .regs = { - .override = 0x478, - .security = 0x47c, + .sid = { + .override = 0x478, + .security = 0x47c, + }, }, }, { .name = "ufshcr", .sid = TEGRA194_SID_UFSHC, .regs = { - .override = 0x480, - .security = 0x484, + .sid = { + .override = 0x480, + .security = 0x484, + }, }, }, { .name = "ufshcw", .sid = TEGRA194_SID_UFSHC, .regs = { - .override = 0x488, - .security = 0x48c, + .sid = { + .override = 0x488, + .security = 0x48c, + }, }, }, { .name = "nvdisplayr", .sid = TEGRA194_SID_NVDISPLAY, .regs = { - .override = 0x490, - .security = 0x494, + .sid = { + .override = 0x490, + .security = 0x494, + }, }, }, { .name = "bpmpr", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x498, - .security = 0x49c, + .sid = { + .override = 0x498, + .security = 0x49c, + }, }, }, { .name = "bpmpw", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4a0, - .security = 0x4a4, + .sid = { + .override = 0x4a0, + .security = 0x4a4, + }, }, }, { .name = "bpmpdmar", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4a8, - .security = 0x4ac, + .sid = { + .override = 0x4a8, + .security = 0x4ac, + }, }, }, { .name = "bpmpdmaw", .sid = TEGRA194_SID_BPMP, .regs = { - .override = 0x4b0, - .security = 0x4b4, + .sid = { + .override = 0x4b0, + .security = 0x4b4, + }, }, }, { .name = "aonr", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4b8, - .security = 0x4bc, + .sid = { + .override = 0x4b8, + .security = 0x4bc, + }, }, }, { .name = "aonw", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4c0, - .security = 0x4c4, + .sid = { + .override = 0x4c0, + .security = 0x4c4, + }, }, }, { .name = "aondmar", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4c8, - .security = 0x4cc, + .sid = { + .override = 0x4c8, + .security = 0x4cc, + }, }, }, { .name = "aondmaw", .sid = TEGRA194_SID_AON, .regs = { - .override = 0x4d0, - .security = 0x4d4, + .sid = { + .override = 0x4d0, + .security = 0x4d4, + }, }, }, { .name = "scer", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4d8, - .security = 0x4dc, + .sid = { + .override = 0x4d8, + .security = 0x4dc, + }, }, }, { .name = "scew", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4e0, - .security = 0x4e4, + .sid = { + .override = 0x4e0, + .security = 0x4e4, + }, }, }, { .name = "scedmar", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4e8, - .security = 0x4ec, + .sid = { + .override = 0x4e8, + .security = 0x4ec, + }, }, }, { .name = "scedmaw", .sid = TEGRA194_SID_SCE, .regs = { - .override = 0x4f0, - .security = 0x4f4, + .sid = { + .override = 0x4f0, + .security = 0x4f4, + }, }, }, { .name = "apedmar", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x4f8, - .security = 0x4fc, + .sid = { + .override = 0x4f8, + .security = 0x4fc, + }, }, }, { .name = "apedmaw", .sid = TEGRA194_SID_APE, .regs = { - .override = 0x500, - .security = 0x504, + .sid = { + .override = 0x500, + .security = 0x504, + }, }, }, { .name = "nvdisplayr1", .sid = TEGRA194_SID_NVDISPLAY, .regs = { - .override = 0x508, - .security = 0x50c, + .sid = { + .override = 0x508, + .security = 0x50c, + }, }, }, { .name = "vicsrd1", .sid = TEGRA194_SID_VIC, .regs = { - .override = 0x510, - .security = 0x514, + .sid = { + .override = 0x510, + .security = 0x514, + }, }, }, { .name = "nvdecsrd1", .sid = TEGRA194_SID_NVDEC, .regs = { - .override = 0x518, - .security = 0x51c, + .sid = { + .override = 0x518, + .security = 0x51c, + }, }, }, { .name = "miu0r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x530, - .security = 0x534, + .sid = { + .override = 0x530, + .security = 0x534, + }, }, }, { .name = "miu0w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x538, - .security = 0x53c, + .sid = { + .override = 0x538, + .security = 0x53c, + }, }, }, { .name = "miu1r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x540, - .security = 0x544, + .sid = { + .override = 0x540, + .security = 0x544, + }, }, }, { .name = "miu1w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x548, - .security = 0x54c, + .sid = { + .override = 0x548, + .security = 0x54c, + }, }, }, { .name = "miu2r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x570, - .security = 0x574, + .sid = { + .override = 0x570, + .security = 0x574, + }, }, }, { .name = "miu2w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x578, - .security = 0x57c, + .sid = { + .override = 0x578, + .security = 0x57c, + }, }, }, { .name = "miu3r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x580, - .security = 0x584, + .sid = { + .override = 0x580, + .security = 0x584, + }, }, }, { .name = "miu3w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x588, - .security = 0x58c, + .sid = { + .override = 0x588, + .security = 0x58c, + }, }, }, { .name = "miu4r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x590, - .security = 0x594, + .sid = { + .override = 0x590, + .security = 0x594, + }, }, }, { .name = "miu4w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x598, - .security = 0x59c, + .sid = { + .override = 0x598, + .security = 0x59c, + }, }, }, { .name = "dpmur", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { - .override = 0x598, - .security = 0x59c, + .sid = { + .override = 0x598, + .security = 0x59c, + }, }, }, { .name = "vifalr", .sid = TEGRA194_SID_VI_FALCON, .regs = { - .override = 0x5e0, - .security = 0x5e4, + .sid = { + .override = 0x5e0, + .security = 0x5e4, + }, }, }, { .name = "vifalw", .sid = TEGRA194_SID_VI_FALCON, .regs = { - .override = 0x5e8, - .security = 0x5ec, + .sid = { + .override = 0x5e8, + .security = 0x5ec, + }, }, }, { .name = "dla0rda", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x5f0, - .security = 0x5f4, + .sid = { + .override = 0x5f0, + .security = 0x5f4, + }, }, }, { .name = "dla0falrdb", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x5f8, - .security = 0x5fc, + .sid = { + .override = 0x5f8, + .security = 0x5fc, + }, }, }, { .name = "dla0wra", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x600, - .security = 0x604, + .sid = { + .override = 0x600, + .security = 0x604, + }, }, }, { .name = "dla0falwrb", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x608, - .security = 0x60c, + .sid = { + .override = 0x608, + .security = 0x60c, + }, }, }, { .name = "dla1rda", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x610, - .security = 0x614, + .sid = { + .override = 0x610, + .security = 0x614, + }, }, }, { .name = "dla1falrdb", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x618, - .security = 0x61c, + .sid = { + .override = 0x618, + .security = 0x61c, + }, }, }, { .name = "dla1wra", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x620, - .security = 0x624, + .sid = { + .override = 0x620, + .security = 0x624, + }, }, }, { .name = "dla1falwrb", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x628, - .security = 0x62c, + .sid = { + .override = 0x628, + .security = 0x62c, + }, }, }, { .name = "pva0rda", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x630, - .security = 0x634, + .sid = { + .override = 0x630, + .security = 0x634, + }, }, }, { .name = "pva0rdb", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x638, - .security = 0x63c, + .sid = { + .override = 0x638, + .security = 0x63c, + }, }, }, { .name = "pva0rdc", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x640, - .security = 0x644, + .sid = { + .override = 0x640, + .security = 0x644, + }, }, }, { .name = "pva0wra", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x648, - .security = 0x64c, + .sid = { + .override = 0x648, + .security = 0x64c, + }, }, }, { .name = "pva0wrb", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x650, - .security = 0x654, + .sid = { + .override = 0x650, + .security = 0x654, + }, }, }, { .name = "pva0wrc", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x658, - .security = 0x65c, + .sid = { + .override = 0x658, + .security = 0x65c, + }, }, }, { .name = "pva1rda", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x660, - .security = 0x664, + .sid = { + .override = 0x660, + .security = 0x664, + }, }, }, { .name = "pva1rdb", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x668, - .security = 0x66c, + .sid = { + .override = 0x668, + .security = 0x66c, + }, }, }, { .name = "pva1rdc", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x670, - .security = 0x674, + .sid = { + .override = 0x670, + .security = 0x674, + }, }, }, { .name = "pva1wra", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x678, - .security = 0x67c, + .sid = { + .override = 0x678, + .security = 0x67c, + }, }, }, { .name = "pva1wrb", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x680, - .security = 0x684, + .sid = { + .override = 0x680, + .security = 0x684, + }, }, }, { .name = "pva1wrc", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x688, - .security = 0x68c, + .sid = { + .override = 0x688, + .security = 0x68c, + }, }, }, { .name = "rcer", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x690, - .security = 0x694, + .sid = { + .override = 0x690, + .security = 0x694, + }, }, }, { .name = "rcew", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x698, - .security = 0x69c, + .sid = { + .override = 0x698, + .security = 0x69c, + }, }, }, { .name = "rcedmar", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x6a0, - .security = 0x6a4, + .sid = { + .override = 0x6a0, + .security = 0x6a4, + }, }, }, { .name = "rcedmaw", .sid = TEGRA194_SID_RCE, .regs = { - .override = 0x6a8, - .security = 0x6ac, + .sid = { + .override = 0x6a8, + .security = 0x6ac, + }, }, }, { .name = "nvenc1srd", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x6b0, - .security = 0x6b4, + .sid = { + .override = 0x6b0, + .security = 0x6b4, + }, }, }, { .name = "nvenc1swr", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x6b8, - .security = 0x6bc, + .sid = { + .override = 0x6b8, + .security = 0x6bc, + }, }, }, { .name = "pcie0r", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x6c0, - .security = 0x6c4, + .sid = { + .override = 0x6c0, + .security = 0x6c4, + }, }, }, { .name = "pcie0w", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x6c8, - .security = 0x6cc, + .sid = { + .override = 0x6c8, + .security = 0x6cc, + }, }, }, { .name = "pcie1r", .sid = TEGRA194_SID_PCIE1, .regs = { - .override = 0x6d0, - .security = 0x6d4, + .sid = { + .override = 0x6d0, + .security = 0x6d4, + }, }, }, { .name = "pcie1w", .sid = TEGRA194_SID_PCIE1, .regs = { - .override = 0x6d8, - .security = 0x6dc, + .sid = { + .override = 0x6d8, + .security = 0x6dc, + }, }, }, { .name = "pcie2ar", .sid = TEGRA194_SID_PCIE2, .regs = { - .override = 0x6e0, - .security = 0x6e4, + .sid = { + .override = 0x6e0, + .security = 0x6e4, + }, }, }, { .name = "pcie2aw", .sid = TEGRA194_SID_PCIE2, .regs = { - .override = 0x6e8, - .security = 0x6ec, + .sid = { + .override = 0x6e8, + .security = 0x6ec, + }, }, }, { .name = "pcie3r", .sid = TEGRA194_SID_PCIE3, .regs = { - .override = 0x6f0, - .security = 0x6f4, + .sid = { + .override = 0x6f0, + .security = 0x6f4, + }, }, }, { .name = "pcie3w", .sid = TEGRA194_SID_PCIE3, .regs = { - .override = 0x6f8, - .security = 0x6fc, + .sid = { + .override = 0x6f8, + .security = 0x6fc, + }, }, }, { .name = "pcie4r", .sid = TEGRA194_SID_PCIE4, .regs = { - .override = 0x700, - .security = 0x704, + .sid = { + .override = 0x700, + .security = 0x704, + }, }, }, { .name = "pcie4w", .sid = TEGRA194_SID_PCIE4, .regs = { - .override = 0x708, - .security = 0x70c, + .sid = { + .override = 0x708, + .security = 0x70c, + }, }, }, { .name = "pcie5r", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x710, - .security = 0x714, + .sid = { + .override = 0x710, + .security = 0x714, + }, }, }, { .name = "pcie5w", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x718, - .security = 0x71c, + .sid = { + .override = 0x718, + .security = 0x71c, + }, }, }, { .name = "ispfalw", .sid = TEGRA194_SID_ISP_FALCON, .regs = { - .override = 0x720, - .security = 0x724, + .sid = { + .override = 0x720, + .security = 0x724, + }, }, }, { .name = "dla0rda1", .sid = TEGRA194_SID_NVDLA0, .regs = { - .override = 0x748, - .security = 0x74c, + .sid = { + .override = 0x748, + .security = 0x74c, + }, }, }, { .name = "dla1rda1", .sid = TEGRA194_SID_NVDLA1, .regs = { - .override = 0x750, - .security = 0x754, + .sid = { + .override = 0x750, + .security = 0x754, + }, }, }, { .name = "pva0rda1", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x758, - .security = 0x75c, + .sid = { + .override = 0x758, + .security = 0x75c, + }, }, }, { .name = "pva0rdb1", .sid = TEGRA194_SID_PVA0, .regs = { - .override = 0x760, - .security = 0x764, + .sid = { + .override = 0x760, + .security = 0x764, + }, }, }, { .name = "pva1rda1", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x768, - .security = 0x76c, + .sid = { + .override = 0x768, + .security = 0x76c, + }, }, }, { .name = "pva1rdb1", .sid = TEGRA194_SID_PVA1, .regs = { - .override = 0x770, - .security = 0x774, + .sid = { + .override = 0x770, + .security = 0x774, + }, }, }, { .name = "pcie5r1", .sid = TEGRA194_SID_PCIE5, .regs = { - .override = 0x778, - .security = 0x77c, + .sid = { + .override = 0x778, + .security = 0x77c, + }, }, }, { .name = "nvencsrd1", .sid = TEGRA194_SID_NVENC, .regs = { - .override = 0x780, - .security = 0x784, + .sid = { + .override = 0x780, + .security = 0x784, + }, }, }, { .name = "nvenc1srd1", .sid = TEGRA194_SID_NVENC1, .regs = { - .override = 0x788, - .security = 0x78c, + .sid = { + .override = 0x788, + .security = 0x78c, + }, }, }, { .name = "ispra1", .sid = TEGRA194_SID_ISP, .regs = { - .override = 0x790, - .security = 0x794, + .sid = { + .override = 0x790, + .security = 0x794, + }, }, }, { .name = "pcie0r1", .sid = TEGRA194_SID_PCIE0, .regs = { - .override = 0x798, - .security = 0x79c, + .sid = { + .override = 0x798, + .security = 0x79c, + }, }, }, { .name = "nvdec1srd", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7c8, - .security = 0x7cc, + .sid = { + .override = 0x7c8, + .security = 0x7cc, + }, }, }, { .name = "nvdec1srd1", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7d0, - .security = 0x7d4, + .sid = { + .override = 0x7d0, + .security = 0x7d4, + }, }, }, { .name = "nvdec1swr", .sid = TEGRA194_SID_NVDEC1, .regs = { - .override = 0x7d8, - .security = 0x7dc, + .sid = { + .override = 0x7d8, + .security = 0x7dc, + }, }, }, { .name = "miu5r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7e0, - .security = 0x7e4, + .sid = { + .override = 0x7e0, + .security = 0x7e4, + }, }, }, { .name = "miu5w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7e8, - .security = 0x7ec, + .sid = { + .override = 0x7e8, + .security = 0x7ec, + }, }, }, { .name = "miu6r", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7f0, - .security = 0x7f4, + .sid = { + .override = 0x7f0, + .security = 0x7f4, + }, }, }, { .name = "miu6w", .sid = TEGRA194_SID_MIU, .regs = { - .override = 0x7f8, - .security = 0x7fc, + .sid = { + .override = 0x7f8, + .security = 0x7fc, + }, }, }, }; -static const struct tegra186_mc_soc tegra194_mc_soc = { +static const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, }; @@ -1523,8 +1914,8 @@ static const struct tegra186_mc_soc tegra194_mc_soc = { static int tegra186_mc_probe(struct platform_device *pdev) { - struct tegra186_mc *mc; struct resource *res; + struct tegra_mc *mc; int err; mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); @@ -1552,7 +1943,7 @@ static int tegra186_mc_probe(struct platform_device *pdev) static int tegra186_mc_remove(struct platform_device *pdev) { - struct tegra186_mc *mc = platform_get_drvdata(pdev); + struct tegra_mc *mc = platform_get_drvdata(pdev); of_platform_depopulate(mc->dev); @@ -1577,7 +1968,7 @@ static int __maybe_unused tegra186_mc_suspend(struct device *dev) static int __maybe_unused tegra186_mc_resume(struct device *dev) { - struct tegra186_mc *mc = dev_get_drvdata(dev); + struct tegra_mc *mc = dev_get_drvdata(dev); tegra186_mc_program_sid(mc); diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index dd26505464c2..9da4ef52ce30 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -26,12 +26,20 @@ struct tegra_mc_timing { struct tegra_mc_client { unsigned int id; const char *name; - unsigned int swgroup; + /* + * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the + * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU + * stream ID used for IOVA translations for the given memory client. + */ + union { + unsigned int swgroup; + unsigned int sid; + }; unsigned int fifo_size; struct { - /* Tegra SMMU enable */ + /* Tegra SMMU enable (Tegra210 and earlier) */ struct { unsigned int reg; unsigned int bit; @@ -44,6 +52,12 @@ struct tegra_mc_client { unsigned int mask; unsigned int def; } la; + + /* stream ID overrides (Tegra186 and later) */ + struct { + unsigned int override; + unsigned int security; + } sid; } regs; }; From patchwork Wed Jun 2 16:32:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from 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Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 03/12] memory: tegra: Introduce struct tegra_mc_ops Date: Wed, 2 Jun 2021 18:32:53 +0200 Message-Id: <20210602163302.120041-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093237_750253_C45655A9 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Subsequent patches will introduce further callbacks, so create a new struct tegra_mc_ops to collect all of them in a single place. Move the existing ->init() callback into the new structure. Signed-off-by: Thierry Reding --- Changes in v2: - new patch (suggested by Krzysztof) drivers/memory/tegra/mc.c | 4 ++-- drivers/memory/tegra/tegra20.c | 6 +++++- include/soc/tegra/mc.h | 7 +++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index b7e104bf6614..559ae1ef5633 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -829,8 +829,8 @@ static int tegra_mc_probe(struct platform_device *pdev) mc->debugfs.root = debugfs_create_dir("mc", NULL); - if (mc->soc->init) { - err = mc->soc->init(mc); + if (mc->soc->ops && mc->soc->ops->init) { + err = mc->soc->ops->init(mc); if (err < 0) dev_err(&pdev->dev, "failed to initialize SoC driver: %d\n", err); diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 2db68a913b7a..3b7b93b96480 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -687,6 +687,10 @@ static int tegra20_mc_init(struct tegra_mc *mc) return 0; } +static const struct tegra_mc_ops tegra20_mc_ops = { + .init = tegra20_mc_init, +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -698,5 +702,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), .icc_ops = &tegra20_mc_icc_ops, - .init = tegra20_mc_init, + .ops = &tegra20_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 9da4ef52ce30..4f88da907a02 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -169,6 +169,10 @@ struct tegra_mc_icc_ops { void *data); }; +struct tegra_mc_ops { + int (*init)(struct tegra_mc *mc); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -190,8 +194,7 @@ struct tegra_mc_soc { unsigned int num_resets; const struct tegra_mc_icc_ops *icc_ops; - - int (*init)(struct tegra_mc *mc); + const struct tegra_mc_ops *ops; }; struct tegra_mc { From patchwork Wed Jun 2 16:32:54 2021 Content-Type: text/plain; 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Wed, 02 Jun 2021 09:31:37 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 04/12] memory: tegra: Push suspend/resume into SoC drivers Date: Wed, 2 Jun 2021 18:32:54 +0200 Message-Id: <20210602163302.120041-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093140_537010_D51E3C68 X-CRM114-Status: GOOD ( 17.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Continuing the scheme of unification, push suspend/resume callbacks into per-SoC driver so that they can be properly parameterized. Signed-off-by: Thierry Reding --- Changes in v2: - split ->init callback hunk into separate patch (Krzysztof) - use SET_SYSTEM_SLEEP_PM_OPS (Dmitry) drivers/memory/tegra/mc.c | 23 +++++++---------------- drivers/memory/tegra/tegra186.c | 27 +++++++++++++++++++++++---- drivers/memory/tegra/tegra20.c | 28 ++++++++++++++++++++++++++++ include/soc/tegra/mc.h | 2 ++ 4 files changed, 60 insertions(+), 20 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 559ae1ef5633..a3b7ba33b7f9 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -867,37 +867,28 @@ static int tegra_mc_probe(struct platform_device *pdev) return 0; } -static int tegra_mc_suspend(struct device *dev) +static int __maybe_unused tegra_mc_suspend(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - int err; - if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { - err = tegra_gart_suspend(mc->gart); - if (err) - return err; - } + if (mc->soc->ops && mc->soc->ops->suspend) + return mc->soc->ops->suspend(mc); return 0; } -static int tegra_mc_resume(struct device *dev) +static int __maybe_unused tegra_mc_resume(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - int err; - if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { - err = tegra_gart_resume(mc->gart); - if (err) - return err; - } + if (mc->soc->ops && mc->soc->ops->resume) + return mc->soc->ops->resume(mc); return 0; } static const struct dev_pm_ops tegra_mc_pm_ops = { - .suspend = tegra_mc_suspend, - .resume = tegra_mc_resume, + SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) }; static struct platform_driver tegra_mc_driver = { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 8e77567d1378..9d3fdb609d55 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -45,6 +45,17 @@ static void tegra186_mc_program_sid(struct tegra_mc *mc) } } +static int tegra186_mc_resume(struct tegra_mc *mc) +{ + tegra186_mc_program_sid(mc); + + return 0; +} + +static const struct tegra_mc_ops tegra186_mc_ops = { + .resume = tegra186_mc_resume, +}; + #if defined(CONFIG_ARCH_TEGRA_186_SOC) static const struct tegra_mc_client tegra186_mc_clients[] = { { @@ -701,6 +712,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { static const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, + .ops = &tegra186_mc_ops, }; #endif @@ -1909,6 +1921,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { static const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, + .ops = &tegra186_mc_ops, }; #endif @@ -1961,22 +1974,28 @@ static const struct of_device_id tegra186_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); -static int __maybe_unused tegra186_mc_suspend(struct device *dev) +static int __maybe_unused tegra_mc_suspend(struct device *dev) { + struct tegra_mc *mc = dev_get_drvdata(dev); + + if (mc->soc->ops && mc->soc->ops->suspend) + return mc->soc->ops->suspend(mc); + return 0; } -static int __maybe_unused tegra186_mc_resume(struct device *dev) +static int __maybe_unused tegra_mc_resume(struct device *dev) { struct tegra_mc *mc = dev_get_drvdata(dev); - tegra186_mc_program_sid(mc); + if (mc->soc->ops && mc->soc->ops->resume) + return mc->soc->ops->resume(mc); return 0; } static const struct dev_pm_ops tegra186_mc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume) + SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) }; static struct platform_driver tegra186_mc_driver = { diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 3b7b93b96480..a3335ad20f4d 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -687,8 +687,36 @@ static int tegra20_mc_init(struct tegra_mc *mc) return 0; } +static int tegra20_mc_suspend(struct tegra_mc *mc) +{ + int err; + + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { + err = tegra_gart_suspend(mc->gart); + if (err < 0) + return err; + } + + return 0; +} + +static int tegra20_mc_resume(struct tegra_mc *mc) +{ + int err; + + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { + err = tegra_gart_resume(mc->gart); + if (err < 0) + return err; + } + + return 0; +} + static const struct tegra_mc_ops tegra20_mc_ops = { .init = tegra20_mc_init, + .suspend = tegra20_mc_suspend, + .resume = tegra20_mc_resume, }; const struct tegra_mc_soc tegra20_mc_soc = { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 4f88da907a02..7c49f75087c3 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -171,6 +171,8 @@ struct tegra_mc_icc_ops { struct tegra_mc_ops { int (*init)(struct tegra_mc *mc); + int (*suspend)(struct tegra_mc *mc); + int (*resume)(struct tegra_mc *mc); }; struct tegra_mc_soc { From patchwork Wed Jun 2 16:32:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98BD5C47083 for ; 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Wed, 02 Jun 2021 09:31:40 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id r4sm234717ejd.105.2021.06.02.09.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:39 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 05/12] memory: tegra: Make per-SoC setup more generic Date: Wed, 2 Jun 2021 18:32:55 +0200 Message-Id: <20210602163302.120041-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093142_012480_E2521A83 X-CRM114-Status: GOOD ( 21.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding The current per-SoC setup code runs at a fairly arbitrary point during probe, thereby making it less flexible for other SoC generations. Move the call around slightly (after only the very basic, common setup that applies to all SoC generations has been performed), which will allow it to be used for other implementations. Signed-off-by: Thierry Reding --- Changes in v2: - add kerneldoc comment to clarify when the per-SoC ->probe() is called - clarify this in the commit message as well drivers/memory/tegra/mc.c | 17 ++++++++--------- drivers/memory/tegra/tegra20.c | 4 ++-- include/soc/tegra/mc.h | 6 +++++- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a3b7ba33b7f9..ea2142ba720a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -784,6 +784,14 @@ static int tegra_mc_probe(struct platform_device *pdev) return PTR_ERR(mc->clk); } + mc->debugfs.root = debugfs_create_dir("mc", NULL); + + if (mc->soc->ops && mc->soc->ops->probe) { + err = mc->soc->ops->probe(mc); + if (err < 0) + return err; + } + #ifdef CONFIG_ARCH_TEGRA_2x_SOC if (mc->soc == &tegra20_mc_soc) { isr = tegra20_mc_irq; @@ -827,15 +835,6 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } - mc->debugfs.root = debugfs_create_dir("mc", NULL); - - if (mc->soc->ops && mc->soc->ops->init) { - err = mc->soc->ops->init(mc); - if (err < 0) - dev_err(&pdev->dev, "failed to initialize SoC driver: %d\n", - err); - } - err = tegra_mc_reset_setup(mc); if (err < 0) dev_err(&pdev->dev, "failed to register reset controller: %d\n", diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a3335ad20f4d..2c86c0d70d59 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -679,7 +679,7 @@ static int tegra20_mc_stats_show(struct seq_file *s, void *unused) return 0; } -static int tegra20_mc_init(struct tegra_mc *mc) +static int tegra20_mc_probe(struct tegra_mc *mc) { debugfs_create_devm_seqfile(mc->dev, "stats", mc->debugfs.root, tegra20_mc_stats_show); @@ -714,7 +714,7 @@ static int tegra20_mc_resume(struct tegra_mc *mc) } static const struct tegra_mc_ops tegra20_mc_ops = { - .init = tegra20_mc_init, + .probe = tegra20_mc_probe, .suspend = tegra20_mc_suspend, .resume = tegra20_mc_resume, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 7c49f75087c3..00d16c356db8 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -170,7 +170,11 @@ struct tegra_mc_icc_ops { }; struct tegra_mc_ops { - int (*init)(struct tegra_mc *mc); + /* + * @probe: Callback to set up SoC-specific bits of the memory controller. This is called + * after basic, common set up that is done by the SoC-agnostic bits. + */ + int (*probe)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); }; From patchwork Wed Jun 2 16:32:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BC6DC4708F for ; Wed, 2 Jun 2021 16:34:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18F866198C for ; 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Wed, 02 Jun 2021 09:31:41 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 06/12] memory: tegra: Extract setup code into callback Date: Wed, 2 Jun 2021 18:32:56 +0200 Message-Id: <20210602163302.120041-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093144_883133_B2568E92 X-CRM114-Status: GOOD ( 21.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Separate the setup code for Tegra30 and later into a ->setup() callback and set it for all applicable chips. Signed-off-by: Thierry Reding --- drivers/memory/tegra/mc.c | 127 ++++++++++++++++++-------------- drivers/memory/tegra/mc.h | 9 +++ drivers/memory/tegra/tegra114.c | 1 + drivers/memory/tegra/tegra124.c | 2 + drivers/memory/tegra/tegra210.c | 1 + drivers/memory/tegra/tegra30.c | 1 + 6 files changed, 84 insertions(+), 57 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ea2142ba720a..edb3c4a25365 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -299,38 +299,6 @@ static int tegra_mc_reset_setup(struct tegra_mc *mc) return 0; } -static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) -{ - unsigned long long tick; - unsigned int i; - u32 value; - - /* compute the number of MC clock cycles per tick */ - tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); - do_div(tick, NSEC_PER_SEC); - - value = mc_readl(mc, MC_EMEM_ARB_CFG); - value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; - value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); - mc_writel(mc, value, MC_EMEM_ARB_CFG); - - /* write latency allowance defaults */ - for (i = 0; i < mc->soc->num_clients; i++) { - const struct tegra_mc_client *client = &mc->soc->clients[i]; - u32 value; - - value = mc_readl(mc, client->regs.la.reg); - value &= ~(client->regs.la.mask << client->regs.la.shift); - value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; - mc_writel(mc, value, client->regs.la.reg); - } - - /* latch new values */ - mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); - - return 0; -} - int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) { unsigned int i; @@ -368,6 +336,43 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) } EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ + defined(CONFIG_ARCH_TEGRA_114_SOC) || \ + defined(CONFIG_ARCH_TEGRA_124_SOC) || \ + defined(CONFIG_ARCH_TEGRA_132_SOC) || \ + defined(CONFIG_ARCH_TEGRA_210_SOC) +static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) +{ + unsigned long long tick; + unsigned int i; + u32 value; + + /* compute the number of MC clock cycles per tick */ + tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); + do_div(tick, NSEC_PER_SEC); + + value = mc_readl(mc, MC_EMEM_ARB_CFG); + value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; + value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); + mc_writel(mc, value, MC_EMEM_ARB_CFG); + + /* write latency allowance defaults */ + for (i = 0; i < mc->soc->num_clients; i++) { + const struct tegra_mc_client *client = &mc->soc->clients[i]; + u32 value; + + value = mc_readl(mc, client->regs.la.reg); + value &= ~(client->regs.la.mask << client->regs.la.shift); + value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; + mc_writel(mc, value, client->regs.la.reg); + } + + /* latch new values */ + mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); + + return 0; +} + static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, struct device_node *node) @@ -459,6 +464,39 @@ static int tegra_mc_setup_timings(struct tegra_mc *mc) return 0; } +int tegra30_mc_probe(struct tegra_mc *mc) +{ + int err; + + mc->clk = devm_clk_get_optional(mc->dev, "mc"); + if (IS_ERR(mc->clk)) { + dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk)); + return PTR_ERR(mc->clk); + } + + /* ensure that debug features are disabled */ + mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); + + err = tegra_mc_setup_latency_allowance(mc); + if (err < 0) { + dev_err(mc->dev, "failed to setup latency allowance: %d\n", err); + return err; + } + + err = tegra_mc_setup_timings(mc); + if (err < 0) { + dev_err(mc->dev, "failed to setup timings: %d\n", err); + return err; + } + + return 0; +} + +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, +}; +#endif + static const char *const status_names[32] = { [ 1] = "External interrupt", [ 6] = "EMEM address decode error", @@ -777,13 +815,6 @@ static int tegra_mc_probe(struct platform_device *pdev) if (IS_ERR(mc->regs)) return PTR_ERR(mc->regs); - mc->clk = devm_clk_get(&pdev->dev, "mc"); - if (IS_ERR(mc->clk)) { - dev_err(&pdev->dev, "failed to get MC clock: %ld\n", - PTR_ERR(mc->clk)); - return PTR_ERR(mc->clk); - } - mc->debugfs.root = debugfs_create_dir("mc", NULL); if (mc->soc->ops && mc->soc->ops->probe) { @@ -798,25 +829,7 @@ static int tegra_mc_probe(struct platform_device *pdev) } else #endif { - /* ensure that debug features are disabled */ - mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); - - err = tegra_mc_setup_latency_allowance(mc); - if (err < 0) { - dev_err(&pdev->dev, - "failed to setup latency allowance: %d\n", - err); - return err; - } - isr = tegra_mc_irq; - - err = tegra_mc_setup_timings(mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to setup timings: %d\n", - err); - return err; - } } mc->irq = platform_get_irq(pdev, 0); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 1ee34f0da4f7..731896169cf3 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -129,6 +129,15 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ + defined(CONFIG_ARCH_TEGRA_114_SOC) || \ + defined(CONFIG_ARCH_TEGRA_124_SOC) || \ + defined(CONFIG_ARCH_TEGRA_132_SOC) || \ + defined(CONFIG_ARCH_TEGRA_210_SOC) +int tegra30_mc_probe(struct tegra_mc *mc); +extern const struct tegra_mc_ops tegra30_mc_ops; +#endif + /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are * chosen such that they don't conflict with the device-tree ICC node IDs. diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 1f2054d34bf5..41350570c815 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1113,4 +1113,5 @@ const struct tegra_mc_soc tegra114_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra114_mc_resets, .num_resets = ARRAY_SIZE(tegra114_mc_resets), + .ops = &tegra30_mc_ops, }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 8a8485ceb789..d780a84241fe 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1274,6 +1274,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), .icc_ops = &tegra124_mc_icc_ops, + .ops = &tegra30_mc_ops, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ @@ -1305,5 +1306,6 @@ const struct tegra_mc_soc tegra132_mc_soc = { .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), .icc_ops = &tegra124_mc_icc_ops, + .ops = &tegra30_mc_ops, }; #endif /* CONFIG_ARCH_TEGRA_132_SOC */ diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 08f3a08cd743..8ab6498dbe7d 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1286,4 +1286,5 @@ const struct tegra_mc_soc tegra210_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra210_mc_resets, .num_resets = ARRAY_SIZE(tegra210_mc_resets), + .ops = &tegra30_mc_ops, }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 1922ab64e686..84316357513d 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1399,4 +1399,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .resets = tegra30_mc_resets, .num_resets = ARRAY_SIZE(tegra30_mc_resets), .icc_ops = &tegra30_mc_icc_ops, + .ops = &tegra30_mc_ops, }; From patchwork Wed Jun 2 16:32:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C938CC47083 for ; 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Wed, 02 Jun 2021 09:31:45 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id y25sm247876edt.17.2021.06.02.09.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:44 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 07/12] memory: tegra: Parameterize interrupt handler Date: Wed, 2 Jun 2021 18:32:57 +0200 Message-Id: <20210602163302.120041-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093146_453697_09855199 X-CRM114-Status: GOOD ( 23.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Tegra20 requires a slightly different interrupt handler than Tegra30 and later, so parameterize the handler, so that each SoC implementation can provide its own. Signed-off-by: Thierry Reding --- Changes in v3: - make tegra30_mc_handle_irq() static Changes in v2: - use tegra_mc_ prefix for status and error names arrays - keep IRQ handling mandatory in this patch drivers/memory/tegra/mc.c | 136 +++++++-------------------------- drivers/memory/tegra/mc.h | 3 + drivers/memory/tegra/tegra20.c | 74 ++++++++++++++++++ include/soc/tegra/mc.h | 2 + 4 files changed, 106 insertions(+), 109 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index edb3c4a25365..e6c928633b12 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -492,32 +492,7 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } -const struct tegra_mc_ops tegra30_mc_ops = { - .probe = tegra30_mc_probe, -}; -#endif - -static const char *const status_names[32] = { - [ 1] = "External interrupt", - [ 6] = "EMEM address decode error", - [ 7] = "GART page fault", - [ 8] = "Security violation", - [ 9] = "EMEM arbitration error", - [10] = "Page fault", - [11] = "Invalid APB ASID update", - [12] = "VPR violation", - [13] = "Secure carveout violation", - [16] = "MTS carveout violation", -}; - -static const char *const error_names[8] = { - [2] = "EMEM decode error", - [3] = "TrustZone violation", - [4] = "Carveout violation", - [6] = "SMMU translation error", -}; - -static irqreturn_t tegra_mc_irq(int irq, void *data) +static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) { struct tegra_mc *mc = data; unsigned long status; @@ -529,7 +504,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) return IRQ_NONE; for_each_set_bit(bit, &status, 32) { - const char *error = status_names[bit] ?: "unknown"; + const char *error = tegra_mc_status_names[bit] ?: "unknown"; const char *client = "unknown", *desc; const char *direction, *secure; phys_addr_t addr = 0; @@ -569,7 +544,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) type = (value & MC_ERR_STATUS_TYPE_MASK) >> MC_ERR_STATUS_TYPE_SHIFT; - desc = error_names[type]; + desc = tegra_mc_error_names[type]; switch (value & MC_ERR_STATUS_TYPE_MASK) { case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: @@ -614,78 +589,31 @@ static irqreturn_t tegra_mc_irq(int irq, void *data) return IRQ_HANDLED; } -static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) -{ - struct tegra_mc *mc = data; - unsigned long status; - unsigned int bit; - - /* mask all interrupts to avoid flooding */ - status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; - if (!status) - return IRQ_NONE; - - for_each_set_bit(bit, &status, 32) { - const char *direction = "read", *secure = ""; - const char *error = status_names[bit]; - const char *client, *desc; - phys_addr_t addr; - u32 value, reg; - u8 id, type; - - switch (BIT(bit)) { - case MC_INT_DECERR_EMEM: - reg = MC_DECERR_EMEM_OTHERS_STATUS; - value = mc_readl(mc, reg); - - id = value & mc->soc->client_id_mask; - desc = error_names[2]; - - if (value & BIT(31)) - direction = "write"; - break; - - case MC_INT_INVALID_GART_PAGE: - reg = MC_GART_ERROR_REQ; - value = mc_readl(mc, reg); - - id = (value >> 1) & mc->soc->client_id_mask; - desc = error_names[2]; - - if (value & BIT(0)) - direction = "write"; - break; - - case MC_INT_SECURITY_VIOLATION: - reg = MC_SECURITY_VIOLATION_STATUS; - value = mc_readl(mc, reg); - - id = value & mc->soc->client_id_mask; - type = (value & BIT(30)) ? 4 : 3; - desc = error_names[type]; - secure = "secure "; - - if (value & BIT(31)) - direction = "write"; - break; - - default: - continue; - } - - client = mc->soc->clients[id].name; - addr = mc_readl(mc, reg + sizeof(u32)); - - dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", - client, secure, direction, &addr, error, - desc); - } +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, + .handle_irq = tegra30_mc_handle_irq, +}; +#endif - /* clear interrupts */ - mc_writel(mc, status, MC_INTSTATUS); +const char *const tegra_mc_status_names[32] = { + [ 1] = "External interrupt", + [ 6] = "EMEM address decode error", + [ 7] = "GART page fault", + [ 8] = "Security violation", + [ 9] = "EMEM arbitration error", + [10] = "Page fault", + [11] = "Invalid APB ASID update", + [12] = "VPR violation", + [13] = "Secure carveout violation", + [16] = "MTS carveout violation", +}; - return IRQ_HANDLED; -} +const char *const tegra_mc_error_names[8] = { + [2] = "EMEM decode error", + [3] = "TrustZone violation", + [4] = "Carveout violation", + [6] = "SMMU translation error", +}; /* * Memory Controller (MC) has few Memory Clients that are issuing memory @@ -786,7 +714,6 @@ static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; struct tegra_mc *mc; - void *isr; u64 mask; int err; @@ -823,15 +750,6 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - if (mc->soc == &tegra20_mc_soc) { - isr = tegra20_mc_irq; - } else -#endif - { - isr = tegra_mc_irq; - } - mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) return mc->irq; @@ -840,7 +758,7 @@ static int tegra_mc_probe(struct platform_device *pdev) mc_writel(mc, mc->soc->intmask, MC_INTMASK); - err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, + err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, dev_name(&pdev->dev), mc); if (err < 0) { dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 731896169cf3..83c605e42e9a 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -138,6 +138,9 @@ int tegra30_mc_probe(struct tegra_mc *mc); extern const struct tegra_mc_ops tegra30_mc_ops; #endif +extern const char * const tegra_mc_status_names[32]; +extern const char * const tegra_mc_error_names[8]; + /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are * chosen such that they don't conflict with the device-tree ICC node IDs. diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 2c86c0d70d59..fcd7738fcb53 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -713,10 +713,84 @@ static int tegra20_mc_resume(struct tegra_mc *mc) return 0; } +static irqreturn_t tegra20_mc_handle_irq(int irq, void *data) +{ + struct tegra_mc *mc = data; + unsigned long status; + unsigned int bit; + + /* mask all interrupts to avoid flooding */ + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (!status) + return IRQ_NONE; + + for_each_set_bit(bit, &status, 32) { + const char *error = tegra_mc_status_names[bit]; + const char *direction = "read", *secure = ""; + const char *client, *desc; + phys_addr_t addr; + u32 value, reg; + u8 id, type; + + switch (BIT(bit)) { + case MC_INT_DECERR_EMEM: + reg = MC_DECERR_EMEM_OTHERS_STATUS; + value = mc_readl(mc, reg); + + id = value & mc->soc->client_id_mask; + desc = tegra_mc_error_names[2]; + + if (value & BIT(31)) + direction = "write"; + break; + + case MC_INT_INVALID_GART_PAGE: + reg = MC_GART_ERROR_REQ; + value = mc_readl(mc, reg); + + id = (value >> 1) & mc->soc->client_id_mask; + desc = tegra_mc_error_names[2]; + + if (value & BIT(0)) + direction = "write"; + break; + + case MC_INT_SECURITY_VIOLATION: + reg = MC_SECURITY_VIOLATION_STATUS; + value = mc_readl(mc, reg); + + id = value & mc->soc->client_id_mask; + type = (value & BIT(30)) ? 4 : 3; + desc = tegra_mc_error_names[type]; + secure = "secure "; + + if (value & BIT(31)) + direction = "write"; + break; + + default: + continue; + } + + client = mc->soc->clients[id].name; + addr = mc_readl(mc, reg + sizeof(u32)); + + dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", + client, secure, direction, &addr, error, + desc); + } + + /* clear interrupts */ + mc_writel(mc, status, MC_INTSTATUS); + + return IRQ_HANDLED; +} + static const struct tegra_mc_ops tegra20_mc_ops = { .probe = tegra20_mc_probe, .suspend = tegra20_mc_suspend, .resume = tegra20_mc_resume, + .handle_irq = tegra20_mc_handle_irq, }; const struct tegra_mc_soc tegra20_mc_soc = { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 00d16c356db8..87668ebab2a1 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -177,6 +178,7 @@ struct tegra_mc_ops { int (*probe)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); + irqreturn_t (*handle_irq)(int irq, void *data); }; struct tegra_mc_soc { From patchwork Wed Jun 2 16:32:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78A59C47083 for ; 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Wed, 02 Jun 2021 09:31:47 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id d24sm232534edr.95.2021.06.02.09.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:46 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 08/12] memory: tegra: Make IRQ support opitonal Date: Wed, 2 Jun 2021 18:32:58 +0200 Message-Id: <20210602163302.120041-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093248_776432_28C0F496 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Make IRQ support optional to help unify the Tegra186 memory controller driver with this one. Signed-off-by: Thierry Reding --- Changes in v2: - new patch drivers/memory/tegra/mc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index e6c928633b12..68c6797f2707 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -750,20 +750,22 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } - mc->irq = platform_get_irq(pdev, 0); - if (mc->irq < 0) - return mc->irq; + if (mc->soc->ops && mc->soc->ops->handle_irq) { + mc->irq = platform_get_irq(pdev, 0); + if (mc->irq < 0) + return mc->irq; - WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); + WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); - mc_writel(mc, mc->soc->intmask, MC_INTMASK); + mc_writel(mc, mc->soc->intmask, MC_INTMASK); - err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, - dev_name(&pdev->dev), mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, - err); - return err; + err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, + dev_name(&pdev->dev), mc); + if (err < 0) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, + err); + return err; + } } err = tegra_mc_reset_setup(mc); From patchwork Wed Jun 2 16:32:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CC32C47083 for ; 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Wed, 02 Jun 2021 09:31:50 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id br21sm243388ejb.124.2021.06.02.09.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:48 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 09/12] memory: tegra: Only initialize reset controller if available Date: Wed, 2 Jun 2021 18:32:59 +0200 Message-Id: <20210602163302.120041-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093251_346341_1A4425EC X-CRM114-Status: GOOD ( 14.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding The memory controller hot resets are implemented in the BPMP on Tegra186 and later, so there's no need to provide an implementation via the memory controller driver. Conditionally register the reset controller only if needed. Signed-off-by: Thierry Reding --- drivers/memory/tegra/mc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 68c6797f2707..4aa17bdd6392 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -768,10 +768,11 @@ static int tegra_mc_probe(struct platform_device *pdev) } } - err = tegra_mc_reset_setup(mc); - if (err < 0) - dev_err(&pdev->dev, "failed to register reset controller: %d\n", - err); + if (mc->soc->reset_ops) { + err = tegra_mc_reset_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + } err = tegra_mc_interconnect_setup(mc); if (err < 0) From patchwork Wed Jun 2 16:33:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD95FC47083 for ; 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Wed, 02 Jun 2021 09:31:52 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id t18sm244943edw.47.2021.06.02.09.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 10/12] memory: tegra: Unify drivers Date: Wed, 2 Jun 2021 18:33:00 +0200 Message-Id: <20210602163302.120041-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093153_865320_1417DA81 X-CRM114-Status: GOOD ( 25.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding The Tegra210 (and earlier) driver now supports all the functionality that the Tegra186 (and later) driver does, so they can be unified. Note that previously the Tegra186 (and later) driver could be unloaded, even if that was perhaps not very useful. Older chips don't support that yet, but once they do this code can be reenabled. Signed-off-by: Thierry Reding --- Changes in v2: - remove commented-out code for partial driver removal support drivers/memory/tegra/Makefile | 6 +- drivers/memory/tegra/mc.c | 8 ++- drivers/memory/tegra/mc.h | 8 +++ drivers/memory/tegra/tegra186.c | 117 +++++++------------------------- include/soc/tegra/mc.h | 1 + 5 files changed, 45 insertions(+), 95 deletions(-) diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 6c1a2ecc6628..1af0fefacdda 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -7,6 +7,8 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o +tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o +tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o @@ -15,7 +17,7 @@ obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o -obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o -obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 4aa17bdd6392..11b83de9361c 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -39,7 +39,13 @@ static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_210_SOC { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, #endif - { } +#ifdef CONFIG_ARCH_TEGRA_186_SOC + { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#endif +#ifdef CONFIG_ARCH_TEGRA_194_SOC + { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, +#endif + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 83c605e42e9a..24f95e06d18a 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -129,6 +129,14 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +#ifdef CONFIG_ARCH_TEGRA_186_SOC +extern const struct tegra_mc_soc tegra186_mc_soc; +#endif + +#ifdef CONFIG_ARCH_TEGRA_194_SOC +extern const struct tegra_mc_soc tegra194_mc_soc; +#endif + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 9d3fdb609d55..20efbbea587b 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. */ #include @@ -45,6 +45,24 @@ static void tegra186_mc_program_sid(struct tegra_mc *mc) } } +static int tegra186_mc_probe(struct tegra_mc *mc) +{ + int err; + + err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); + if (err < 0) + return err; + + tegra186_mc_program_sid(mc); + + return 0; +} + +static void tegra186_mc_remove(struct tegra_mc *mc) +{ + of_platform_depopulate(mc->dev); +} + static int tegra186_mc_resume(struct tegra_mc *mc) { tegra186_mc_program_sid(mc); @@ -53,6 +71,8 @@ static int tegra186_mc_resume(struct tegra_mc *mc) } static const struct tegra_mc_ops tegra186_mc_ops = { + .probe = tegra186_mc_probe, + .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, }; @@ -709,9 +729,10 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }; -static const struct tegra_mc_soc tegra186_mc_soc = { +const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, + .num_address_bits = 40, .ops = &tegra186_mc_ops, }; #endif @@ -1918,98 +1939,10 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }; -static const struct tegra_mc_soc tegra194_mc_soc = { +const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, + .num_address_bits = 40, .ops = &tegra186_mc_ops, }; #endif - -static int tegra186_mc_probe(struct platform_device *pdev) -{ - struct resource *res; - struct tegra_mc *mc; - int err; - - mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); - if (!mc) - return -ENOMEM; - - mc->soc = of_device_get_match_data(&pdev->dev); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mc->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mc->regs)) - return PTR_ERR(mc->regs); - - mc->dev = &pdev->dev; - - err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); - if (err < 0) - return err; - - platform_set_drvdata(pdev, mc); - tegra186_mc_program_sid(mc); - - return 0; -} - -static int tegra186_mc_remove(struct platform_device *pdev) -{ - struct tegra_mc *mc = platform_get_drvdata(pdev); - - of_platform_depopulate(mc->dev); - - return 0; -} - -static const struct of_device_id tegra186_mc_of_match[] = { -#if defined(CONFIG_ARCH_TEGRA_186_SOC) - { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, -#endif -#if defined(CONFIG_ARCH_TEGRA_194_SOC) - { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, -#endif - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); - -static int __maybe_unused tegra_mc_suspend(struct device *dev) -{ - struct tegra_mc *mc = dev_get_drvdata(dev); - - if (mc->soc->ops && mc->soc->ops->suspend) - return mc->soc->ops->suspend(mc); - - return 0; -} - -static int __maybe_unused tegra_mc_resume(struct device *dev) -{ - struct tegra_mc *mc = dev_get_drvdata(dev); - - if (mc->soc->ops && mc->soc->ops->resume) - return mc->soc->ops->resume(mc); - - return 0; -} - -static const struct dev_pm_ops tegra186_mc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) -}; - -static struct platform_driver tegra186_mc_driver = { - .driver = { - .name = "tegra186-mc", - .of_match_table = tegra186_mc_of_match, - .pm = &tegra186_mc_pm_ops, - .suppress_bind_attrs = true, - }, - .probe = tegra186_mc_probe, - .remove = tegra186_mc_remove, -}; -module_platform_driver(tegra186_mc_driver); - -MODULE_AUTHOR("Thierry Reding "); -MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver"); -MODULE_LICENSE("GPL v2"); diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 87668ebab2a1..1bd5aed81868 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -176,6 +176,7 @@ struct tegra_mc_ops { * after basic, common set up that is done by the SoC-agnostic bits. */ int (*probe)(struct tegra_mc *mc); + void (*remove)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); From patchwork Wed Jun 2 16:33:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5133AC47083 for ; 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Wed, 02 Jun 2021 09:31:54 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id gb26sm268187ejc.25.2021.06.02.09.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:53 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 11/12] memory: tegra: Add memory client IDs to tables Date: Wed, 2 Jun 2021 18:33:01 +0200 Message-Id: <20210602163302.120041-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093156_029695_E8EEB492 X-CRM114-Status: GOOD ( 12.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding The memory client IDs will subsequently be used to program override SIDs for the given clients depending on the device tree configuration. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 205 ++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 20efbbea587b..2f6ef46c33a4 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -79,6 +79,7 @@ static const struct tegra_mc_ops tegra186_mc_ops = { #if defined(CONFIG_ARCH_TEGRA_186_SOC) static const struct tegra_mc_client tegra186_mc_clients[] = { { + .id = TEGRA186_MEMORY_CLIENT_PTCR, .name = "ptcr", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { @@ -88,6 +89,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AFIR, .name = "afir", .sid = TEGRA186_SID_AFI, .regs = { @@ -97,6 +99,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_HDAR, .name = "hdar", .sid = TEGRA186_SID_HDA, .regs = { @@ -106,6 +109,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, .name = "host1xdmar", .sid = TEGRA186_SID_HOST1X, .regs = { @@ -115,6 +119,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVENCSRD, .name = "nvencsrd", .sid = TEGRA186_SID_NVENC, .regs = { @@ -124,6 +129,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SATAR, .name = "satar", .sid = TEGRA186_SID_SATA, .regs = { @@ -133,6 +139,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_MPCORER, .name = "mpcorer", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { @@ -142,6 +149,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVENCSWR, .name = "nvencswr", .sid = TEGRA186_SID_NVENC, .regs = { @@ -151,6 +159,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AFIW, .name = "afiw", .sid = TEGRA186_SID_AFI, .regs = { @@ -160,6 +169,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_HDAW, .name = "hdaw", .sid = TEGRA186_SID_HDA, .regs = { @@ -169,6 +179,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_MPCOREW, .name = "mpcorew", .sid = TEGRA186_SID_PASSTHROUGH, .regs = { @@ -178,6 +189,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SATAW, .name = "sataw", .sid = TEGRA186_SID_SATA, .regs = { @@ -187,6 +199,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_ISPRA, .name = "ispra", .sid = TEGRA186_SID_ISP, .regs = { @@ -196,6 +209,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_ISPWA, .name = "ispwa", .sid = TEGRA186_SID_ISP, .regs = { @@ -205,6 +219,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_ISPWB, .name = "ispwb", .sid = TEGRA186_SID_ISP, .regs = { @@ -214,6 +229,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, .name = "xusb_hostr", .sid = TEGRA186_SID_XUSB_HOST, .regs = { @@ -223,6 +239,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, .name = "xusb_hostw", .sid = TEGRA186_SID_XUSB_HOST, .regs = { @@ -232,6 +249,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, .name = "xusb_devr", .sid = TEGRA186_SID_XUSB_DEV, .regs = { @@ -241,6 +259,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, .name = "xusb_devw", .sid = TEGRA186_SID_XUSB_DEV, .regs = { @@ -250,6 +269,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_TSECSRD, .name = "tsecsrd", .sid = TEGRA186_SID_TSEC, .regs = { @@ -259,6 +279,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_TSECSWR, .name = "tsecswr", .sid = TEGRA186_SID_TSEC, .regs = { @@ -268,6 +289,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_GPUSRD, .name = "gpusrd", .sid = TEGRA186_SID_GPU, .regs = { @@ -277,6 +299,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_GPUSWR, .name = "gpuswr", .sid = TEGRA186_SID_GPU, .regs = { @@ -286,6 +309,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCRA, .name = "sdmmcra", .sid = TEGRA186_SID_SDMMC1, .regs = { @@ -295,6 +319,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, .name = "sdmmcraa", .sid = TEGRA186_SID_SDMMC2, .regs = { @@ -304,6 +329,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCR, .name = "sdmmcr", .sid = TEGRA186_SID_SDMMC3, .regs = { @@ -313,6 +339,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", .sid = TEGRA186_SID_SDMMC4, .regs = { @@ -322,6 +349,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCWA, .name = "sdmmcwa", .sid = TEGRA186_SID_SDMMC1, .regs = { @@ -331,6 +359,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, .name = "sdmmcwaa", .sid = TEGRA186_SID_SDMMC2, .regs = { @@ -340,6 +369,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCW, .name = "sdmmcw", .sid = TEGRA186_SID_SDMMC3, .regs = { @@ -349,6 +379,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", .sid = TEGRA186_SID_SDMMC4, .regs = { @@ -358,6 +389,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_VICSRD, .name = "vicsrd", .sid = TEGRA186_SID_VIC, .regs = { @@ -367,6 +399,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_VICSWR, .name = "vicswr", .sid = TEGRA186_SID_VIC, .regs = { @@ -376,6 +409,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_VIW, .name = "viw", .sid = TEGRA186_SID_VI, .regs = { @@ -385,6 +419,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVDECSRD, .name = "nvdecsrd", .sid = TEGRA186_SID_NVDEC, .regs = { @@ -394,6 +429,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVDECSWR, .name = "nvdecswr", .sid = TEGRA186_SID_NVDEC, .regs = { @@ -403,6 +439,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_APER, .name = "aper", .sid = TEGRA186_SID_APE, .regs = { @@ -412,6 +449,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_APEW, .name = "apew", .sid = TEGRA186_SID_APE, .regs = { @@ -421,6 +459,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, .name = "nvjpgsrd", .sid = TEGRA186_SID_NVJPG, .regs = { @@ -430,6 +469,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, .name = "nvjpgswr", .sid = TEGRA186_SID_NVJPG, .regs = { @@ -439,6 +479,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SESRD, .name = "sesrd", .sid = TEGRA186_SID_SE, .regs = { @@ -448,6 +489,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SESWR, .name = "seswr", .sid = TEGRA186_SID_SE, .regs = { @@ -457,6 +499,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_ETRR, .name = "etrr", .sid = TEGRA186_SID_ETR, .regs = { @@ -466,6 +509,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_ETRW, .name = "etrw", .sid = TEGRA186_SID_ETR, .regs = { @@ -475,6 +519,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_TSECSRDB, .name = "tsecsrdb", .sid = TEGRA186_SID_TSECB, .regs = { @@ -484,6 +529,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_TSECSWRB, .name = "tsecswrb", .sid = TEGRA186_SID_TSECB, .regs = { @@ -493,6 +539,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_GPUSRD2, .name = "gpusrd2", .sid = TEGRA186_SID_GPU, .regs = { @@ -502,6 +549,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_GPUSWR2, .name = "gpuswr2", .sid = TEGRA186_SID_GPU, .regs = { @@ -511,6 +559,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AXISR, .name = "axisr", .sid = TEGRA186_SID_GPCDMA_0, .regs = { @@ -520,6 +569,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AXISW, .name = "axisw", .sid = TEGRA186_SID_GPCDMA_0, .regs = { @@ -529,6 +579,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_EQOSR, .name = "eqosr", .sid = TEGRA186_SID_EQOS, .regs = { @@ -538,6 +589,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_EQOSW, .name = "eqosw", .sid = TEGRA186_SID_EQOS, .regs = { @@ -547,6 +599,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_UFSHCR, .name = "ufshcr", .sid = TEGRA186_SID_UFSHC, .regs = { @@ -556,6 +609,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_UFSHCW, .name = "ufshcw", .sid = TEGRA186_SID_UFSHC, .regs = { @@ -565,6 +619,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", .sid = TEGRA186_SID_NVDISPLAY, .regs = { @@ -574,6 +629,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_BPMPR, .name = "bpmpr", .sid = TEGRA186_SID_BPMP, .regs = { @@ -583,6 +639,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_BPMPW, .name = "bpmpw", .sid = TEGRA186_SID_BPMP, .regs = { @@ -592,6 +649,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, .name = "bpmpdmar", .sid = TEGRA186_SID_BPMP, .regs = { @@ -601,6 +659,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, .name = "bpmpdmaw", .sid = TEGRA186_SID_BPMP, .regs = { @@ -610,6 +669,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AONR, .name = "aonr", .sid = TEGRA186_SID_AON, .regs = { @@ -619,6 +679,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AONW, .name = "aonw", .sid = TEGRA186_SID_AON, .regs = { @@ -628,6 +689,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AONDMAR, .name = "aondmar", .sid = TEGRA186_SID_AON, .regs = { @@ -637,6 +699,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_AONDMAW, .name = "aondmaw", .sid = TEGRA186_SID_AON, .regs = { @@ -646,6 +709,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SCER, .name = "scer", .sid = TEGRA186_SID_SCE, .regs = { @@ -655,6 +719,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SCEW, .name = "scew", .sid = TEGRA186_SID_SCE, .regs = { @@ -664,6 +729,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SCEDMAR, .name = "scedmar", .sid = TEGRA186_SID_SCE, .regs = { @@ -673,6 +739,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_SCEDMAW, .name = "scedmaw", .sid = TEGRA186_SID_SCE, .regs = { @@ -682,6 +749,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_APEDMAR, .name = "apedmar", .sid = TEGRA186_SID_APE, .regs = { @@ -691,6 +759,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_APEDMAW, .name = "apedmaw", .sid = TEGRA186_SID_APE, .regs = { @@ -700,6 +769,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, .name = "nvdisplayr1", .sid = TEGRA186_SID_NVDISPLAY, .regs = { @@ -709,6 +779,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_VICSRD1, .name = "vicsrd1", .sid = TEGRA186_SID_VIC, .regs = { @@ -718,6 +789,7 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { }, }, }, { + .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, .name = "nvdecsrd1", .sid = TEGRA186_SID_NVDEC, .regs = { @@ -740,6 +812,7 @@ const struct tegra_mc_soc tegra186_mc_soc = { #if defined(CONFIG_ARCH_TEGRA_194_SOC) static const struct tegra_mc_client tegra194_mc_clients[] = { { + .id = TEGRA194_MEMORY_CLIENT_PTCR, .name = "ptcr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -749,6 +822,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU7R, .name = "miu7r", .sid = TEGRA194_SID_MIU, .regs = { @@ -758,6 +832,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU7W, .name = "miu7w", .sid = TEGRA194_SID_MIU, .regs = { @@ -767,6 +842,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_HDAR, .name = "hdar", .sid = TEGRA194_SID_HDA, .regs = { @@ -776,6 +852,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR, .name = "host1xdmar", .sid = TEGRA194_SID_HOST1X, .regs = { @@ -785,6 +862,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD, .name = "nvencsrd", .sid = TEGRA194_SID_NVENC, .regs = { @@ -794,6 +872,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SATAR, .name = "satar", .sid = TEGRA194_SID_SATA, .regs = { @@ -803,6 +882,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MPCORER, .name = "mpcorer", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -812,6 +892,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSWR, .name = "nvencswr", .sid = TEGRA194_SID_NVENC, .regs = { @@ -821,6 +902,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_HDAW, .name = "hdaw", .sid = TEGRA194_SID_HDA, .regs = { @@ -830,6 +912,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MPCOREW, .name = "mpcorew", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -839,6 +922,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SATAW, .name = "sataw", .sid = TEGRA194_SID_SATA, .regs = { @@ -848,6 +932,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPRA, .name = "ispra", .sid = TEGRA194_SID_ISP, .regs = { @@ -857,6 +942,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPFALR, .name = "ispfalr", .sid = TEGRA194_SID_ISP_FALCON, .regs = { @@ -866,6 +952,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPWA, .name = "ispwa", .sid = TEGRA194_SID_ISP, .regs = { @@ -875,6 +962,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPWB, .name = "ispwb", .sid = TEGRA194_SID_ISP, .regs = { @@ -884,6 +972,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR, .name = "xusb_hostr", .sid = TEGRA194_SID_XUSB_HOST, .regs = { @@ -893,6 +982,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW, .name = "xusb_hostw", .sid = TEGRA194_SID_XUSB_HOST, .regs = { @@ -902,6 +992,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR, .name = "xusb_devr", .sid = TEGRA194_SID_XUSB_DEV, .regs = { @@ -911,6 +1002,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW, .name = "xusb_devw", .sid = TEGRA194_SID_XUSB_DEV, .regs = { @@ -920,6 +1012,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCRA, .name = "sdmmcra", .sid = TEGRA194_SID_SDMMC1, .regs = { @@ -929,6 +1022,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCR, .name = "sdmmcr", .sid = TEGRA194_SID_SDMMC3, .regs = { @@ -938,6 +1032,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", .sid = TEGRA194_SID_SDMMC4, .regs = { @@ -947,6 +1042,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCWA, .name = "sdmmcwa", .sid = TEGRA194_SID_SDMMC1, .regs = { @@ -956,6 +1052,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCW, .name = "sdmmcw", .sid = TEGRA194_SID_SDMMC3, .regs = { @@ -965,6 +1062,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", .sid = TEGRA194_SID_SDMMC4, .regs = { @@ -974,6 +1072,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VICSRD, .name = "vicsrd", .sid = TEGRA194_SID_VIC, .regs = { @@ -983,6 +1082,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VICSWR, .name = "vicswr", .sid = TEGRA194_SID_VIC, .regs = { @@ -992,6 +1092,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VIW, .name = "viw", .sid = TEGRA194_SID_VI, .regs = { @@ -1001,6 +1102,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD, .name = "nvdecsrd", .sid = TEGRA194_SID_NVDEC, .regs = { @@ -1010,6 +1112,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSWR, .name = "nvdecswr", .sid = TEGRA194_SID_NVDEC, .regs = { @@ -1019,6 +1122,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_APER, .name = "aper", .sid = TEGRA194_SID_APE, .regs = { @@ -1028,6 +1132,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_APEW, .name = "apew", .sid = TEGRA194_SID_APE, .regs = { @@ -1037,6 +1142,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD, .name = "nvjpgsrd", .sid = TEGRA194_SID_NVJPG, .regs = { @@ -1046,6 +1152,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR, .name = "nvjpgswr", .sid = TEGRA194_SID_NVJPG, .regs = { @@ -1056,6 +1163,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, { .name = "axiapr", + .id = TEGRA194_MEMORY_CLIENT_AXIAPR, .sid = TEGRA194_SID_PASSTHROUGH, .regs = { .sid = { @@ -1064,6 +1172,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AXIAPW, .name = "axiapw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -1073,6 +1182,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ETRR, .name = "etrr", .sid = TEGRA194_SID_ETR, .regs = { @@ -1082,6 +1192,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ETRW, .name = "etrw", .sid = TEGRA194_SID_ETR, .regs = { @@ -1091,6 +1202,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AXISR, .name = "axisr", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -1100,6 +1212,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AXISW, .name = "axisw", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -1109,6 +1222,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_EQOSR, .name = "eqosr", .sid = TEGRA194_SID_EQOS, .regs = { @@ -1119,6 +1233,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, { .name = "eqosw", + .id = TEGRA194_MEMORY_CLIENT_EQOSW, .sid = TEGRA194_SID_EQOS, .regs = { .sid = { @@ -1127,6 +1242,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_UFSHCR, .name = "ufshcr", .sid = TEGRA194_SID_UFSHC, .regs = { @@ -1136,6 +1252,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_UFSHCW, .name = "ufshcw", .sid = TEGRA194_SID_UFSHC, .regs = { @@ -1145,6 +1262,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", .sid = TEGRA194_SID_NVDISPLAY, .regs = { @@ -1154,6 +1272,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPR, .name = "bpmpr", .sid = TEGRA194_SID_BPMP, .regs = { @@ -1163,6 +1282,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPW, .name = "bpmpw", .sid = TEGRA194_SID_BPMP, .regs = { @@ -1172,6 +1292,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR, .name = "bpmpdmar", .sid = TEGRA194_SID_BPMP, .regs = { @@ -1181,6 +1302,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW, .name = "bpmpdmaw", .sid = TEGRA194_SID_BPMP, .regs = { @@ -1190,6 +1312,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AONR, .name = "aonr", .sid = TEGRA194_SID_AON, .regs = { @@ -1199,6 +1322,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AONW, .name = "aonw", .sid = TEGRA194_SID_AON, .regs = { @@ -1208,6 +1332,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AONDMAR, .name = "aondmar", .sid = TEGRA194_SID_AON, .regs = { @@ -1217,6 +1342,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_AONDMAW, .name = "aondmaw", .sid = TEGRA194_SID_AON, .regs = { @@ -1226,6 +1352,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SCER, .name = "scer", .sid = TEGRA194_SID_SCE, .regs = { @@ -1235,6 +1362,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SCEW, .name = "scew", .sid = TEGRA194_SID_SCE, .regs = { @@ -1244,6 +1372,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SCEDMAR, .name = "scedmar", .sid = TEGRA194_SID_SCE, .regs = { @@ -1253,6 +1382,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_SCEDMAW, .name = "scedmaw", .sid = TEGRA194_SID_SCE, .regs = { @@ -1262,6 +1392,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_APEDMAR, .name = "apedmar", .sid = TEGRA194_SID_APE, .regs = { @@ -1271,6 +1402,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_APEDMAW, .name = "apedmaw", .sid = TEGRA194_SID_APE, .regs = { @@ -1280,6 +1412,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1, .name = "nvdisplayr1", .sid = TEGRA194_SID_NVDISPLAY, .regs = { @@ -1289,6 +1422,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VICSRD1, .name = "vicsrd1", .sid = TEGRA194_SID_VIC, .regs = { @@ -1298,6 +1432,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1, .name = "nvdecsrd1", .sid = TEGRA194_SID_NVDEC, .regs = { @@ -1307,6 +1442,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU0R, .name = "miu0r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1317,6 +1453,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, { .name = "miu0w", + .id = TEGRA194_MEMORY_CLIENT_MIU0W, .sid = TEGRA194_SID_MIU, .regs = { .sid = { @@ -1325,6 +1462,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU1R, .name = "miu1r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1334,6 +1472,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU1W, .name = "miu1w", .sid = TEGRA194_SID_MIU, .regs = { @@ -1343,6 +1482,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU2R, .name = "miu2r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1352,6 +1492,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU2W, .name = "miu2w", .sid = TEGRA194_SID_MIU, .regs = { @@ -1361,6 +1502,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU3R, .name = "miu3r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1370,6 +1512,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU3W, .name = "miu3w", .sid = TEGRA194_SID_MIU, .regs = { @@ -1379,6 +1522,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU4R, .name = "miu4r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1388,6 +1532,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU4W, .name = "miu4w", .sid = TEGRA194_SID_MIU, .regs = { @@ -1397,6 +1542,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DPMUR, .name = "dpmur", .sid = TEGRA194_SID_PASSTHROUGH, .regs = { @@ -1406,6 +1552,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VIFALR, .name = "vifalr", .sid = TEGRA194_SID_VI_FALCON, .regs = { @@ -1415,6 +1562,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_VIFALW, .name = "vifalw", .sid = TEGRA194_SID_VI_FALCON, .regs = { @@ -1424,6 +1572,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA, .name = "dla0rda", .sid = TEGRA194_SID_NVDLA0, .regs = { @@ -1433,6 +1582,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB, .name = "dla0falrdb", .sid = TEGRA194_SID_NVDLA0, .regs = { @@ -1442,6 +1592,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0WRA, .name = "dla0wra", .sid = TEGRA194_SID_NVDLA0, .regs = { @@ -1451,6 +1602,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB, .name = "dla0falwrb", .sid = TEGRA194_SID_NVDLA0, .regs = { @@ -1460,6 +1612,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA, .name = "dla1rda", .sid = TEGRA194_SID_NVDLA1, .regs = { @@ -1469,6 +1622,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB, .name = "dla1falrdb", .sid = TEGRA194_SID_NVDLA1, .regs = { @@ -1478,6 +1632,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1WRA, .name = "dla1wra", .sid = TEGRA194_SID_NVDLA1, .regs = { @@ -1487,6 +1642,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB, .name = "dla1falwrb", .sid = TEGRA194_SID_NVDLA1, .regs = { @@ -1496,6 +1652,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA, .name = "pva0rda", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1505,6 +1662,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB, .name = "pva0rdb", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1514,6 +1672,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDC, .name = "pva0rdc", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1523,6 +1682,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRA, .name = "pva0wra", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1532,6 +1692,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRB, .name = "pva0wrb", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1541,6 +1702,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRC, .name = "pva0wrc", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1550,6 +1712,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA, .name = "pva1rda", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1559,6 +1722,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB, .name = "pva1rdb", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1568,6 +1732,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDC, .name = "pva1rdc", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1577,6 +1742,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRA, .name = "pva1wra", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1586,6 +1752,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRB, .name = "pva1wrb", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1595,6 +1762,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRC, .name = "pva1wrc", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1604,6 +1772,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_RCER, .name = "rcer", .sid = TEGRA194_SID_RCE, .regs = { @@ -1613,6 +1782,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_RCEW, .name = "rcew", .sid = TEGRA194_SID_RCE, .regs = { @@ -1622,6 +1792,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_RCEDMAR, .name = "rcedmar", .sid = TEGRA194_SID_RCE, .regs = { @@ -1631,6 +1802,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_RCEDMAW, .name = "rcedmaw", .sid = TEGRA194_SID_RCE, .regs = { @@ -1640,6 +1812,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD, .name = "nvenc1srd", .sid = TEGRA194_SID_NVENC1, .regs = { @@ -1649,6 +1822,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR, .name = "nvenc1swr", .sid = TEGRA194_SID_NVENC1, .regs = { @@ -1658,6 +1832,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0R, .name = "pcie0r", .sid = TEGRA194_SID_PCIE0, .regs = { @@ -1667,6 +1842,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0W, .name = "pcie0w", .sid = TEGRA194_SID_PCIE0, .regs = { @@ -1676,6 +1852,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE1R, .name = "pcie1r", .sid = TEGRA194_SID_PCIE1, .regs = { @@ -1685,6 +1862,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE1W, .name = "pcie1w", .sid = TEGRA194_SID_PCIE1, .regs = { @@ -1694,6 +1872,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE2AR, .name = "pcie2ar", .sid = TEGRA194_SID_PCIE2, .regs = { @@ -1703,6 +1882,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE2AW, .name = "pcie2aw", .sid = TEGRA194_SID_PCIE2, .regs = { @@ -1712,6 +1892,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE3R, .name = "pcie3r", .sid = TEGRA194_SID_PCIE3, .regs = { @@ -1721,6 +1902,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE3W, .name = "pcie3w", .sid = TEGRA194_SID_PCIE3, .regs = { @@ -1730,6 +1912,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE4R, .name = "pcie4r", .sid = TEGRA194_SID_PCIE4, .regs = { @@ -1739,6 +1922,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE4W, .name = "pcie4w", .sid = TEGRA194_SID_PCIE4, .regs = { @@ -1748,6 +1932,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5R, .name = "pcie5r", .sid = TEGRA194_SID_PCIE5, .regs = { @@ -1757,6 +1942,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5W, .name = "pcie5w", .sid = TEGRA194_SID_PCIE5, .regs = { @@ -1766,6 +1952,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPFALW, .name = "ispfalw", .sid = TEGRA194_SID_ISP_FALCON, .regs = { @@ -1775,6 +1962,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1, .name = "dla0rda1", .sid = TEGRA194_SID_NVDLA0, .regs = { @@ -1784,6 +1972,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1, .name = "dla1rda1", .sid = TEGRA194_SID_NVDLA1, .regs = { @@ -1793,6 +1982,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1, .name = "pva0rda1", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1802,6 +1992,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1, .name = "pva0rdb1", .sid = TEGRA194_SID_PVA0, .regs = { @@ -1811,6 +2002,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1, .name = "pva1rda1", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1820,6 +2012,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1, .name = "pva1rdb1", .sid = TEGRA194_SID_PVA1, .regs = { @@ -1829,6 +2022,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5R1, .name = "pcie5r1", .sid = TEGRA194_SID_PCIE5, .regs = { @@ -1838,6 +2032,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1, .name = "nvencsrd1", .sid = TEGRA194_SID_NVENC, .regs = { @@ -1847,6 +2042,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1, .name = "nvenc1srd1", .sid = TEGRA194_SID_NVENC1, .regs = { @@ -1856,6 +2052,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_ISPRA1, .name = "ispra1", .sid = TEGRA194_SID_ISP, .regs = { @@ -1865,6 +2062,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0R1, .name = "pcie0r1", .sid = TEGRA194_SID_PCIE0, .regs = { @@ -1874,6 +2072,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD, .name = "nvdec1srd", .sid = TEGRA194_SID_NVDEC1, .regs = { @@ -1883,6 +2082,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1, .name = "nvdec1srd1", .sid = TEGRA194_SID_NVDEC1, .regs = { @@ -1892,6 +2092,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR, .name = "nvdec1swr", .sid = TEGRA194_SID_NVDEC1, .regs = { @@ -1901,6 +2102,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU5R, .name = "miu5r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1910,6 +2112,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU5W, .name = "miu5w", .sid = TEGRA194_SID_MIU, .regs = { @@ -1919,6 +2122,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU6R, .name = "miu6r", .sid = TEGRA194_SID_MIU, .regs = { @@ -1928,6 +2132,7 @@ static const struct tegra_mc_client tegra194_mc_clients[] = { }, }, }, { + .id = TEGRA194_MEMORY_CLIENT_MIU6W, .name = "miu6w", .sid = TEGRA194_SID_MIU, .regs = { From patchwork Wed Jun 2 16:33:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12295285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, 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cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:31:55 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Jon Hunter , Dmitry Osipenko , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 12/12] memory: tegra: Split Tegra194 data into separate file Date: Wed, 2 Jun 2021 18:33:02 +0200 Message-Id: <20210602163302.120041-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602163302.120041-1-thierry.reding@gmail.com> References: <20210602163302.120041-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_093202_283574_B9949401 X-CRM114-Status: GOOD ( 15.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Keep the directory structure consistent by splitting the Tegra194 data into a separate file. Signed-off-by: Thierry Reding --- Changes in v3: - drop redundant #ifdef/#endif guards drivers/memory/tegra/Makefile | 2 +- drivers/memory/tegra/mc.h | 5 + drivers/memory/tegra/tegra186.c | 1349 +----------------------------- drivers/memory/tegra/tegra194.c | 1351 +++++++++++++++++++++++++++++++ 4 files changed, 1358 insertions(+), 1349 deletions(-) create mode 100644 drivers/memory/tegra/tegra194.c diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 1af0fefacdda..c992e87782d2 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -8,7 +8,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o -tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o +tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 24f95e06d18a..1e492989c363 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -146,6 +146,11 @@ int tegra30_mc_probe(struct tegra_mc *mc); extern const struct tegra_mc_ops tegra30_mc_ops; #endif +#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ + defined(CONFIG_ARCH_TEGRA_194_SOC) +extern const struct tegra_mc_ops tegra186_mc_ops; +#endif + extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 2f6ef46c33a4..1f87915ccd62 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -15,10 +15,6 @@ #include #endif -#if defined(CONFIG_ARCH_TEGRA_194_SOC) -#include -#endif - static void tegra186_mc_program_sid(struct tegra_mc *mc) { unsigned int i; @@ -70,7 +66,7 @@ static int tegra186_mc_resume(struct tegra_mc *mc) return 0; } -static const struct tegra_mc_ops tegra186_mc_ops = { +const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, @@ -808,1346 +804,3 @@ const struct tegra_mc_soc tegra186_mc_soc = { .ops = &tegra186_mc_ops, }; #endif - -#if defined(CONFIG_ARCH_TEGRA_194_SOC) -static const struct tegra_mc_client tegra194_mc_clients[] = { - { - .id = TEGRA194_MEMORY_CLIENT_PTCR, - .name = "ptcr", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x000, - .security = 0x004, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU7R, - .name = "miu7r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x008, - .security = 0x00c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU7W, - .name = "miu7w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x010, - .security = 0x014, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_HDAR, - .name = "hdar", - .sid = TEGRA194_SID_HDA, - .regs = { - .sid = { - .override = 0x0a8, - .security = 0x0ac, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR, - .name = "host1xdmar", - .sid = TEGRA194_SID_HOST1X, - .regs = { - .sid = { - .override = 0x0b0, - .security = 0x0b4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENCSRD, - .name = "nvencsrd", - .sid = TEGRA194_SID_NVENC, - .regs = { - .sid = { - .override = 0x0e0, - .security = 0x0e4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SATAR, - .name = "satar", - .sid = TEGRA194_SID_SATA, - .regs = { - .sid = { - .override = 0x0f8, - .security = 0x0fc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MPCORER, - .name = "mpcorer", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x138, - .security = 0x13c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENCSWR, - .name = "nvencswr", - .sid = TEGRA194_SID_NVENC, - .regs = { - .sid = { - .override = 0x158, - .security = 0x15c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_HDAW, - .name = "hdaw", - .sid = TEGRA194_SID_HDA, - .regs = { - .sid = { - .override = 0x1a8, - .security = 0x1ac, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MPCOREW, - .name = "mpcorew", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x1c8, - .security = 0x1cc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SATAW, - .name = "sataw", - .sid = TEGRA194_SID_SATA, - .regs = { - .sid = { - .override = 0x1e8, - .security = 0x1ec, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPRA, - .name = "ispra", - .sid = TEGRA194_SID_ISP, - .regs = { - .sid = { - .override = 0x220, - .security = 0x224, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPFALR, - .name = "ispfalr", - .sid = TEGRA194_SID_ISP_FALCON, - .regs = { - .sid = { - .override = 0x228, - .security = 0x22c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPWA, - .name = "ispwa", - .sid = TEGRA194_SID_ISP, - .regs = { - .sid = { - .override = 0x230, - .security = 0x234, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPWB, - .name = "ispwb", - .sid = TEGRA194_SID_ISP, - .regs = { - .sid = { - .override = 0x238, - .security = 0x23c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR, - .name = "xusb_hostr", - .sid = TEGRA194_SID_XUSB_HOST, - .regs = { - .sid = { - .override = 0x250, - .security = 0x254, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW, - .name = "xusb_hostw", - .sid = TEGRA194_SID_XUSB_HOST, - .regs = { - .sid = { - .override = 0x258, - .security = 0x25c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR, - .name = "xusb_devr", - .sid = TEGRA194_SID_XUSB_DEV, - .regs = { - .sid = { - .override = 0x260, - .security = 0x264, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW, - .name = "xusb_devw", - .sid = TEGRA194_SID_XUSB_DEV, - .regs = { - .sid = { - .override = 0x268, - .security = 0x26c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCRA, - .name = "sdmmcra", - .sid = TEGRA194_SID_SDMMC1, - .regs = { - .sid = { - .override = 0x300, - .security = 0x304, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCR, - .name = "sdmmcr", - .sid = TEGRA194_SID_SDMMC3, - .regs = { - .sid = { - .override = 0x310, - .security = 0x314, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB, - .name = "sdmmcrab", - .sid = TEGRA194_SID_SDMMC4, - .regs = { - .sid = { - .override = 0x318, - .security = 0x31c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCWA, - .name = "sdmmcwa", - .sid = TEGRA194_SID_SDMMC1, - .regs = { - .sid = { - .override = 0x320, - .security = 0x324, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCW, - .name = "sdmmcw", - .sid = TEGRA194_SID_SDMMC3, - .regs = { - .sid = { - .override = 0x330, - .security = 0x334, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB, - .name = "sdmmcwab", - .sid = TEGRA194_SID_SDMMC4, - .regs = { - .sid = { - .override = 0x338, - .security = 0x33c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VICSRD, - .name = "vicsrd", - .sid = TEGRA194_SID_VIC, - .regs = { - .sid = { - .override = 0x360, - .security = 0x364, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VICSWR, - .name = "vicswr", - .sid = TEGRA194_SID_VIC, - .regs = { - .sid = { - .override = 0x368, - .security = 0x36c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VIW, - .name = "viw", - .sid = TEGRA194_SID_VI, - .regs = { - .sid = { - .override = 0x390, - .security = 0x394, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDECSRD, - .name = "nvdecsrd", - .sid = TEGRA194_SID_NVDEC, - .regs = { - .sid = { - .override = 0x3c0, - .security = 0x3c4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDECSWR, - .name = "nvdecswr", - .sid = TEGRA194_SID_NVDEC, - .regs = { - .sid = { - .override = 0x3c8, - .security = 0x3cc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_APER, - .name = "aper", - .sid = TEGRA194_SID_APE, - .regs = { - .sid = { - .override = 0x3c0, - .security = 0x3c4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_APEW, - .name = "apew", - .sid = TEGRA194_SID_APE, - .regs = { - .sid = { - .override = 0x3d0, - .security = 0x3d4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD, - .name = "nvjpgsrd", - .sid = TEGRA194_SID_NVJPG, - .regs = { - .sid = { - .override = 0x3f0, - .security = 0x3f4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR, - .name = "nvjpgswr", - .sid = TEGRA194_SID_NVJPG, - .regs = { - .sid = { - .override = 0x3f0, - .security = 0x3f4, - }, - }, - }, { - .name = "axiapr", - .id = TEGRA194_MEMORY_CLIENT_AXIAPR, - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x410, - .security = 0x414, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AXIAPW, - .name = "axiapw", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x418, - .security = 0x41c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ETRR, - .name = "etrr", - .sid = TEGRA194_SID_ETR, - .regs = { - .sid = { - .override = 0x420, - .security = 0x424, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ETRW, - .name = "etrw", - .sid = TEGRA194_SID_ETR, - .regs = { - .sid = { - .override = 0x428, - .security = 0x42c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AXISR, - .name = "axisr", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x460, - .security = 0x464, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AXISW, - .name = "axisw", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x468, - .security = 0x46c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_EQOSR, - .name = "eqosr", - .sid = TEGRA194_SID_EQOS, - .regs = { - .sid = { - .override = 0x470, - .security = 0x474, - }, - }, - }, { - .name = "eqosw", - .id = TEGRA194_MEMORY_CLIENT_EQOSW, - .sid = TEGRA194_SID_EQOS, - .regs = { - .sid = { - .override = 0x478, - .security = 0x47c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_UFSHCR, - .name = "ufshcr", - .sid = TEGRA194_SID_UFSHC, - .regs = { - .sid = { - .override = 0x480, - .security = 0x484, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_UFSHCW, - .name = "ufshcw", - .sid = TEGRA194_SID_UFSHC, - .regs = { - .sid = { - .override = 0x488, - .security = 0x48c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR, - .name = "nvdisplayr", - .sid = TEGRA194_SID_NVDISPLAY, - .regs = { - .sid = { - .override = 0x490, - .security = 0x494, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_BPMPR, - .name = "bpmpr", - .sid = TEGRA194_SID_BPMP, - .regs = { - .sid = { - .override = 0x498, - .security = 0x49c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_BPMPW, - .name = "bpmpw", - .sid = TEGRA194_SID_BPMP, - .regs = { - .sid = { - .override = 0x4a0, - .security = 0x4a4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR, - .name = "bpmpdmar", - .sid = TEGRA194_SID_BPMP, - .regs = { - .sid = { - .override = 0x4a8, - .security = 0x4ac, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW, - .name = "bpmpdmaw", - .sid = TEGRA194_SID_BPMP, - .regs = { - .sid = { - .override = 0x4b0, - .security = 0x4b4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AONR, - .name = "aonr", - .sid = TEGRA194_SID_AON, - .regs = { - .sid = { - .override = 0x4b8, - .security = 0x4bc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AONW, - .name = "aonw", - .sid = TEGRA194_SID_AON, - .regs = { - .sid = { - .override = 0x4c0, - .security = 0x4c4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AONDMAR, - .name = "aondmar", - .sid = TEGRA194_SID_AON, - .regs = { - .sid = { - .override = 0x4c8, - .security = 0x4cc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_AONDMAW, - .name = "aondmaw", - .sid = TEGRA194_SID_AON, - .regs = { - .sid = { - .override = 0x4d0, - .security = 0x4d4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SCER, - .name = "scer", - .sid = TEGRA194_SID_SCE, - .regs = { - .sid = { - .override = 0x4d8, - .security = 0x4dc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SCEW, - .name = "scew", - .sid = TEGRA194_SID_SCE, - .regs = { - .sid = { - .override = 0x4e0, - .security = 0x4e4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SCEDMAR, - .name = "scedmar", - .sid = TEGRA194_SID_SCE, - .regs = { - .sid = { - .override = 0x4e8, - .security = 0x4ec, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_SCEDMAW, - .name = "scedmaw", - .sid = TEGRA194_SID_SCE, - .regs = { - .sid = { - .override = 0x4f0, - .security = 0x4f4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_APEDMAR, - .name = "apedmar", - .sid = TEGRA194_SID_APE, - .regs = { - .sid = { - .override = 0x4f8, - .security = 0x4fc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_APEDMAW, - .name = "apedmaw", - .sid = TEGRA194_SID_APE, - .regs = { - .sid = { - .override = 0x500, - .security = 0x504, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1, - .name = "nvdisplayr1", - .sid = TEGRA194_SID_NVDISPLAY, - .regs = { - .sid = { - .override = 0x508, - .security = 0x50c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VICSRD1, - .name = "vicsrd1", - .sid = TEGRA194_SID_VIC, - .regs = { - .sid = { - .override = 0x510, - .security = 0x514, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1, - .name = "nvdecsrd1", - .sid = TEGRA194_SID_NVDEC, - .regs = { - .sid = { - .override = 0x518, - .security = 0x51c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU0R, - .name = "miu0r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x530, - .security = 0x534, - }, - }, - }, { - .name = "miu0w", - .id = TEGRA194_MEMORY_CLIENT_MIU0W, - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x538, - .security = 0x53c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU1R, - .name = "miu1r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x540, - .security = 0x544, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU1W, - .name = "miu1w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x548, - .security = 0x54c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU2R, - .name = "miu2r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x570, - .security = 0x574, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU2W, - .name = "miu2w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x578, - .security = 0x57c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU3R, - .name = "miu3r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x580, - .security = 0x584, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU3W, - .name = "miu3w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x588, - .security = 0x58c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU4R, - .name = "miu4r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x590, - .security = 0x594, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU4W, - .name = "miu4w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x598, - .security = 0x59c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DPMUR, - .name = "dpmur", - .sid = TEGRA194_SID_PASSTHROUGH, - .regs = { - .sid = { - .override = 0x598, - .security = 0x59c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VIFALR, - .name = "vifalr", - .sid = TEGRA194_SID_VI_FALCON, - .regs = { - .sid = { - .override = 0x5e0, - .security = 0x5e4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_VIFALW, - .name = "vifalw", - .sid = TEGRA194_SID_VI_FALCON, - .regs = { - .sid = { - .override = 0x5e8, - .security = 0x5ec, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA0RDA, - .name = "dla0rda", - .sid = TEGRA194_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x5f0, - .security = 0x5f4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB, - .name = "dla0falrdb", - .sid = TEGRA194_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x5f8, - .security = 0x5fc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA0WRA, - .name = "dla0wra", - .sid = TEGRA194_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x600, - .security = 0x604, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB, - .name = "dla0falwrb", - .sid = TEGRA194_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x608, - .security = 0x60c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA1RDA, - .name = "dla1rda", - .sid = TEGRA194_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x610, - .security = 0x614, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB, - .name = "dla1falrdb", - .sid = TEGRA194_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x618, - .security = 0x61c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA1WRA, - .name = "dla1wra", - .sid = TEGRA194_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x620, - .security = 0x624, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB, - .name = "dla1falwrb", - .sid = TEGRA194_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x628, - .security = 0x62c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0RDA, - .name = "pva0rda", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x630, - .security = 0x634, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0RDB, - .name = "pva0rdb", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x638, - .security = 0x63c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0RDC, - .name = "pva0rdc", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x640, - .security = 0x644, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0WRA, - .name = "pva0wra", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x648, - .security = 0x64c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0WRB, - .name = "pva0wrb", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x650, - .security = 0x654, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0WRC, - .name = "pva0wrc", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x658, - .security = 0x65c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1RDA, - .name = "pva1rda", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x660, - .security = 0x664, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1RDB, - .name = "pva1rdb", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x668, - .security = 0x66c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1RDC, - .name = "pva1rdc", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x670, - .security = 0x674, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1WRA, - .name = "pva1wra", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x678, - .security = 0x67c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1WRB, - .name = "pva1wrb", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x680, - .security = 0x684, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1WRC, - .name = "pva1wrc", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x688, - .security = 0x68c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_RCER, - .name = "rcer", - .sid = TEGRA194_SID_RCE, - .regs = { - .sid = { - .override = 0x690, - .security = 0x694, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_RCEW, - .name = "rcew", - .sid = TEGRA194_SID_RCE, - .regs = { - .sid = { - .override = 0x698, - .security = 0x69c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_RCEDMAR, - .name = "rcedmar", - .sid = TEGRA194_SID_RCE, - .regs = { - .sid = { - .override = 0x6a0, - .security = 0x6a4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_RCEDMAW, - .name = "rcedmaw", - .sid = TEGRA194_SID_RCE, - .regs = { - .sid = { - .override = 0x6a8, - .security = 0x6ac, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD, - .name = "nvenc1srd", - .sid = TEGRA194_SID_NVENC1, - .regs = { - .sid = { - .override = 0x6b0, - .security = 0x6b4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR, - .name = "nvenc1swr", - .sid = TEGRA194_SID_NVENC1, - .regs = { - .sid = { - .override = 0x6b8, - .security = 0x6bc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE0R, - .name = "pcie0r", - .sid = TEGRA194_SID_PCIE0, - .regs = { - .sid = { - .override = 0x6c0, - .security = 0x6c4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE0W, - .name = "pcie0w", - .sid = TEGRA194_SID_PCIE0, - .regs = { - .sid = { - .override = 0x6c8, - .security = 0x6cc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE1R, - .name = "pcie1r", - .sid = TEGRA194_SID_PCIE1, - .regs = { - .sid = { - .override = 0x6d0, - .security = 0x6d4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE1W, - .name = "pcie1w", - .sid = TEGRA194_SID_PCIE1, - .regs = { - .sid = { - .override = 0x6d8, - .security = 0x6dc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE2AR, - .name = "pcie2ar", - .sid = TEGRA194_SID_PCIE2, - .regs = { - .sid = { - .override = 0x6e0, - .security = 0x6e4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE2AW, - .name = "pcie2aw", - .sid = TEGRA194_SID_PCIE2, - .regs = { - .sid = { - .override = 0x6e8, - .security = 0x6ec, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE3R, - .name = "pcie3r", - .sid = TEGRA194_SID_PCIE3, - .regs = { - .sid = { - .override = 0x6f0, - .security = 0x6f4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE3W, - .name = "pcie3w", - .sid = TEGRA194_SID_PCIE3, - .regs = { - .sid = { - .override = 0x6f8, - .security = 0x6fc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE4R, - .name = "pcie4r", - .sid = TEGRA194_SID_PCIE4, - .regs = { - .sid = { - .override = 0x700, - .security = 0x704, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE4W, - .name = "pcie4w", - .sid = TEGRA194_SID_PCIE4, - .regs = { - .sid = { - .override = 0x708, - .security = 0x70c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE5R, - .name = "pcie5r", - .sid = TEGRA194_SID_PCIE5, - .regs = { - .sid = { - .override = 0x710, - .security = 0x714, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE5W, - .name = "pcie5w", - .sid = TEGRA194_SID_PCIE5, - .regs = { - .sid = { - .override = 0x718, - .security = 0x71c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPFALW, - .name = "ispfalw", - .sid = TEGRA194_SID_ISP_FALCON, - .regs = { - .sid = { - .override = 0x720, - .security = 0x724, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1, - .name = "dla0rda1", - .sid = TEGRA194_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x748, - .security = 0x74c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1, - .name = "dla1rda1", - .sid = TEGRA194_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x750, - .security = 0x754, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1, - .name = "pva0rda1", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x758, - .security = 0x75c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1, - .name = "pva0rdb1", - .sid = TEGRA194_SID_PVA0, - .regs = { - .sid = { - .override = 0x760, - .security = 0x764, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1, - .name = "pva1rda1", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x768, - .security = 0x76c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1, - .name = "pva1rdb1", - .sid = TEGRA194_SID_PVA1, - .regs = { - .sid = { - .override = 0x770, - .security = 0x774, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE5R1, - .name = "pcie5r1", - .sid = TEGRA194_SID_PCIE5, - .regs = { - .sid = { - .override = 0x778, - .security = 0x77c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1, - .name = "nvencsrd1", - .sid = TEGRA194_SID_NVENC, - .regs = { - .sid = { - .override = 0x780, - .security = 0x784, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1, - .name = "nvenc1srd1", - .sid = TEGRA194_SID_NVENC1, - .regs = { - .sid = { - .override = 0x788, - .security = 0x78c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_ISPRA1, - .name = "ispra1", - .sid = TEGRA194_SID_ISP, - .regs = { - .sid = { - .override = 0x790, - .security = 0x794, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_PCIE0R1, - .name = "pcie0r1", - .sid = TEGRA194_SID_PCIE0, - .regs = { - .sid = { - .override = 0x798, - .security = 0x79c, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD, - .name = "nvdec1srd", - .sid = TEGRA194_SID_NVDEC1, - .regs = { - .sid = { - .override = 0x7c8, - .security = 0x7cc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1, - .name = "nvdec1srd1", - .sid = TEGRA194_SID_NVDEC1, - .regs = { - .sid = { - .override = 0x7d0, - .security = 0x7d4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR, - .name = "nvdec1swr", - .sid = TEGRA194_SID_NVDEC1, - .regs = { - .sid = { - .override = 0x7d8, - .security = 0x7dc, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU5R, - .name = "miu5r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x7e0, - .security = 0x7e4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU5W, - .name = "miu5w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x7e8, - .security = 0x7ec, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU6R, - .name = "miu6r", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x7f0, - .security = 0x7f4, - }, - }, - }, { - .id = TEGRA194_MEMORY_CLIENT_MIU6W, - .name = "miu6w", - .sid = TEGRA194_SID_MIU, - .regs = { - .sid = { - .override = 0x7f8, - .security = 0x7fc, - }, - }, - }, -}; - -const struct tegra_mc_soc tegra194_mc_soc = { - .num_clients = ARRAY_SIZE(tegra194_mc_clients), - .clients = tegra194_mc_clients, - .num_address_bits = 40, - .ops = &tegra186_mc_ops, -}; -#endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c new file mode 100644 index 000000000000..cab998b8bd5c --- /dev/null +++ b/drivers/memory/tegra/tegra194.c @@ -0,0 +1,1351 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. + */ + +#include + +#include + +#include "mc.h" + +static const struct tegra_mc_client tegra194_mc_clients[] = { + { + .id = TEGRA194_MEMORY_CLIENT_PTCR, + .name = "ptcr", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x000, + .security = 0x004, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU7R, + .name = "miu7r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x008, + .security = 0x00c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU7W, + .name = "miu7w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x010, + .security = 0x014, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_HDAR, + .name = "hdar", + .sid = TEGRA194_SID_HDA, + .regs = { + .sid = { + .override = 0x0a8, + .security = 0x0ac, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR, + .name = "host1xdmar", + .sid = TEGRA194_SID_HOST1X, + .regs = { + .sid = { + .override = 0x0b0, + .security = 0x0b4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD, + .name = "nvencsrd", + .sid = TEGRA194_SID_NVENC, + .regs = { + .sid = { + .override = 0x0e0, + .security = 0x0e4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SATAR, + .name = "satar", + .sid = TEGRA194_SID_SATA, + .regs = { + .sid = { + .override = 0x0f8, + .security = 0x0fc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MPCORER, + .name = "mpcorer", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x138, + .security = 0x13c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSWR, + .name = "nvencswr", + .sid = TEGRA194_SID_NVENC, + .regs = { + .sid = { + .override = 0x158, + .security = 0x15c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_HDAW, + .name = "hdaw", + .sid = TEGRA194_SID_HDA, + .regs = { + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MPCOREW, + .name = "mpcorew", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x1c8, + .security = 0x1cc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SATAW, + .name = "sataw", + .sid = TEGRA194_SID_SATA, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPRA, + .name = "ispra", + .sid = TEGRA194_SID_ISP, + .regs = { + .sid = { + .override = 0x220, + .security = 0x224, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPFALR, + .name = "ispfalr", + .sid = TEGRA194_SID_ISP_FALCON, + .regs = { + .sid = { + .override = 0x228, + .security = 0x22c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPWA, + .name = "ispwa", + .sid = TEGRA194_SID_ISP, + .regs = { + .sid = { + .override = 0x230, + .security = 0x234, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPWB, + .name = "ispwb", + .sid = TEGRA194_SID_ISP, + .regs = { + .sid = { + .override = 0x238, + .security = 0x23c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR, + .name = "xusb_hostr", + .sid = TEGRA194_SID_XUSB_HOST, + .regs = { + .sid = { + .override = 0x250, + .security = 0x254, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW, + .name = "xusb_hostw", + .sid = TEGRA194_SID_XUSB_HOST, + .regs = { + .sid = { + .override = 0x258, + .security = 0x25c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR, + .name = "xusb_devr", + .sid = TEGRA194_SID_XUSB_DEV, + .regs = { + .sid = { + .override = 0x260, + .security = 0x264, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW, + .name = "xusb_devw", + .sid = TEGRA194_SID_XUSB_DEV, + .regs = { + .sid = { + .override = 0x268, + .security = 0x26c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCRA, + .name = "sdmmcra", + .sid = TEGRA194_SID_SDMMC1, + .regs = { + .sid = { + .override = 0x300, + .security = 0x304, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCR, + .name = "sdmmcr", + .sid = TEGRA194_SID_SDMMC3, + .regs = { + .sid = { + .override = 0x310, + .security = 0x314, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB, + .name = "sdmmcrab", + .sid = TEGRA194_SID_SDMMC4, + .regs = { + .sid = { + .override = 0x318, + .security = 0x31c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCWA, + .name = "sdmmcwa", + .sid = TEGRA194_SID_SDMMC1, + .regs = { + .sid = { + .override = 0x320, + .security = 0x324, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCW, + .name = "sdmmcw", + .sid = TEGRA194_SID_SDMMC3, + .regs = { + .sid = { + .override = 0x330, + .security = 0x334, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB, + .name = "sdmmcwab", + .sid = TEGRA194_SID_SDMMC4, + .regs = { + .sid = { + .override = 0x338, + .security = 0x33c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VICSRD, + .name = "vicsrd", + .sid = TEGRA194_SID_VIC, + .regs = { + .sid = { + .override = 0x360, + .security = 0x364, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VICSWR, + .name = "vicswr", + .sid = TEGRA194_SID_VIC, + .regs = { + .sid = { + .override = 0x368, + .security = 0x36c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VIW, + .name = "viw", + .sid = TEGRA194_SID_VI, + .regs = { + .sid = { + .override = 0x390, + .security = 0x394, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD, + .name = "nvdecsrd", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSWR, + .name = "nvdecswr", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_APER, + .name = "aper", + .sid = TEGRA194_SID_APE, + .regs = { + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_APEW, + .name = "apew", + .sid = TEGRA194_SID_APE, + .regs = { + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD, + .name = "nvjpgsrd", + .sid = TEGRA194_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR, + .name = "nvjpgswr", + .sid = TEGRA194_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, + }, { + .name = "axiapr", + .id = TEGRA194_MEMORY_CLIENT_AXIAPR, + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x410, + .security = 0x414, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AXIAPW, + .name = "axiapw", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x418, + .security = 0x41c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ETRR, + .name = "etrr", + .sid = TEGRA194_SID_ETR, + .regs = { + .sid = { + .override = 0x420, + .security = 0x424, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ETRW, + .name = "etrw", + .sid = TEGRA194_SID_ETR, + .regs = { + .sid = { + .override = 0x428, + .security = 0x42c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AXISR, + .name = "axisr", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x460, + .security = 0x464, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AXISW, + .name = "axisw", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x468, + .security = 0x46c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_EQOSR, + .name = "eqosr", + .sid = TEGRA194_SID_EQOS, + .regs = { + .sid = { + .override = 0x470, + .security = 0x474, + }, + }, + }, { + .name = "eqosw", + .id = TEGRA194_MEMORY_CLIENT_EQOSW, + .sid = TEGRA194_SID_EQOS, + .regs = { + .sid = { + .override = 0x478, + .security = 0x47c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_UFSHCR, + .name = "ufshcr", + .sid = TEGRA194_SID_UFSHC, + .regs = { + .sid = { + .override = 0x480, + .security = 0x484, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_UFSHCW, + .name = "ufshcw", + .sid = TEGRA194_SID_UFSHC, + .regs = { + .sid = { + .override = 0x488, + .security = 0x48c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR, + .name = "nvdisplayr", + .sid = TEGRA194_SID_NVDISPLAY, + .regs = { + .sid = { + .override = 0x490, + .security = 0x494, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPR, + .name = "bpmpr", + .sid = TEGRA194_SID_BPMP, + .regs = { + .sid = { + .override = 0x498, + .security = 0x49c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPW, + .name = "bpmpw", + .sid = TEGRA194_SID_BPMP, + .regs = { + .sid = { + .override = 0x4a0, + .security = 0x4a4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR, + .name = "bpmpdmar", + .sid = TEGRA194_SID_BPMP, + .regs = { + .sid = { + .override = 0x4a8, + .security = 0x4ac, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW, + .name = "bpmpdmaw", + .sid = TEGRA194_SID_BPMP, + .regs = { + .sid = { + .override = 0x4b0, + .security = 0x4b4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AONR, + .name = "aonr", + .sid = TEGRA194_SID_AON, + .regs = { + .sid = { + .override = 0x4b8, + .security = 0x4bc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AONW, + .name = "aonw", + .sid = TEGRA194_SID_AON, + .regs = { + .sid = { + .override = 0x4c0, + .security = 0x4c4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AONDMAR, + .name = "aondmar", + .sid = TEGRA194_SID_AON, + .regs = { + .sid = { + .override = 0x4c8, + .security = 0x4cc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_AONDMAW, + .name = "aondmaw", + .sid = TEGRA194_SID_AON, + .regs = { + .sid = { + .override = 0x4d0, + .security = 0x4d4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SCER, + .name = "scer", + .sid = TEGRA194_SID_SCE, + .regs = { + .sid = { + .override = 0x4d8, + .security = 0x4dc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SCEW, + .name = "scew", + .sid = TEGRA194_SID_SCE, + .regs = { + .sid = { + .override = 0x4e0, + .security = 0x4e4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SCEDMAR, + .name = "scedmar", + .sid = TEGRA194_SID_SCE, + .regs = { + .sid = { + .override = 0x4e8, + .security = 0x4ec, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_SCEDMAW, + .name = "scedmaw", + .sid = TEGRA194_SID_SCE, + .regs = { + .sid = { + .override = 0x4f0, + .security = 0x4f4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_APEDMAR, + .name = "apedmar", + .sid = TEGRA194_SID_APE, + .regs = { + .sid = { + .override = 0x4f8, + .security = 0x4fc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_APEDMAW, + .name = "apedmaw", + .sid = TEGRA194_SID_APE, + .regs = { + .sid = { + .override = 0x500, + .security = 0x504, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .sid = TEGRA194_SID_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VICSRD1, + .name = "vicsrd1", + .sid = TEGRA194_SID_VIC, + .regs = { + .sid = { + .override = 0x510, + .security = 0x514, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1, + .name = "nvdecsrd1", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .sid = { + .override = 0x518, + .security = 0x51c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU0R, + .name = "miu0r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x530, + .security = 0x534, + }, + }, + }, { + .name = "miu0w", + .id = TEGRA194_MEMORY_CLIENT_MIU0W, + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x538, + .security = 0x53c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU1R, + .name = "miu1r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x540, + .security = 0x544, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU1W, + .name = "miu1w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x548, + .security = 0x54c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU2R, + .name = "miu2r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x570, + .security = 0x574, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU2W, + .name = "miu2w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x578, + .security = 0x57c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU3R, + .name = "miu3r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x580, + .security = 0x584, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU3W, + .name = "miu3w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x588, + .security = 0x58c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU4R, + .name = "miu4r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x590, + .security = 0x594, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU4W, + .name = "miu4w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x598, + .security = 0x59c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DPMUR, + .name = "dpmur", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .sid = { + .override = 0x598, + .security = 0x59c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VIFALR, + .name = "vifalr", + .sid = TEGRA194_SID_VI_FALCON, + .regs = { + .sid = { + .override = 0x5e0, + .security = 0x5e4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_VIFALW, + .name = "vifalw", + .sid = TEGRA194_SID_VI_FALCON, + .regs = { + .sid = { + .override = 0x5e8, + .security = 0x5ec, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA, + .name = "dla0rda", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x5f0, + .security = 0x5f4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB, + .name = "dla0falrdb", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x5f8, + .security = 0x5fc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0WRA, + .name = "dla0wra", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x600, + .security = 0x604, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB, + .name = "dla0falwrb", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x608, + .security = 0x60c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA, + .name = "dla1rda", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x610, + .security = 0x614, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB, + .name = "dla1falrdb", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x618, + .security = 0x61c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1WRA, + .name = "dla1wra", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x620, + .security = 0x624, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB, + .name = "dla1falwrb", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x628, + .security = 0x62c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA, + .name = "pva0rda", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x630, + .security = 0x634, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB, + .name = "pva0rdb", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x638, + .security = 0x63c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDC, + .name = "pva0rdc", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x640, + .security = 0x644, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRA, + .name = "pva0wra", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x648, + .security = 0x64c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRB, + .name = "pva0wrb", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x650, + .security = 0x654, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0WRC, + .name = "pva0wrc", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x658, + .security = 0x65c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA, + .name = "pva1rda", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x660, + .security = 0x664, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB, + .name = "pva1rdb", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x668, + .security = 0x66c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDC, + .name = "pva1rdc", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x670, + .security = 0x674, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRA, + .name = "pva1wra", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x678, + .security = 0x67c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRB, + .name = "pva1wrb", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x680, + .security = 0x684, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1WRC, + .name = "pva1wrc", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x688, + .security = 0x68c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_RCER, + .name = "rcer", + .sid = TEGRA194_SID_RCE, + .regs = { + .sid = { + .override = 0x690, + .security = 0x694, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_RCEW, + .name = "rcew", + .sid = TEGRA194_SID_RCE, + .regs = { + .sid = { + .override = 0x698, + .security = 0x69c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_RCEDMAR, + .name = "rcedmar", + .sid = TEGRA194_SID_RCE, + .regs = { + .sid = { + .override = 0x6a0, + .security = 0x6a4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_RCEDMAW, + .name = "rcedmaw", + .sid = TEGRA194_SID_RCE, + .regs = { + .sid = { + .override = 0x6a8, + .security = 0x6ac, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD, + .name = "nvenc1srd", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .sid = { + .override = 0x6b0, + .security = 0x6b4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR, + .name = "nvenc1swr", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .sid = { + .override = 0x6b8, + .security = 0x6bc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0R, + .name = "pcie0r", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c0, + .security = 0x6c4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0W, + .name = "pcie0w", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c8, + .security = 0x6cc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE1R, + .name = "pcie1r", + .sid = TEGRA194_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d0, + .security = 0x6d4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE1W, + .name = "pcie1w", + .sid = TEGRA194_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d8, + .security = 0x6dc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE2AR, + .name = "pcie2ar", + .sid = TEGRA194_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e0, + .security = 0x6e4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE2AW, + .name = "pcie2aw", + .sid = TEGRA194_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e8, + .security = 0x6ec, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE3R, + .name = "pcie3r", + .sid = TEGRA194_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f0, + .security = 0x6f4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE3W, + .name = "pcie3w", + .sid = TEGRA194_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f8, + .security = 0x6fc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE4R, + .name = "pcie4r", + .sid = TEGRA194_SID_PCIE4, + .regs = { + .sid = { + .override = 0x700, + .security = 0x704, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE4W, + .name = "pcie4w", + .sid = TEGRA194_SID_PCIE4, + .regs = { + .sid = { + .override = 0x708, + .security = 0x70c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5R, + .name = "pcie5r", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .sid = { + .override = 0x710, + .security = 0x714, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5W, + .name = "pcie5w", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .sid = { + .override = 0x718, + .security = 0x71c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPFALW, + .name = "ispfalw", + .sid = TEGRA194_SID_ISP_FALCON, + .regs = { + .sid = { + .override = 0x720, + .security = 0x724, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1, + .name = "dla0rda1", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x748, + .security = 0x74c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1, + .name = "dla1rda1", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x750, + .security = 0x754, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1, + .name = "pva0rda1", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x758, + .security = 0x75c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1, + .name = "pva0rdb1", + .sid = TEGRA194_SID_PVA0, + .regs = { + .sid = { + .override = 0x760, + .security = 0x764, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1, + .name = "pva1rda1", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x768, + .security = 0x76c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1, + .name = "pva1rdb1", + .sid = TEGRA194_SID_PVA1, + .regs = { + .sid = { + .override = 0x770, + .security = 0x774, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE5R1, + .name = "pcie5r1", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .sid = { + .override = 0x778, + .security = 0x77c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1, + .name = "nvencsrd1", + .sid = TEGRA194_SID_NVENC, + .regs = { + .sid = { + .override = 0x780, + .security = 0x784, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1, + .name = "nvenc1srd1", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .sid = { + .override = 0x788, + .security = 0x78c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_ISPRA1, + .name = "ispra1", + .sid = TEGRA194_SID_ISP, + .regs = { + .sid = { + .override = 0x790, + .security = 0x794, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_PCIE0R1, + .name = "pcie0r1", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .sid = { + .override = 0x798, + .security = 0x79c, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD, + .name = "nvdec1srd", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .sid = { + .override = 0x7c8, + .security = 0x7cc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1, + .name = "nvdec1srd1", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .sid = { + .override = 0x7d0, + .security = 0x7d4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR, + .name = "nvdec1swr", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .sid = { + .override = 0x7d8, + .security = 0x7dc, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU5R, + .name = "miu5r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x7e0, + .security = 0x7e4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU5W, + .name = "miu5w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x7e8, + .security = 0x7ec, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU6R, + .name = "miu6r", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x7f0, + .security = 0x7f4, + }, + }, + }, { + .id = TEGRA194_MEMORY_CLIENT_MIU6W, + .name = "miu6w", + .sid = TEGRA194_SID_MIU, + .regs = { + .sid = { + .override = 0x7f8, + .security = 0x7fc, + }, + }, + }, +}; + +const struct tegra_mc_soc tegra194_mc_soc = { + .num_clients = ARRAY_SIZE(tegra194_mc_clients), + .clients = tegra194_mc_clients, + .num_address_bits = 40, + .ops = &tegra186_mc_ops, +};