From patchwork Wed Jun 2 16:52:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12295389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C548BC4708F for ; Wed, 2 Jun 2021 17:06:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C86A61C8F for ; Wed, 2 Jun 2021 17:06:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C86A61C8F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PtjKubn3h6JiIe8NEH4tTReuM9zNDAQcpgl5ReNQrg8=; b=z4DOdR61nGZv6k JpmtfLXN0aGzW7zOZkddhP5slIv26vvIEhqX+yuxQWYxowEiEEiTbLvISWqJNkfctcJXUvk5lYbhL HC8MrQmpBnltSfeHwavoP0PkupMv6MJhUZbKu9N/Dxjkg38BjzGSQVcwVAAFO5FC6fPEfZ73M81jc lRt5eBNXsCZNBeC/l7JQqAtWfwlpgKeyUl1s9MPcILuVMIiDaDojF+L0eoaUDunUg3SNKTSc3qule kEYeBGlQlNW3myJOubOd+JqM+nQvbqyRY7iGicnUBsKXVwewqP/QYWuFgAzwAwVIk/O+dVbZdzbD6 LUAJS91yxwzShe/hcqvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loUHo-005M38-Ij; Wed, 02 Jun 2021 17:04:09 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1loU3d-005Fw1-6Z for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 16:49:32 +0000 Received: by mail-pj1-x102e.google.com with SMTP id l23-20020a17090a0717b029016ae774f973so1495908pjl.1 for ; Wed, 02 Jun 2021 09:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9ttH2lB2Q3iQhWxz0MO6TSPDv0IHfj1scw5R0SMtBJU=; b=nvCYD3LtO/CuojD7wCnU+c6O+R2pp2pb1KXMOskVgNnkGQajATVAekeuE6ORBh0Ejc R+rirwTVetIxLdBoJvcWUyV/gTioLE6JphhTZET6wlb79RKHV9XvZeWHYR6je6dKHZhF V9BbncwWr9HZVyJY1PRwvutwmxgKkuv8CpK/MGzO/FlSs4oHWlD92lTft0nt3i7IDq7o rYIzeDd6rqGScVllo4n47EJUGx0wKYSvfhhA9Z3pyjsJXJZMYyVf1+exgCwiMrudG5CO 0qy3xgJ8A/YEyVDXLulIRaX6UkQU9K3uybFEK4T83wm52schJGyQx/lKR2yp0XXccXP1 PthA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ttH2lB2Q3iQhWxz0MO6TSPDv0IHfj1scw5R0SMtBJU=; b=r2PNmVRqC02fuTll+Sr+3DCNRMNfixOWrewBiBWaORgcCfkncdd+3hBdAPV4yOnc6K c0Eb16D0TGuy1HXz1OZCUu2owB64CYxsSopKZWXuWjsTczx5sGIL0Rgi3v+36/vfyx6r ciR8hVqI6v4wVoa7OADfrngOhpffJ8BuEleqUuXTVfjyBR9aJDfKo8fHiVBVgeNcDOxj SL3X2tv3wagMQGI9PYetBBK2HE7tWqrNxY7vZcgGeDmotwhvea325fwaP7uIIdQZdeyD W33MjsiGT2CGsZzLBnVLtU9T23KM276T9P1DlKebqY/oK21tycq5HsD5Ly5H1hfyjM2O FCbQ== X-Gm-Message-State: AOAM530ovk91ERAilLPl/+gSm2YOnY+mbFUtHSfrEP/fJAbwml8urKJS CJ0hiQFYRgoc5BuDbA2R8gc= X-Google-Smtp-Source: ABdhPJyNuM1C0B/N7VSYw14UuHjXqYthGnVv3VSYDW7n4ueLVcZgKCAnAlLqEclUOMb0/oghQizYeA== X-Received: by 2002:a17:90a:de0c:: with SMTP id m12mr32297535pjv.54.1622652568268; Wed, 02 Jun 2021 09:49:28 -0700 (PDT) Received: from localhost (c-73-25-156-94.hsd1.or.comcast.net. [73.25.156.94]) by smtp.gmail.com with ESMTPSA id z5sm155302pfa.172.2021.06.02.09.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:49:27 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Subject: [RESEND PATCH v4 1/6] iommu/arm-smmu: Add support for driver IOMMU fault handlers Date: Wed, 2 Jun 2021 09:52:44 -0700 Message-Id: <20210602165313.553291-2-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602165313.553291-1-robdclark@gmail.com> References: <20210602165313.553291-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_094929_279468_A8837F5B X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , "open list:IOMMU DRIVERS" , Jordan Crouse , Jordan Crouse , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jordan Crouse Call report_iommu_fault() to allow upper-level drivers to register their own fault handlers. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Acked-by: Will Deacon --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 6f72c4d208ca..b4b32d31fc06 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -408,6 +408,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; int idx = smmu_domain->cfg.cbndx; + int ret; fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); if (!(fsr & ARM_SMMU_FSR_FAULT)) @@ -417,8 +418,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", + ret = report_iommu_fault(domain, NULL, iova, + fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + + if (ret == -ENOSYS) + dev_err_ratelimited(smmu->dev, + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", fsr, iova, fsynr, cbfrsynra, idx); arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); From patchwork Wed Jun 2 16:52:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12295401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFBB5C47083 for ; Wed, 2 Jun 2021 17:07:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 84A4961028 for ; Wed, 2 Jun 2021 17:07:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 84A4961028 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vojjb8n5YiGqBs24reVPMxIXpFBMlhzrALI0nI5x4jQ=; b=Hfk79GTajoOPaR g608Ft14cKqXKrRnzjSwnh4V6uoys423ZejSQJKx4/CnlHQSR/JWP9Utel2+8JK1khch3Sn+d3Rkx 0EDc0ZVYuE20Fh7ZPfWMYJvmFDj+2Ga4YxvxcTQ/j199ITEkZZ6TKEEMBD4rfwIRCNBCspeSRXJ2q cnDEX/hKsJaY9NN4YNPNuCEu5CjiUSW2FswUNtQ7kUrpp8bj7IXD5jEKFqcjj/sCDp3HtxY+pzPE4 VjobtWSVdaoRyzUMMRM0EWfJjqzUpAgZLFDoLUhJ60yBue7+0bbXlj0yn0j7rllhfXdoDba7kldF2 N0pRGrupXIMvfqWuPvcA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loUJ5-005MY4-K1; Wed, 02 Jun 2021 17:05:30 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1loU3k-005G08-Ec for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 16:49:39 +0000 Received: by mail-pl1-x62b.google.com with SMTP id c13so1431535plz.0 for ; Wed, 02 Jun 2021 09:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HIFc0p7RPawTOWte2X5RUNbAQ3QNHzruJUPp0tR4Akc=; b=P9ePaPkILna1m5EbwQyQwkT0F5woumNowvee3LlEvv7R6loAaqdHZPBAIXeLMoFO5/ ihdWj7C9r5gVAzJanHqmE7MTgZuWy4kzW+CUg7gQ5yMhTxjQKrwT9yvbC8F5b9dSBQs4 BJPaAZ9RPVEN1eiTye6lwPcxPzvwoHswKM+KT+1bguMptSJFFpSS99zU9I48xiNlQbHm upbiQH353g7Uh76sApyOL8hjfUOTU+GAOfxB4cZCiJiz7yWaEeul3Esyc58sw0JWHAgS IUzzhZ6bJ9uhR7UZ8IOa50Nr6Fga1vUXQbThGHZZj7TlJYFHbNHtK2eDXLwL1kG2gGZW aIMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HIFc0p7RPawTOWte2X5RUNbAQ3QNHzruJUPp0tR4Akc=; b=Msxib3MtH0fWATZ7AG0e3IkMXFnsePaKSZZl5ITWhrN/zEeWN/dF47ufZgOznEeNFL LxKJa4OAeY2few4j10f82+4STdpvwgiUHubOeWm9dO8Qp+PhEwJXI9Jq3tcYqQlVli/5 /5Go1YEh3HgL1OV7xG8u+anuME2o4EH8m75lyQ0lI7EjVRkqBa9BOLhp/e8ItEGq+h3I gB1j/PEsQ6BeJCOl8bMFXgF8CjD6GTt0H+JFH/Jx/2Oy5dSnONLY9hVA6BM/Ziubuuiv ckS2WbsaJlfCXMbX6zQ7SRFWVM6NtiqujoEi+MT9LGCsztvX+Tq7EKSN8YcdafXNd82k guaQ== X-Gm-Message-State: AOAM532ijir9nLnUHK4wGFgB9PlYaFE/PSxgNOcQ4lDVY9aubDSwiWIp wOHT+cwuL1oMHk10767g2Pg= X-Google-Smtp-Source: ABdhPJy/05e8S6GapiTSUMH4UiH1MxMRd+MYrooJwGK4MpokhKentSb+2TX288gZRMveN1R8WbJUvw== X-Received: by 2002:a17:90b:3004:: with SMTP id hg4mr3952990pjb.12.1622652575292; Wed, 02 Jun 2021 09:49:35 -0700 (PDT) Received: from localhost (c-73-25-156-94.hsd1.or.comcast.net. [73.25.156.94]) by smtp.gmail.com with ESMTPSA id u3sm158967pfk.73.2021.06.02.09.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:49:34 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Subject: [RESEND PATCH v4 2/6] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Date: Wed, 2 Jun 2021 09:52:45 -0700 Message-Id: <20210602165313.553291-3-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602165313.553291-1-robdclark@gmail.com> References: <20210602165313.553291-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_094936_552380_04DC1F8F X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Konrad Dybcio , Robin Murphy , "open list:IOMMU DRIVERS" , Bjorn Andersson , Jordan Crouse , Jordan Crouse , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jordan Crouse Add a callback in adreno-smmu-priv to read interesting SMMU registers to provide an opportunity for a richer debug experience in the GPU driver. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 98b3a1c2a181..b2e31ea84128 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } +static void qcom_adreno_smmu_get_fault_info(const void *cookie, + struct adreno_smmu_fault_info *info) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->cookie = smmu_domain; priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index c31a59d35c64..84c21c4b0691 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_FSYNR0 0x68 #define ARM_SMMU_FSYNR0_WNR BIT(4) +#define ARM_SMMU_CB_FSYNR1 0x6c + #define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIASID 0x610 #define ARM_SMMU_CB_S1_TLBIVAL 0x620 diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index a889f28afb42..53fe32fb9214 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -8,6 +8,32 @@ #include +/** + * struct adreno_smmu_fault_info - container for key fault information + * + * @far: The faulting IOVA from ARM_SMMU_CB_FAR + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR + * @fsr: The fault status from ARM_SMMU_CB_FSR + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) + * + * This struct passes back key page fault information to the GPU driver + * through the get_fault_info function pointer. + * The GPU driver can use this information to print informative + * log messages and provide deeper GPU specific insight into the fault. + */ +struct adreno_smmu_fault_info { + u64 far; + u64 ttbr0; + u32 contextidr; + u32 fsr; + u32 fsynr0; + u32 fsynr1; + u32 cbfrsynra; +}; + /** * struct adreno_smmu_priv - private interface between adreno-smmu and GPU * @@ -17,6 +43,8 @@ * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A * NULL config disables TTBR0 translation, otherwise * TTBR0 translation is enabled with the specified cfg + * @get_fault_info: Called by the GPU fault handler to get information about + * the fault * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -31,6 +59,7 @@ struct adreno_smmu_priv { const void *cookie; const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); }; -#endif /* __ADRENO_SMMU_PRIV_H */ \ No newline at end of file +#endif /* __ADRENO_SMMU_PRIV_H */ From patchwork Wed Jun 2 16:52:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12295403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4484FC4708F for ; Wed, 2 Jun 2021 17:08:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1075861028 for ; Wed, 2 Jun 2021 17:08:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1075861028 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=innPQC22fCwwObI2OTc819sfhI9JQcxc8pxkWRin1cM=; b=G9baWjm/6nKuxh 10mWxkXYeDIs/dsWPxFsr1zi8CLJgudtIeuR5tbjQt5t8Dklmsx6AHfmpx2zDohUR+IObMHNCHnjg Dcysbb5jC6KTO83jMfeJgC0qPG6R6A5UgnpKC1zfs1mm5UvEjai8uQ25fNccUTqLBWU/6SOQd5nou j+rrN/zfn/CFF/im4QWPEX613HvZBgYbvy/S+QuKBEkk2ALNzjBbL5aS9s8i98xeLs0qSGQeR35pm w1iwga/2TUrkru6YpCEsXYXw6SeofIYUMlSB4i46vWbqmQqd0eTrqeX7Ok1pumGa54/dfhvCPQGo1 /sXJ+m478fS7+b+kllEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loUK5-005NC8-5V; Wed, 02 Jun 2021 17:06:29 +0000 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1loU3v-005G5y-6M for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 16:49:49 +0000 Received: by mail-pg1-x52e.google.com with SMTP id 133so2748667pgf.2 for ; Wed, 02 Jun 2021 09:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HJLWu1zM3KEPxqyiMkUoKzy2S77vpcKMGJiuiZ9HewA=; b=by1ZflZbnh4CH2xpD3JNiXCoJYGIv8yKGm2fTIflNkLYEjcoJ7/ZVtj3c851MGW1ZB WIXDyaDd2cb45WhVKYQ7Z+lT/bGBfa00uXpQrUpgm5yXJsIbbPkRTW78w8p8D2XRumMk MkcbcPb2lTdCpsZWx1paYwuOilW6IbGWYLKVU0TlSqZXb0/tAelVcQpbJKUYuyaGACUu OmGxvPycGd2nofn73dYxG+THGn4rBtGl8gIeg29i5o7ZLivcrYU3YNGqzfefaPejpZg5 XdN71n/1WblpQRJY3NmMB56jVw8Gq6WqpmXh7aWlSjNvu0UBKqM/G09UfDReWjgmIpUb gENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HJLWu1zM3KEPxqyiMkUoKzy2S77vpcKMGJiuiZ9HewA=; b=gErZrEWo1jVzpzk8SG1j20KSddtL89F0hUgRL+E8eWHml9F2DyvccdbYGoh21+AmrR /a1UCJ36onPKxyERdgPIR0eVslNSaOiB8O8q3IdLtzBolrLA4udWyDvEG3EZBjSyu7O1 gxTj3meqywAtN6+AR5E1PAaerDTBlev0rQdubR5Cy0J8cy232Oq6I+4PRygzPn75LRSg hF7KRZOLY/ghXejIg0bLFplNa5/I68h7xxUrw2cnN1g2aEyBL8gXl+e84k2rFhRWVqSL YXOyhI1eEP7OOmr5SNGrdeiveKK+TdjA5LhtiI3HQ2Bnm1e0G8Kdp2pPtVYd4+s4sEvz qRDQ== X-Gm-Message-State: AOAM531NvXrALAf+k8sdGmro8VUbk0eifyOA77fmGnpFFjNKK0CZVrSR lbSC6xEcTkwp6r1eAhQMpEs= X-Google-Smtp-Source: ABdhPJx2jYZ4gw4zkgo10aKSFeUHDkdmxgHdyOEoyPAVT53mZVtusybZ5lKVB8P7rIbNejV3KGC6hQ== X-Received: by 2002:a65:4289:: with SMTP id j9mr34713823pgp.165.1622652586302; Wed, 02 Jun 2021 09:49:46 -0700 (PDT) Received: from localhost (c-73-25-156-94.hsd1.or.comcast.net. [73.25.156.94]) by smtp.gmail.com with ESMTPSA id h76sm176121pfe.161.2021.06.02.09.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 09:49:45 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Jordan Crouse , "Isaac J. Manjarres" , Sai Prakash Ranjan , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), iommu@lists.linux-foundation.org (open list:IOMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v4 4/6] iommu/arm-smmu-qcom: Add stall support Date: Wed, 2 Jun 2021 09:52:47 -0700 Message-Id: <20210602165313.553291-5-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210602165313.553291-1-robdclark@gmail.com> References: <20210602165313.553291-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_094947_268323_25CE9256 X-CRM114-Status: GOOD ( 20.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rob Clark Add, via the adreno-smmu-priv interface, a way for the GPU to request the SMMU to stall translation on faults, and then later resume the translation, either retrying or terminating the current translation. This will be used on the GPU side to "freeze" the GPU while we snapshot useful state for devcoredump. Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++ include/linux/adreno-smmu-priv.h | 7 +++++ 2 files changed, 40 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b2e31ea84128..61fc645c1325 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -13,6 +13,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; bool bypass_quirk; u8 bypass_cbndx; + u32 stall_enabled; }; static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) @@ -23,12 +24,17 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, u32 reg) { + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + /* * On the GPU device we want to process subsequent transactions after a * fault to keep the GPU from hanging */ reg |= ARM_SMMU_SCTLR_HUPCF; + if (qsmmu->stall_enabled & BIT(idx)) + reg |= ARM_SMMU_SCTLR_CFCFG; + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } @@ -48,6 +54,31 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie, info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); } +static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); + + if (enabled) + qsmmu->stall_enabled |= BIT(cfg->cbndx); + else + qsmmu->stall_enabled &= ~BIT(cfg->cbndx); +} + +static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + u32 reg = 0; + + if (terminate) + reg |= ARM_SMMU_RESUME_TERMINATE; + + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -173,6 +204,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; priv->get_fault_info = qcom_adreno_smmu_get_fault_info; + priv->set_stall = qcom_adreno_smmu_set_stall; + priv->resume_translation = qcom_adreno_smmu_resume_translation; return 0; } diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index 53fe32fb9214..c637e0997f6d 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -45,6 +45,11 @@ struct adreno_smmu_fault_info { * TTBR0 translation is enabled with the specified cfg * @get_fault_info: Called by the GPU fault handler to get information about * the fault + * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call + * before set_ttbr0_cfg(). If stalling on fault is enabled, + * the GPU driver must call resume_translation() + * @resume_translation: Resume translation after a fault + * * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -60,6 +65,8 @@ struct adreno_smmu_priv { const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); + void (*set_stall)(const void *cookie, bool enabled); + void (*resume_translation)(const void *cookie, bool terminate); }; #endif /* __ADRENO_SMMU_PRIV_H */