From patchwork Thu Jun 3 05:05:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12296175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8D1DC47097 for ; Thu, 3 Jun 2021 05:06:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5724613F0 for ; Thu, 3 Jun 2021 05:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229682AbhFCFHx (ORCPT ); Thu, 3 Jun 2021 01:07:53 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:58595 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229697AbhFCFHw (ORCPT ); Thu, 3 Jun 2021 01:07:52 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1622696768; h=Content-Transfer-Encoding: MIME-Version: Message-Id: Date: Subject: Cc: To: From: Sender; bh=yjEmiZ7jjHZMO1rvh/z4s+iEoOvJbPXaLOM9FC5ynDg=; b=DE2IYMtWEeadyJcnWNOxrHZ5iA1d8EsYdWmE+0lz5V8fy2v+bzy3ubx927A6etTTpK26t7Qu lxVKeoMhU5vROgrX7AUV1cUyFvwpt8xIQxD/fYoeEyj0vXt4t6YLw6h9LMy2xb9wv/aMSOh5 dREiChd9HNCzQUoTloU884p8pK4= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-west-2.postgun.com with SMTP id 60b8632b2eaeb98b5ecf4064 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 03 Jun 2021 05:05:47 GMT Sender: srivasam=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0F8F1C4323A; Thu, 3 Jun 2021 05:05:47 +0000 (UTC) Received: from hyd-lnxbld210.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: srivasam) by smtp.codeaurora.org (Postfix) with ESMTPSA id 05F97C433F1; Thu, 3 Jun 2021 05:05:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 05F97C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=srivasam@codeaurora.org From: Srinivasa Rao Mandadapu To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, srinivas.kandagatla@linaro.org, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, judyhsiao@chromium.org Cc: Srinivasa Rao Mandadapu Subject: [PATCH] ASoC: qcom: Fix for DMA interrupt clear reg overwriting Date: Thu, 3 Jun 2021 10:35:30 +0530 Message-Id: <20210603050530.15898-1-srivasam@codeaurora.org> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch fixes the DMA interrupt registers overwriting issue in lpass platform interrupt handler. Signed-off-by: Srinivasa Rao Mandadapu --- sound/soc/qcom/lpass-platform.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c index 0df9481ea4c6..e02caa121fa4 100644 --- a/sound/soc/qcom/lpass-platform.c +++ b/sound/soc/qcom/lpass-platform.c @@ -526,7 +526,7 @@ static int lpass_platform_pcmops_trigger(struct snd_soc_component *component, return -EINVAL; } - ret = regmap_write(map, reg_irqclr, val_irqclr); + ret = regmap_update_bits(map, reg_irqclr, val_irqclr, val_irqclr); if (ret) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret); return ret; @@ -650,7 +650,7 @@ static irqreturn_t lpass_dma_interrupt_handler( struct lpass_variant *v = drvdata->variant; irqreturn_t ret = IRQ_NONE; int rv; - unsigned int reg = 0, val = 0; + unsigned int reg = 0, val = 0, val_clr = 0, val_mask = 0; struct regmap *map; unsigned int dai_id = cpu_dai->driver->id; @@ -676,8 +676,9 @@ static irqreturn_t lpass_dma_interrupt_handler( return -EINVAL; } if (interrupts & LPAIF_IRQ_PER(chan)) { - - rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) | val); + val_clr = (LPAIF_IRQ_PER(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv); @@ -688,7 +689,9 @@ static irqreturn_t lpass_dma_interrupt_handler( } if (interrupts & LPAIF_IRQ_XRUN(chan)) { - rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) | val); + val_clr = (LPAIF_IRQ_XRUN(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv); @@ -700,7 +703,9 @@ static irqreturn_t lpass_dma_interrupt_handler( } if (interrupts & LPAIF_IRQ_ERR(chan)) { - rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) | val); + val_clr = (LPAIF_IRQ_ERR(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv);