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Thu, 03 Jun 2021 05:05:46 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 64708C433D3; Thu, 3 Jun 2021 05:05:46 +0000 (UTC) Received: from hyd-lnxbld210.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: srivasam) by smtp.codeaurora.org (Postfix) with ESMTPSA id 05F97C433F1; Thu, 3 Jun 2021 05:05:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 05F97C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=srivasam@codeaurora.org From: Srinivasa Rao Mandadapu To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, srinivas.kandagatla@linaro.org, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, judyhsiao@chromium.org Subject: [PATCH] ASoC: qcom: Fix for DMA interrupt clear reg overwriting Date: Thu, 3 Jun 2021 10:35:30 +0530 Message-Id: <20210603050530.15898-1-srivasam@codeaurora.org> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Cc: Srinivasa Rao Mandadapu X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This patch fixes the DMA interrupt registers overwriting issue in lpass platform interrupt handler. Signed-off-by: Srinivasa Rao Mandadapu --- sound/soc/qcom/lpass-platform.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c index 0df9481ea4c6..e02caa121fa4 100644 --- a/sound/soc/qcom/lpass-platform.c +++ b/sound/soc/qcom/lpass-platform.c @@ -526,7 +526,7 @@ static int lpass_platform_pcmops_trigger(struct snd_soc_component *component, return -EINVAL; } - ret = regmap_write(map, reg_irqclr, val_irqclr); + ret = regmap_update_bits(map, reg_irqclr, val_irqclr, val_irqclr); if (ret) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret); return ret; @@ -650,7 +650,7 @@ static irqreturn_t lpass_dma_interrupt_handler( struct lpass_variant *v = drvdata->variant; irqreturn_t ret = IRQ_NONE; int rv; - unsigned int reg = 0, val = 0; + unsigned int reg = 0, val = 0, val_clr = 0, val_mask = 0; struct regmap *map; unsigned int dai_id = cpu_dai->driver->id; @@ -676,8 +676,9 @@ static irqreturn_t lpass_dma_interrupt_handler( return -EINVAL; } if (interrupts & LPAIF_IRQ_PER(chan)) { - - rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) | val); + val_clr = (LPAIF_IRQ_PER(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv); @@ -688,7 +689,9 @@ static irqreturn_t lpass_dma_interrupt_handler( } if (interrupts & LPAIF_IRQ_XRUN(chan)) { - rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) | val); + val_clr = (LPAIF_IRQ_XRUN(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv); @@ -700,7 +703,9 @@ static irqreturn_t lpass_dma_interrupt_handler( } if (interrupts & LPAIF_IRQ_ERR(chan)) { - rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) | val); + val_clr = (LPAIF_IRQ_ERR(chan) | val); + val_mask = LPAIF_IRQ_ALL(chan); + rv = regmap_update_bits(map, reg, val_mask, val_clr); if (rv) { dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", rv);