From patchwork Fri Jun 4 19:05:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300513 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D70D6C4743C for ; Fri, 4 Jun 2021 19:05:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD978601FA for ; Fri, 4 Jun 2021 19:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230383AbhFDTHf (ORCPT ); Fri, 4 Jun 2021 15:07:35 -0400 Received: from mga06.intel.com ([134.134.136.31]:48564 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhFDTHd (ORCPT ); Fri, 4 Jun 2021 15:07:33 -0400 IronPort-SDR: 9u38mVsjHPuAjHm6nafBo8QIfl+CkupI93rp4XGpXQit/pp5DFl/BI4AxT6zyShcTD95UsXSNy al71yLRIn33Q== X-IronPort-AV: E=McAfee;i="6200,9189,10005"; a="265513931" X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="265513931" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:45 -0700 IronPort-SDR: 7yIl4I0bHiaT4siA51rao5h+U0gnmmtvQ3xiLjB49ECa9dL0CcJDEnoQTBdtiiUH10oncfTRCd sYudfQoggMBg== X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="401049101" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:45 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 1/9] cxl: Rename variable to match other code Date: Fri, 4 Jun 2021 12:05:33 -0700 Message-Id: <20210604190541.175602-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The current variable is word sized, and so this makes the CXL code match the rest of the code. --- ls-ecaps.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/ls-ecaps.c b/ls-ecaps.c index 99c55ff..edb4401 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -692,7 +692,7 @@ cap_rcec(struct device *d, int where) static void cap_dvsec_cxl(struct device *d, int where) { - u16 l; + u16 w; printf(": CXL\n"); if (verbose < 2) @@ -701,19 +701,19 @@ cap_dvsec_cxl(struct device *d, int where) if (!config_fetch(d, where + PCI_CXL_CAP, 12)) return; - l = get_conf_word(d, where + PCI_CXL_CAP); + w = get_conf_word(d, where + PCI_CXL_CAP); printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", - FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM), - FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL)); + FLAG(w, PCI_CXL_CAP_CACHE), FLAG(w, PCI_CXL_CAP_IO), FLAG(w, PCI_CXL_CAP_MEM), + FLAG(w, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_CAP_VIRAL)); - l = get_conf_word(d, where + PCI_CXL_CTRL); + w = get_conf_word(d, where + PCI_CXL_CTRL); printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", - FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM), - PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN), - FLAG(l, PCI_CXL_CTRL_VIRAL)); + FLAG(w, PCI_CXL_CTRL_CACHE), FLAG(w, PCI_CXL_CTRL_IO), FLAG(w, PCI_CXL_CTRL_MEM), + PCI_CXL_CTRL_CACHE_SF_COV(w), PCI_CXL_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_CTRL_CACHE_CLN), + FLAG(w, PCI_CXL_CTRL_VIRAL)); - l = get_conf_word(d, where + PCI_CXL_STATUS); - printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL)); + w = get_conf_word(d, where + PCI_CXL_STATUS); + printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_STATUS_VIRAL)); } static void From patchwork Fri Jun 4 19:05:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300511 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88A7FC4743D for ; Fri, 4 Jun 2021 19:05:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 715EE6140C for ; Fri, 4 Jun 2021 19:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbhFDTHe (ORCPT ); Fri, 4 Jun 2021 15:07:34 -0400 Received: from mga06.intel.com ([134.134.136.31]:48564 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229823AbhFDTHd (ORCPT ); Fri, 4 Jun 2021 15:07:33 -0400 IronPort-SDR: CmsX79GpxVSyeMlYCK/sCr3EDu0FjoUXLqIUf+u1Bol0ZFcH7UGbWOK4/f39WokFrPWT/01Nj2 ZsOTo9dG7sXw== X-IronPort-AV: E=McAfee;i="6200,9189,10005"; a="265513934" X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="265513934" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:46 -0700 IronPort-SDR: ZU+5V4L68kbEnP2eDF0yqzS/neR0B0TCPFoQf1eYuDWJYHskWV87S12iQSpL10WqcTuEpHAG+9 VPNrq52Wg8kg== X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="401049108" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:45 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 2/9] cxl: Make id check more explicit Date: Fri, 4 Jun 2021 12:05:34 -0700 Message-Id: <20210604190541.175602-3-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently only type 0 DVSEC caps are handled. Moving this check will allow more robust type handling in the future. Should be no functional change. Signed-off-by: Ben Widawsky --- ls-ecaps.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/ls-ecaps.c b/ls-ecaps.c index edb4401..83ca93e 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -690,7 +690,7 @@ cap_rcec(struct device *d, int where) } static void -cap_dvsec_cxl(struct device *d, int where) +cap_dvsec_cxl(struct device *d, int id, int where) { u16 w; @@ -698,6 +698,9 @@ cap_dvsec_cxl(struct device *d, int where) if (verbose < 2) return; + if (id != 0) + return; + if (!config_fetch(d, where + PCI_CXL_CAP, 12)) return; @@ -734,8 +737,8 @@ cap_dvsec(struct device *d, int where) u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len); - if (vendor == PCI_DVSEC_VENDOR_ID_CXL && id == PCI_DVSEC_ID_CXL && len >= 16) - cap_dvsec_cxl(d, where); + if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16) + cap_dvsec_cxl(d, id, where); else printf(" \n"); } From patchwork Fri Jun 4 19:05:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300515 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4C87C4743F for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90CDC601FA for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbhFDTHg (ORCPT ); Fri, 4 Jun 2021 15:07:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:48564 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbhFDTHf (ORCPT ); Fri, 4 Jun 2021 15:07:35 -0400 IronPort-SDR: iutIhCEes9pFAMl2eaWLHx+3AcvA8J5h2qhbMncA8EwbNbJmNCDeWSnrLdowJ01Islq4TRnnuB NuSfrZPEo5nQ== X-IronPort-AV: E=McAfee;i="6200,9189,10005"; a="265513935" X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="265513935" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:46 -0700 IronPort-SDR: z/HlabLCIGXnyuUr/Ijry5oAQxW/MPzwADybkkJ9wCM4/3l+kr3vhEePEh5JGiEkxxpDctKGLw MQfk5i9uWUCg== X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="401049113" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:46 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 3/9] cxl: Collect all DVSEC Device fields Date: Fri, 4 Jun 2021 12:05:35 -0700 Message-Id: <20210604190541.175602-4-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Ben Widawsky --- ls-ecaps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ls-ecaps.c b/ls-ecaps.c index 83ca93e..2b3f0f9 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -701,7 +701,7 @@ cap_dvsec_cxl(struct device *d, int id, int where) if (id != 0) return; - if (!config_fetch(d, where + PCI_CXL_CAP, 12)) + if (!config_fetch(d, where + PCI_CXL_CAP, 0x38 - 0xa)) return; w = get_conf_word(d, where + PCI_CXL_CAP); From patchwork Fri Jun 4 19:05:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300521 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B96F2C48BCD for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A41C4613FA for ; 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04 Jun 2021 12:05:46 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 4/9] cxl: Rework caps to new function Date: Fri, 4 Jun 2021 12:05:36 -0700 Message-Id: <20210604190541.175602-5-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This will help upcoming caps Signed-off-by: Ben Widawsky --- ls-ecaps.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/ls-ecaps.c b/ls-ecaps.c index 2b3f0f9..c2a13d5 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -690,35 +690,49 @@ cap_rcec(struct device *d, int where) } static void -cap_dvsec_cxl(struct device *d, int id, int where) +dvsec_cxl_device(uint8_t *data, int rev) { u16 w; - printf(": CXL\n"); - if (verbose < 2) - return; - - if (id != 0) - return; - - if (!config_fetch(d, where + PCI_CXL_CAP, 0x38 - 0xa)) + /* Legacy 1.1 revs aren't handled */ + if (rev != 1) return; - w = get_conf_word(d, where + PCI_CXL_CAP); + w = *(u16 *)(data + PCI_CXL_CAP); printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", FLAG(w, PCI_CXL_CAP_CACHE), FLAG(w, PCI_CXL_CAP_IO), FLAG(w, PCI_CXL_CAP_MEM), FLAG(w, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_CAP_VIRAL)); - w = get_conf_word(d, where + PCI_CXL_CTRL); + w = *(u16 *)(data + PCI_CXL_CTRL); printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", FLAG(w, PCI_CXL_CTRL_CACHE), FLAG(w, PCI_CXL_CTRL_IO), FLAG(w, PCI_CXL_CTRL_MEM), PCI_CXL_CTRL_CACHE_SF_COV(w), PCI_CXL_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_CTRL_CACHE_CLN), FLAG(w, PCI_CXL_CTRL_VIRAL)); - w = get_conf_word(d, where + PCI_CXL_STATUS); + w = *(u16 *)(data + PCI_CXL_STATUS); printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_STATUS_VIRAL)); } +static void +cap_dvsec_cxl(struct device *d, int id, int where) +{ + u8 rev; + + printf(": CXL\n"); + if (verbose < 2) + return; + + if (id != 0) + return; + + rev = BITS(get_conf_byte(d, where + 0x6), 0, 4); + + if (!config_fetch(d, where, 0x38)) + return; + + dvsec_cxl_device(d->config + where, rev); +} + static void cap_dvsec(struct device *d, int where) { From patchwork Fri Jun 4 19:05:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300519 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 345BAC4743E for ; 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d="scan'208";a="401049119" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:46 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 5/9] cxl: Rename caps to be device caps Date: Fri, 4 Jun 2021 12:05:37 -0700 Message-Id: <20210604190541.175602-6-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Ben Widawsky --- lib/header.h | 36 ++++++++++++++++++------------------ ls-ecaps.c | 18 +++++++++--------- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/lib/header.h b/lib/header.h index 170e5c1..3ff514a 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1067,24 +1067,24 @@ #define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 /* Designated Vendor-Specific Vendor ID for CXL */ #define PCI_DVSEC_ID_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */ -/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */ -#define PCI_CXL_CAP 0x0a /* CXL Capability Register */ -#define PCI_CXL_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ -#define PCI_CXL_CAP_IO 0x0002 /* CXL.io Protocol Support */ -#define PCI_CXL_CAP_MEM 0x0004 /* CXL.mem Protocol Support */ -#define PCI_CXL_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initializes with HW/FW Support */ -#define PCI_CXL_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */ -#define PCI_CXL_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */ -#define PCI_CXL_CTRL 0x0c /* CXL Control Register */ -#define PCI_CXL_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */ -#define PCI_CXL_CTRL_IO 0x0002 /* CXL.io Protocol Enable */ -#define PCI_CXL_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */ -#define PCI_CXL_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */ -#define PCI_CXL_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */ -#define PCI_CXL_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */ -#define PCI_CXL_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ -#define PCI_CXL_STATUS 0x0e /* CXL Status Register */ -#define PCI_CXL_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ +/* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */ +#define PCI_CXL_DEV_CAP 0x0a /* CXL Capability Register */ +#define PCI_CXL_DEV_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ +#define PCI_CXL_DEV_CAP_IO 0x0002 /* CXL.io Protocol Support */ +#define PCI_CXL_DEV_CAP_MEM 0x0004 /* CXL.mem Protocol Support */ +#define PCI_CXL_DEV_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initializes with HW/FW Support */ +#define PCI_CXL_DEV_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */ +#define PCI_CXL_DEV_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */ +#define PCI_CXL_DEV_CTRL 0x0c /* CXL Control Register */ +#define PCI_CXL_DEV_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */ +#define PCI_CXL_DEV_CTRL_IO 0x0002 /* CXL.io Protocol Enable */ +#define PCI_CXL_DEV_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */ +#define PCI_CXL_DEV_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */ +#define PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */ +#define PCI_CXL_DEV_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */ +#define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ +#define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */ +#define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ diff --git a/ls-ecaps.c b/ls-ecaps.c index c2a13d5..443d11d 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -698,19 +698,19 @@ dvsec_cxl_device(uint8_t *data, int rev) if (rev != 1) return; - w = *(u16 *)(data + PCI_CXL_CAP); + w = *(u16 *)(data + PCI_CXL_DEV_CAP); printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", - FLAG(w, PCI_CXL_CAP_CACHE), FLAG(w, PCI_CXL_CAP_IO), FLAG(w, PCI_CXL_CAP_MEM), - FLAG(w, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_CAP_VIRAL)); + FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM), + FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL)); - w = *(u16 *)(data + PCI_CXL_CTRL); + w = *(u16 *)(data + PCI_CXL_DEV_CTRL); printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", - FLAG(w, PCI_CXL_CTRL_CACHE), FLAG(w, PCI_CXL_CTRL_IO), FLAG(w, PCI_CXL_CTRL_MEM), - PCI_CXL_CTRL_CACHE_SF_COV(w), PCI_CXL_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_CTRL_CACHE_CLN), - FLAG(w, PCI_CXL_CTRL_VIRAL)); + FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM), + PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN), + FLAG(w, PCI_CXL_DEV_CTRL_VIRAL)); - w = *(u16 *)(data + PCI_CXL_STATUS); - printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_STATUS_VIRAL)); + w = *(u16 *)(data + PCI_CXL_DEV_STATUS); + printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL)); } static void From patchwork Fri Jun 4 19:05:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300527 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF942C48BCF for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA40A6140F for ; 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04 Jun 2021 12:05:46 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 6/9] cxl: Implement more device DVSEC decoding Date: Fri, 4 Jun 2021 12:05:38 -0700 Message-Id: <20210604190541.175602-7-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --- lib/header.h | 23 +++++++++++++++++++ ls-ecaps.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/lib/header.h b/lib/header.h index 3ff514a..c346548 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1085,6 +1085,29 @@ #define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ #define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */ #define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ +#define PCI_CXL_DEV_STATUS2 0x12 +#define PCI_CXL_DEV_STATUS_CACHE_INV 0x0001 +#define PCI_CXL_DEV_STATUS_RC 0x0002 /* Device Reset Complete */ +#define PCI_CXL_DEV_STATUS_RE 0x0004 /* Device Reset Error */ +#define PCI_CXL_DEV_STATUS_PMC 0x8000 /* Power Management Init Complete */ +#define PCI_CXL_DEV_CAP2 0x16 +#define PCI_CXL_DEV_CAP2_CACHE_UNK 0x0000 /* Cache Size Isn't Reported */ +#define PCI_CXL_DEV_CAP2_CACHE_64K 0x0001 /* Unit Size 64K */ +#define PCI_CXL_DEV_CAP2_CACHE_1M 0x0002 /* Unit Size 1M */ +#define PCI_CXL_DEV_RANGE1_SIZE_HI 0x18 +#define PCI_CXL_DEV_RANGE1_SIZE_LO 0x1c +#define PCI_CXL_RANGE_VALID 0x0001 +#define PCI_CXL_RANGE_ACTIVE 0x0002 +#define PCI_CXL_RANGE_TYPE(x) (((x) >> 2) & 0x7) +#define PCI_CXL_RANGE_CLASS(x) (((x) >> 5) & 0x7) +#define PCI_CXL_RANGE_INTERLEAVE(x) (((x) >> 8) & 0x1f) +#define PCI_CXL_RANGE_TIMEOUT(x) (((x) >> 13) & 0x7) +#define PCI_CXL_DEV_RANGE1_BASE_HI 0x20 +#define PCI_CXL_DEV_RANGE1_BASE_LO 0x24 +#define PCI_CXL_DEV_RANGE2_SIZE_HI 0x28 +#define PCI_CXL_DEV_RANGE2_SIZE_LO 0x2c +#define PCI_CXL_DEV_RANGE2_BASE_HI 0x30 +#define PCI_CXL_DEV_RANGE2_BASE_LO 0x34 /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ diff --git a/ls-ecaps.c b/ls-ecaps.c index 443d11d..8072bbe 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -689,9 +689,31 @@ cap_rcec(struct device *d, int where) printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn ); } +static void +cxl_range(u64 size, u64 base, int n) +{ + u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 }; + const char *type[] = { "Volatile", "Non-volatile", "CDAT" }; + const char *class[] = { "DRAM", "Storage", "CDAT" }; + u16 w; + + w = (u16) base; + + base &= ~0x0fffffffULL; + + printf("\t\tRange%d: %"PRIx64"-%"PRIx64"\n", n, base, base + size - 1); + printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n", + FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE), + type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)], + interleave[PCI_CXL_RANGE_INTERLEAVE(w)], + 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2)); +} + static void dvsec_cxl_device(uint8_t *data, int rev) { + u32 cache_size, cache_unit_size, l; + u64 range_base, range_size; u16 w; /* Legacy 1.1 revs aren't handled */ @@ -711,6 +733,49 @@ dvsec_cxl_device(uint8_t *data, int rev) w = *(u16 *)(data + PCI_CXL_DEV_STATUS); printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL)); + + w = *(u16 *)(data + PCI_CXL_DEV_STATUS2); + printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n", + FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC)); + + w = *(u16 *)(data + PCI_CXL_DEV_CAP2); + cache_unit_size = BITS(w, 0, 4); + cache_size = BITS(w, 8, 8); + switch (cache_unit_size) + { + case PCI_CXL_DEV_CAP2_CACHE_1M: + printf("\t\tCache Size: %08x\n", cache_size * (1<<20)); + break; + case PCI_CXL_DEV_CAP2_CACHE_64K: + printf("\t\tCache Size: %08x\n", cache_size * (64<<10)); + break; + case PCI_CXL_DEV_CAP2_CACHE_UNK: + printf("\t\tCache Size Not Reported\n"); + break; + default: + printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size); + break; + } + + l = *(u32 *)(data + PCI_CXL_DEV_RANGE1_SIZE_HI); + range_size = (u64) l << 32; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE1_SIZE_LO); + range_size |= l; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE1_BASE_HI); + range_base = (u64) l << 32; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE1_BASE_LO); + range_base |= l; + cxl_range(range_base, range_size, 1); + + l = *(u32 *)(data + PCI_CXL_DEV_RANGE2_SIZE_HI); + range_size = (u64) l << 32; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE2_SIZE_LO); + range_size |= l; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE2_BASE_HI); + range_base = (u64) l << 32; + l = *(u32 *)(data + PCI_CXL_DEV_RANGE2_BASE_LO); + range_base |= l; + cxl_range(range_base, range_size, 2); } static void From patchwork Fri Jun 4 19:05:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300525 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20C70C48BDF for ; Fri, 4 Jun 2021 19:05:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09DA86140C for ; Fri, 4 Jun 2021 19:05:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbhFDTHg (ORCPT ); Fri, 4 Jun 2021 15:07:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:48569 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhFDTHg (ORCPT ); Fri, 4 Jun 2021 15:07:36 -0400 IronPort-SDR: VBpEk4uaTSam57/hvLj1qu3oA8aR9sdmRRnKfc55jV7tNHnewQNnYeohDQKCWguqI1auJ/rGHE Hd5QW4vqaBwg== X-IronPort-AV: E=McAfee;i="6200,9189,10005"; a="265513942" X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="265513942" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:47 -0700 IronPort-SDR: HN8zOg0M6sGZxSydzu8dI/DALkGCL1bfOx6QrFCyG6gLr9iuEN3OF4KZ7h6l7cX0Z1fHkztY6L kXg+iEodHBRQ== X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="401049127" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:46 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 7/9] cxl: Add support for DVSEC port cap Date: Fri, 4 Jun 2021 12:05:39 -0700 Message-Id: <20210604190541.175602-8-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Ben Widawsky --- lib/header.h | 11 +++++++++++ ls-ecaps.c | 43 +++++++++++++++++++++++++++++++++++++------ 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/lib/header.h b/lib/header.h index c346548..8141e13 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1109,6 +1109,17 @@ #define PCI_CXL_DEV_RANGE2_BASE_HI 0x30 #define PCI_CXL_DEV_RANGE2_BASE_LO 0x34 +/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */ +#define PCI_CXL_PORT_EXT_STATUS 0x0a /* Port Extension Status */ +#define PCI_CXL_PORT_PM_INIT_COMPLETE 0x1 /* Port Power Management Initialization Complete */ +#define PCI_CXL_PORT_CTRL 0x0c /* Port Control Override */ +#define PCI_CXL_PORT_UNMASK_SBR 0x0001 /* Unmask SBR */ +#define PCI_CXL_PORT_UNMASK_LINK 0x0002 /* Unmask Link Disable */ +#define PCI_CXL_PORT_ALT_MEMORY 0x0004 /* Alt Memory and ID Space Enable */ +#define PCI_CXL_PORT_ALT_BME 0x0008 /* Alt BME */ +#define PCI_CXL_PORT_ALT_BUS_BASE 0xe +#define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ diff --git a/ls-ecaps.c b/ls-ecaps.c index 8072bbe..b11d5a9 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -778,6 +778,28 @@ dvsec_cxl_device(uint8_t *data, int rev) cxl_range(range_base, range_size, 2); } +static void +dvsec_cxl_port(uint8_t* data, int rev) +{ + u16 w; + u8 b1, b2; + + if (rev != 0) + return; + + w = *(u16 *)(data + PCI_CXL_PORT_EXT_STATUS); + printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS)); + + w = *(u16 *)(data + PCI_CXL_PORT_CTRL); + printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c\n", + FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK), + FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME)); + + b1 = *(u8 *)(data + PCI_CXL_PORT_ALT_BUS_BASE); + b2 = *(u8 *)(data + PCI_CXL_PORT_ALT_BUS_LIMIT); + printf("\t\tAlternateBus: %02x-%02x\n", b1, b2); +} + static void cap_dvsec_cxl(struct device *d, int id, int where) { @@ -787,15 +809,24 @@ cap_dvsec_cxl(struct device *d, int id, int where) if (verbose < 2) return; - if (id != 0) - return; - rev = BITS(get_conf_byte(d, where + 0x6), 0, 4); - if (!config_fetch(d, where, 0x38)) - return; + switch (id) { + case 0: + if (!config_fetch(d, where, 0x38)) + return; + + dvsec_cxl_device(d->config + where, rev); + break; + case 3: + if (!config_fetch(d, where, 0x28)) + return; - dvsec_cxl_device(d->config + where, rev); + dvsec_cxl_port(d->config + where, rev); + break; + default: + break; + } } static void From patchwork Fri Jun 4 19:05:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300517 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A813C48BC2 for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 44DDE613FA for ; Fri, 4 Jun 2021 19:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230409AbhFDTHg (ORCPT ); Fri, 4 Jun 2021 15:07:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:48569 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230254AbhFDTHe (ORCPT ); Fri, 4 Jun 2021 15:07:34 -0400 IronPort-SDR: ls52nCy6OONrFSvFDSX31hPPxZTMAR/HU8e+qkXbVNrt6FrdAYjJPXMsEciAbLxe2mHUC5yXOi gr/kZUFmKQTA== X-IronPort-AV: E=McAfee;i="6200,9189,10005"; a="265513943" X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="265513943" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:47 -0700 IronPort-SDR: UqWI9jC1pGkJpvMXQ5dgiz9hF8Jl+mhfiITIbGLMNvjbGVoE03QCAGqWb5oFKFu5ySakm4mtbp ZgQFsAfaEyxA== X-IronPort-AV: E=Sophos;i="5.83,248,1616482800"; d="scan'208";a="401049131" Received: from abathaly-mobl2.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.37]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 12:05:47 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 8/9] cxl: Add DVSEC Register Locator Date: Fri, 4 Jun 2021 12:05:40 -0700 Message-Id: <20210604190541.175602-9-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Ben Widawsky --- lib/header.h | 8 ++++++++ ls-ecaps.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/lib/header.h b/lib/header.h index 8141e13..b77a611 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1120,6 +1120,14 @@ #define PCI_CXL_PORT_ALT_BUS_BASE 0xe #define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf +/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */ +#define PCI_CXL_RL_BASE0_LO 0x0c +#define PCI_CXL_RL_BASE0_HI 0x10 +#define PCI_CXL_RL_BASE1_LO 0x14 +#define PCI_CXL_RL_BASE1_HI 0x18 +#define PCI_CXL_RL_BASE2_LO 0x1c +#define PCI_CXL_RL_BASE2_HI 0x20 + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ diff --git a/ls-ecaps.c b/ls-ecaps.c index b11d5a9..a0ef83d 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -800,9 +800,46 @@ dvsec_cxl_port(uint8_t* data, int rev) printf("\t\tAlternateBus: %02x-%02x\n", b1, b2); } +static const char *id[] = { + "empty", + "component registers", + "BAR virtualization", + "CXL device registers"}; + +static inline void +dvsec_decode_block(uint32_t lo, uint32_t hi, char which) +{ + u64 base_hi = hi, base_lo; + u8 bir, block_id; + + bir = BITS(lo, 0, 3); + block_id = BITS(lo, 8, 8); + base_lo = BITS(lo, 16, 16); + + if (!block_id) + return; + + printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]); + printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16); +} + +static void +dvsec_cxl_register_locator(uint8_t* data, int len, int rev) +{ + int i, j; + + if (rev != 0) + return; + + for (i = 0xc, j = 1; i < len; i += 8, j++) { + dvsec_decode_block(*(u32 *)(data + i), *(u32 *)(data + i + 4), j + 0x31); + } +} + static void cap_dvsec_cxl(struct device *d, int id, int where) { + u16 len; u8 rev; printf(": CXL\n"); @@ -824,6 +861,13 @@ cap_dvsec_cxl(struct device *d, int id, int where) dvsec_cxl_port(d->config + where, rev); break; + case 8: + len = BITS(get_conf_word(d, where + 0x6), 4, 12); + if (!config_fetch(d, where, len)) + return; + + dvsec_cxl_register_locator(d->config + where, len, rev); + break; default: break; } From patchwork Fri Jun 4 19:05:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12300523 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D8E3C48BD1 for ; Fri, 4 Jun 2021 19:05:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A3386140F for ; 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04 Jun 2021 12:05:47 -0700 From: Ben Widawsky To: linux-pci@vger.kernel.org Cc: =?utf-8?q?Martin_Mare=C5=A1?= , Dan Williams , Ben Widawsky Subject: [PATCH 9/9] cxl: Add placeholder for undecoded DVSECs Date: Fri, 4 Jun 2021 12:05:41 -0700 Message-Id: <20210604190541.175602-10-ben.widawsky@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com> References: <20210604190541.175602-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Ben Widawsky --- ls-ecaps.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/ls-ecaps.c b/ls-ecaps.c index a0ef83d..2d064be 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -868,6 +868,21 @@ cap_dvsec_cxl(struct device *d, int id, int where) dvsec_cxl_register_locator(d->config + where, len, rev); break; + case 2: + printf("\t\tNon-CXL Function Map DVSEC\n"); + break; + case 4: + printf("\t\tGPF DVSEC for Port\n"); + break; + case 5: + printf("\t\tGPF DVSEC for Device\n"); + break; + case 7: + printf("\t\tPCIe DVSEC Flex Bus Port\n"); + break; + case 9: + printf("\t\tMLD DVSEC\n"); + break; default: break; }