From patchwork Thu Jun 10 21:44:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12314133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3EF3C48BD1 for ; Thu, 10 Jun 2021 21:48:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BD12611CD for ; Thu, 10 Jun 2021 21:48:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5BD12611CD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Qikc2nUjjgEWgGWKfC3zKVwGzOuVi4W7/uc1+Z9NOWA=; b=VPHqBF7kGw1yOx tmZODIRTP2AikvmmdFJYfLQk+zF6LeT4zuisdLg/AT4t8z+wZeG/t93puwkTdljXcIJUsEK9r2d9+ qbu/9g6uz86e1wcnbsn6y5eGikij/O6Y5bU7R2tXxw4xItcNgHYaFU/L6NW/Os0DOcvvIYk4TJIgg zVr6H3tmB9Y2e3koGf8EE4eFGOe2cP3Suzd/aDabL7i+zhHkP1x2EpnJ5V0RwIoFtyW/c88fTOdOf leXU6WGmzU83pRBD9F7cLNrIrVecYPzBqpQvHCJAv/BlLkmZ/n9u6T1PX5NyVMY12h7mvHmdrBGoh Gefsac1jGQQKEDbDRnng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSVB-002aVx-3l; Thu, 10 Jun 2021 21:46:13 +0000 Received: from mail-pj1-f46.google.com ([209.85.216.46]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSU5-002ZzD-IF for linux-arm-kernel@lists.infradead.org; Thu, 10 Jun 2021 21:45:06 +0000 Received: by mail-pj1-f46.google.com with SMTP id g4so4499980pjk.0 for ; Thu, 10 Jun 2021 14:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BFeq080l4pyungY1s5smdqe1RkTm59ggcZkYab3uzaA=; b=od6K+JZZ2Ya1vmUSFUzEt823il+QDfWsVXULz6C3V7pvOQe/OzfOO55BSEJzkpc8V/ 5JOvD07BvVRg/OUQJGhdt3WhNAMlxvZRHKw4Tom3lj+u254y+rqPNS7CiyfzFeZWay14 QkHfcnTFWk3raQFcGjmXdXzCYZMGKeZkSW5nAnVFeL5+GKtd58AmcFt7hgF2x+oN5Mdk scz1q9J5xs3hherxMHktgpvuV/RTVG57XvRS98Lz1/enDmR2B62RVDrD80/v5vWPJlmt x5eEyI8CcqhqyEIkxvEwrjmZtexHTnAI/ORQNhFawNle8sCr38KIui2WPmSlV2mbDGXy DUsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BFeq080l4pyungY1s5smdqe1RkTm59ggcZkYab3uzaA=; b=uBS0VmcIbOYZZx+V781LURnugDnBnR9ntAbDjAzaVb0hfqGfjc0Ao2bmfwk0EEL9pq Z+snh61wE5lCgTU3gOm/3G9o+kGbPbx8vCBipRsz5qltU5VhKeH2FK6EemAHSq7qRPSt Gvwk18sOswODNXl6cA4NLCUMQWXxnlLXjy08uGvNXo5knKJkY17nekNSGLBZWtJ1nszg h8+TzBA7NYeZMcOYJu+qXWmFTtr9uVtJtgkVmiJ+ccW6bCKuYKIA11/2FYEtZuw4Kr5p 1HUlZW6TRTbBTVq4X0M5Wi1ojGNaIAGznPV71unzjxCYbkP331G0Ch53e2O/to5soAkd FmJg== X-Gm-Message-State: AOAM533nXJ0ISJ+x9UeS2DpzZlIQtQf6pV/SkQldF76HuOrztnGKKcu5 Ek0xWRakr2jywEeSgQwlEv4= X-Google-Smtp-Source: ABdhPJwTXFRr4e/p/Dd+f4YZhg9ockexXtaUtSitnB/HmG6Ps8HeqoEC32RQ+nVKhHQlYKvHIoRK8g== X-Received: by 2002:a17:90a:ad47:: with SMTP id w7mr901700pjv.51.1623361444589; Thu, 10 Jun 2021 14:44:04 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id h18sm3415629pgl.87.2021.06.10.14.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 14:44:03 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org Subject: [PATCH v5 1/5] iommu/arm-smmu: Add support for driver IOMMU fault handlers Date: Thu, 10 Jun 2021 14:44:09 -0700 Message-Id: <20210610214431.539029-2-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210610214431.539029-1-robdclark@gmail.com> References: <20210610214431.539029-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_144505_613626_0D4F4019 X-CRM114-Status: GOOD ( 12.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , Jordan Crouse , Jordan Crouse , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jordan Crouse Call report_iommu_fault() to allow upper-level drivers to register their own fault handlers. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Acked-by: Will Deacon Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 6f72c4d208ca..b4b32d31fc06 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -408,6 +408,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; int idx = smmu_domain->cfg.cbndx; + int ret; fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); if (!(fsr & ARM_SMMU_FSR_FAULT)) @@ -417,8 +418,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", + ret = report_iommu_fault(domain, NULL, iova, + fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); + + if (ret == -ENOSYS) + dev_err_ratelimited(smmu->dev, + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", fsr, iova, fsynr, cbfrsynra, idx); arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); From patchwork Thu Jun 10 21:44:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12314137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC122C48BDF for ; Thu, 10 Jun 2021 21:48:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA6B0610C7 for ; Thu, 10 Jun 2021 21:48:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA6B0610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vojjb8n5YiGqBs24reVPMxIXpFBMlhzrALI0nI5x4jQ=; b=OFDyiQGRJ8kSHG YMOtacQ7S5mAfCr60POo9+Mo+bBrPUsAaqMdcFoWmrGFD3wUJvEPPr8KpTsJ1N6DZ8+cnEKkmtLg0 3Xlne+ON4vfjcs0CrJFzeSQbGjff1YV3hU1qDr8pHNZq9VCS1qko45ksyYVf1MYmwf+oSZIm94Qf4 e/z5w7nOWL52LEAjU4Ieeov5K7DqXB9LegEMGQn2DyztEcWGqwsFisN4lV055N8NOdBpC2uOz9M1d K+cO9XHHA6p4fTfW52kQe7O6R1gXqAOScA8virY+g8EP1UWmX0r4T1ZIZOpg5xzcC4/xAynM5p5r0 517lRStpZJd5/ZePThCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSVQ-002acP-Qu; Thu, 10 Jun 2021 21:46:29 +0000 Received: from mail-pf1-f182.google.com ([209.85.210.182]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSUC-002a31-3B for linux-arm-kernel@lists.infradead.org; Thu, 10 Jun 2021 21:45:13 +0000 Received: by mail-pf1-f182.google.com with SMTP id z26so2718699pfj.5 for ; Thu, 10 Jun 2021 14:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HIFc0p7RPawTOWte2X5RUNbAQ3QNHzruJUPp0tR4Akc=; b=KYwyEPKzt7IprV/LmCS2jquVSyghQ2tyc9lbmuIJqsZKZEDVtv6iDeAY6UAgg8Th53 MiZUcU9/fmKz0rOx2+PLIqbUESjJZjPUTQKriWDpv0LTUDUq0xmrdqzR6UCDdUH7nmW3 hKUgwI9RfaeXkLafMG2y6isYxug2+LMPcqoJMNT0l+s8yp+1MySNQxaioRXjk3RY8KjG 2aSXfKdcmLKO5DuvdpCLDJxDQQoQJUPs+jWYRt/vNxIIlscepbnHow0mbAWqr/tXVz8O n9him5RUAH3VgfigS/jMsOfXeM+wcjNMQ5hd5Qb36dHXFv17p0eckDTbH5ybcok0mUR/ JzCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HIFc0p7RPawTOWte2X5RUNbAQ3QNHzruJUPp0tR4Akc=; b=FBcTIB+SWUH6IlBykCpYyOFPDV+kytZp8FXtNlRjPzppIZcoejCNIHMSqxD3EQESIc L8viXKDU701BLvoFvLv9eLJqHV+ybByDF4NqtU3klRr+/tA2PZr6C7Z+iFYCq7u5pM4D MyZjdb2RkBcP7SOOtAnZgfJeFd4nQenpGaMKUoWDYj/UtgGr/CD/4IPqi0vVgAeogzkO 5LQQG2mQFUiiVD4IuU3BowUAMkRJu1mxikSPwnPQbDWBp6yTsDNhT042INm+nFKiIOEQ av9vffNlqDufgE0aVhurXdJGqcnDeTEv0ZS6e40aVOeLDxyPilY6NJAfQvIShCpdj5pB yBTg== X-Gm-Message-State: AOAM530L8Kxb37ugS8OwODgY34xW2RwhnOBqOB0hKfGn0LvfA6VYSKCR 5c+Ppf5YKRybe+v3V7d1i8I= X-Google-Smtp-Source: ABdhPJx8TK8Z6LeedF51uN0HKCXtO0+L5zVZPp5Zt7RLf6pwy5Sz5ZLTcm/OeWpE0zZWB9Uj6hRDJw== X-Received: by 2002:a62:8803:0:b029:2d9:180d:c2c4 with SMTP id l3-20020a6288030000b02902d9180dc2c4mr4996054pfd.62.1623361451002; Thu, 10 Jun 2021 14:44:11 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id h18sm3415741pgl.87.2021.06.10.14.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 14:44:09 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org Subject: [PATCH v5 2/5] iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info Date: Thu, 10 Jun 2021 14:44:10 -0700 Message-Id: <20210610214431.539029-3-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210610214431.539029-1-robdclark@gmail.com> References: <20210610214431.539029-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_144512_154099_792DFA77 X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , "Isaac J. Manjarres" , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , Jordan Crouse , Jordan Crouse , John Stultz , Bjorn Andersson , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jordan Crouse Add a callback in adreno-smmu-priv to read interesting SMMU registers to provide an opportunity for a richer debug experience in the GPU driver. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 17 ++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 31 +++++++++++++++++++++- 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 98b3a1c2a181..b2e31ea84128 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } +static void qcom_adreno_smmu_get_fault_info(const void *cookie, + struct adreno_smmu_fault_info *info) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + + info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); + info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); + info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); + info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); + info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); + info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); + info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->cookie = smmu_domain; priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; + priv->get_fault_info = qcom_adreno_smmu_get_fault_info; return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index c31a59d35c64..84c21c4b0691 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -224,6 +224,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_FSYNR0 0x68 #define ARM_SMMU_FSYNR0_WNR BIT(4) +#define ARM_SMMU_CB_FSYNR1 0x6c + #define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIASID 0x610 #define ARM_SMMU_CB_S1_TLBIVAL 0x620 diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index a889f28afb42..53fe32fb9214 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -8,6 +8,32 @@ #include +/** + * struct adreno_smmu_fault_info - container for key fault information + * + * @far: The faulting IOVA from ARM_SMMU_CB_FAR + * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0 + * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR + * @fsr: The fault status from ARM_SMMU_CB_FSR + * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0 + * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0 + * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx) + * + * This struct passes back key page fault information to the GPU driver + * through the get_fault_info function pointer. + * The GPU driver can use this information to print informative + * log messages and provide deeper GPU specific insight into the fault. + */ +struct adreno_smmu_fault_info { + u64 far; + u64 ttbr0; + u32 contextidr; + u32 fsr; + u32 fsynr0; + u32 fsynr1; + u32 cbfrsynra; +}; + /** * struct adreno_smmu_priv - private interface between adreno-smmu and GPU * @@ -17,6 +43,8 @@ * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A * NULL config disables TTBR0 translation, otherwise * TTBR0 translation is enabled with the specified cfg + * @get_fault_info: Called by the GPU fault handler to get information about + * the fault * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -31,6 +59,7 @@ struct adreno_smmu_priv { const void *cookie; const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); }; -#endif /* __ADRENO_SMMU_PRIV_H */ \ No newline at end of file +#endif /* __ADRENO_SMMU_PRIV_H */ From patchwork Thu Jun 10 21:44:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 12314139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2729C48BE0 for ; Thu, 10 Jun 2021 21:48:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F8F5611CD for ; Thu, 10 Jun 2021 21:48:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F8F5611CD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=innPQC22fCwwObI2OTc819sfhI9JQcxc8pxkWRin1cM=; b=MlfjSz0B2+E/h0 DrDLLiquawWxC5KvBfNl2lixzPZi4yZwzmjswj4qerV/GW6WpMOYe234hNEzTN9/2ANYMsL9u6O4o gl71pgstfasSfE8ztUKA24/+Ko9SpilIm+p96mIH2UnHSZf+SugQjUaCLtgKuf+Y9dVqIuq/+1Lxt e4AFyUJGp0IePHn1SY7Lp14jOyAt4MTM4i2Qp46GV5gRsk6Pes1YBzIQnNRR9hfFaKv4J9MBVhuQV 834RwspkKEDgUY09nyzPQ+R3d02+Eo5TdsAf6jAM3ZaGkSbge6pLN7DWOwiszHnng1RZOeqk1DVZo VUB51Mng+YS7SyoUOZfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSW2-002ap4-9D; Thu, 10 Jun 2021 21:47:06 +0000 Received: from mail-pf1-f170.google.com ([209.85.210.170]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrSUL-002a8N-V1 for linux-arm-kernel@lists.infradead.org; Thu, 10 Jun 2021 21:45:23 +0000 Received: by mail-pf1-f170.google.com with SMTP id z26so2718998pfj.5 for ; Thu, 10 Jun 2021 14:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HJLWu1zM3KEPxqyiMkUoKzy2S77vpcKMGJiuiZ9HewA=; b=hnBQIh/wd7auKu7jB/+AkJxIOZRnhnERNDtkBJ2ycvt3RG1tw21KbmyRemIVrbHBUy WHOSstymU0X3jzlUY4Sn/LVT4DsEoV013MIDj6PNhWaBxdg1TzwXxj1SRXEiIwVPS4qS MOJxQ3HskbbmG6/bXlAJjhxjTMH7LhXDbDzdaPs8E/foeaNptuAk8Rweeudo7vnB65Pp Ij9G4sPVrc2g3vpeqxhxNZtKYV6O/iyxWgZ18OOJzXTl0ngYfYlViAaD/kga2ruHC+3r 5VmwHd9tNnUvHkf9Ltv5SP3DRvo/XC0OVZXtyvo/2dRZfW9NCZYCfKzyXxVUbTpPDnvs 0Alg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HJLWu1zM3KEPxqyiMkUoKzy2S77vpcKMGJiuiZ9HewA=; b=IiiqoCeUtrbyLXeDEYYEsZQLHh3gLzDL5dN2sWMMLHsAkL02nv/sf5m4BY5jBT+slA t0xZYuMNnsgXezv6pxQ9anpvE4kpxE3jDRhLSnINc8CYYj7MwvzTGiamS8k9MXsrRFwO lSStZz3FBSWbL9zSJjI+f7i6eMNLs3iqIw2YSCyEL71t/JcDHFpJQwo+hIkOHHd9eUe1 5hnS9mFwQy58/RGgg8EaKC4bVdq/jjxOudDMICa3J4G5aH82Io5IHS1xpHCKlglyWYg7 1esVNOy3Ksj+P67RgIg4RTf/iwtVb0qmGnZIK3ya2ovPIWAkwRL1CA5LSdNbi2fMit2f whxg== X-Gm-Message-State: AOAM533icelRLKaRwobJBnMLU49W20+DWvWXFu+F9VkUDC/uBEDGrrTT 1XLiOAHjrQgUwZPzU7oS+nI= X-Google-Smtp-Source: ABdhPJwbRxLCvWQdGZhBquW/xO9Y8PRm7Z5dFqU/NP/5TiyY9cbq46fok0OwhL/Hg4fvi2Ihwu+wyg== X-Received: by 2002:a63:ba5e:: with SMTP id l30mr427490pgu.43.1623361461037; Thu, 10 Jun 2021 14:44:21 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id n14sm3110079pfa.138.2021.06.10.14.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 14:44:20 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , "Isaac J. Manjarres" , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 4/5] iommu/arm-smmu-qcom: Add stall support Date: Thu, 10 Jun 2021 14:44:12 -0700 Message-Id: <20210610214431.539029-5-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210610214431.539029-1-robdclark@gmail.com> References: <20210610214431.539029-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_144522_031294_7E9B2D60 X-CRM114-Status: GOOD ( 19.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rob Clark Add, via the adreno-smmu-priv interface, a way for the GPU to request the SMMU to stall translation on faults, and then later resume the translation, either retrying or terminating the current translation. This will be used on the GPU side to "freeze" the GPU while we snapshot useful state for devcoredump. Signed-off-by: Rob Clark Acked-by: Jordan Crouse Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++ include/linux/adreno-smmu-priv.h | 7 +++++ 2 files changed, 40 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b2e31ea84128..61fc645c1325 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -13,6 +13,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; bool bypass_quirk; u8 bypass_cbndx; + u32 stall_enabled; }; static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) @@ -23,12 +24,17 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, u32 reg) { + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + /* * On the GPU device we want to process subsequent transactions after a * fault to keep the GPU from hanging */ reg |= ARM_SMMU_SCTLR_HUPCF; + if (qsmmu->stall_enabled & BIT(idx)) + reg |= ARM_SMMU_SCTLR_CFCFG; + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } @@ -48,6 +54,31 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie, info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); } +static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); + + if (enabled) + qsmmu->stall_enabled |= BIT(cfg->cbndx); + else + qsmmu->stall_enabled &= ~BIT(cfg->cbndx); +} + +static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + u32 reg = 0; + + if (terminate) + reg |= ARM_SMMU_RESUME_TERMINATE; + + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -173,6 +204,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; priv->get_fault_info = qcom_adreno_smmu_get_fault_info; + priv->set_stall = qcom_adreno_smmu_set_stall; + priv->resume_translation = qcom_adreno_smmu_resume_translation; return 0; } diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index 53fe32fb9214..c637e0997f6d 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -45,6 +45,11 @@ struct adreno_smmu_fault_info { * TTBR0 translation is enabled with the specified cfg * @get_fault_info: Called by the GPU fault handler to get information about * the fault + * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call + * before set_ttbr0_cfg(). If stalling on fault is enabled, + * the GPU driver must call resume_translation() + * @resume_translation: Resume translation after a fault + * * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -60,6 +65,8 @@ struct adreno_smmu_priv { const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); + void (*set_stall)(const void *cookie, bool enabled); + void (*resume_translation)(const void *cookie, bool terminate); }; #endif /* __ADRENO_SMMU_PRIV_H */