From patchwork Fri Jun 18 00:51:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12329959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCE10C49361 for ; Fri, 18 Jun 2021 00:52:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A753361209 for ; Fri, 18 Jun 2021 00:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233214AbhFRAyP (ORCPT ); Thu, 17 Jun 2021 20:54:15 -0400 Received: from mga05.intel.com ([192.55.52.43]:2051 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232959AbhFRAyO (ORCPT ); Thu, 17 Jun 2021 20:54:14 -0400 IronPort-SDR: viqBM1Q/JSwxUTNR0TPIGNjvZVreTB/GwdrFLMc+RYB4/3vzKfbHYr0QrQg+sfasDjTB7X4ch+ ZQumfE9FQp5w== X-IronPort-AV: E=McAfee;i="6200,9189,10018"; a="292105416" X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="292105416" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 IronPort-SDR: LNmyb2K+iyTY2+BotB385HeIsU4Fb5zMcM4JjM7597n641ZwB1KS3Ard6KVUq+9peSNYHW3CNJ Fz/nStlMMawQ== X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="622223113" Received: from mkalyani-mobl.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 1/5] cxl/region: Only allow CXL capable targets Date: Thu, 17 Jun 2021 17:51:56 -0700 Message-Id: <20210618005200.997804-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com> References: <20210618005200.997804-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A cxl_memdev exists for all CXL endpoints that support the CXL.io protocol. If that device cannot participate in CXL.mem protocol, then it cannot be part of a region's interleave set. The ABI allows setting a target which is currently not CXL.mem capable and only will fail when the binding to the region driver occurs. This is in line with the other configuration parameters which are only strictly validated when the driver gets bound to the region. Signed-off-by: Ben Widawsky --- drivers/cxl/mem.h | 5 +++++ drivers/cxl/region.c | 12 +++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h index ff1f9c57e089..3d51bf6c090f 100644 --- a/drivers/cxl/mem.h +++ b/drivers/cxl/mem.h @@ -84,4 +84,9 @@ struct cxl_mem { struct range ram_range; }; +static inline bool is_cxl_capable(struct cxl_memdev *cxlmd) +{ + return false; +} + #endif /* __CXL_MEM_H__ */ diff --git a/drivers/cxl/region.c b/drivers/cxl/region.c index 2e73ece001ec..837f4314ffcc 100644 --- a/drivers/cxl/region.c +++ b/drivers/cxl/region.c @@ -176,6 +176,10 @@ static size_t set_targetN(struct cxl_region *region, const char *buf, int n, siz return -ENOENT; cxlmd = to_cxl_memdev(memdev_dev); + if (!is_cxl_capable(cxlmd)) + dev_dbg(®ion->dev, + "Setting a target which doesn't support CXL.mem"); + get_device(&cxlmd->dev); region->targets[n] = cxlmd; @@ -432,11 +436,17 @@ static int bind_region(struct cxl_region *region) return -ENXIO; } - for (i = 0; i < region->eniw; i++) + for (i = 0; i < region->eniw; i++) { if (!region->targets[i]) { trace_cxl_region_bind(region, "Missing memory device target"); return -ENXIO; } + if (!is_cxl_capable(region->targets[i])) { + trace_cxl_region_bind(region, + "Target isn't CXL.mem capable"); + return -ENODEV; + } + } rc = allocate_region_addr(region); if (rc) From patchwork Fri Jun 18 00:51:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12329963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 560A8C49EA2 for ; Fri, 18 Jun 2021 00:52:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3AF1661209 for ; Fri, 18 Jun 2021 00:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232847AbhFRAyP (ORCPT ); Thu, 17 Jun 2021 20:54:15 -0400 Received: from mga05.intel.com ([192.55.52.43]:2051 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232883AbhFRAyP (ORCPT ); Thu, 17 Jun 2021 20:54:15 -0400 IronPort-SDR: hCTmPtc6Ih4VIYfkllhzy7ElbBrPn8ulOPrM8b0nKatjPy9W61TFX6vzywvYAMnGyIxdsSRuJw yEjmP/lr94Gw== X-IronPort-AV: E=McAfee;i="6200,9189,10018"; a="292105417" X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="292105417" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 IronPort-SDR: vvN94hcTO1i5SuIkW6idg0P6e6EnVcmyIErqlpSALjqRPKKN7gjXoAMx2x/R7cE5NA2MNc74rk 16RVaPA7ACaA== X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="622223117" Received: from mkalyani-mobl.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 2/5] cxl/mem: Introduce CXL mem driver Date: Thu, 17 Jun 2021 17:51:57 -0700 Message-Id: <20210618005200.997804-3-ben.widawsky@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com> References: <20210618005200.997804-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org CXL endpoints that participate in the CXL.mem protocol require extra control to ensure architectural constraints are met for device management. This driver will implement those controls. Signed-off-by: Ben Widawsky --- drivers/cxl/Makefile | 3 ++- drivers/cxl/core.c | 2 ++ drivers/cxl/cxl.h | 1 + drivers/cxl/mem.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/mem.h | 1 + drivers/cxl/pci.c | 5 +++++ 6 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 drivers/cxl/mem.c diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index f35077c073b8..1fc2836d4f12 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CXL_BUS) += cxl_core.o -obj-$(CONFIG_CXL_MEM) += cxl_pci.o cxl_region.o +obj-$(CONFIG_CXL_MEM) += cxl_pci.o cxl_region.o mem.o obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o @@ -10,3 +10,4 @@ cxl_pci-y := pci.o cxl_acpi-y := acpi.o cxl_pmem-y := pmem.o cxl_region-y := region.o +cxl_mem-y := mem.o diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index 5d81fba787e9..16a671722d4e 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -1098,6 +1098,8 @@ static int cxl_device_id(struct device *dev) return CXL_DEVICE_NVDIMM; if (is_cxl_region(dev)) return CXL_DEVICE_REGION; + if (is_cxl_memdev(dev)) + return CXL_DEVICE_ENDPOINT; return 0; } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b5b728155d86..ce4b241c5dda 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -328,6 +328,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv); #define CXL_DEVICE_NVDIMM_BRIDGE 1 #define CXL_DEVICE_NVDIMM 2 #define CXL_DEVICE_REGION 3 +#define CXL_DEVICE_ENDPOINT 4 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") #define CXL_MODALIAS_FMT "cxl:t%d" diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c new file mode 100644 index 000000000000..2997a03abcb6 --- /dev/null +++ b/drivers/cxl/mem.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2021 Intel Corporation. All rights reserved. */ +#include +#include +#include "mem.h" + +/** + * DOC: cxl mem + * + * CXL memory endpoint devices are CXL capable devices that are participating in + * CXL.mem protocol. Their functionality builds on top of the CXL.io protocol + * that allows enumerating and configuring a CXL endpoint via standard PCI + * mechanisms. + */ + +static int cxl_memdev_probe(struct device *dev) +{ + return -EOPNOTSUPP; +} + +static void cxl_memdev_remove(struct device *dev) +{ +} + +static struct cxl_driver cxl_memdev_driver = { + .name = "cxl_memdev", + .probe = cxl_memdev_probe, + .remove = cxl_memdev_remove, + .id = CXL_DEVICE_ENDPOINT, +}; + +static __init int cxl_memdev_init(void) +{ + return cxl_driver_register(&cxl_memdev_driver); +} + +static __exit void cxl_memdev_exit(void) +{ + cxl_driver_unregister(&cxl_memdev_driver); +} + +MODULE_LICENSE("GPL v2"); +module_init(cxl_memdev_init); +module_exit(cxl_memdev_exit); +MODULE_IMPORT_NS(CXL); diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h index 3d51bf6c090f..2c20c1ccd6b8 100644 --- a/drivers/cxl/mem.h +++ b/drivers/cxl/mem.h @@ -88,5 +88,6 @@ static inline bool is_cxl_capable(struct cxl_memdev *cxlmd) { return false; } +bool is_cxl_memdev(struct device *dev); #endif /* __CXL_MEM_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 379a106ada94..f9c0eaf3ff4e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1276,6 +1276,11 @@ static const struct device_type cxl_memdev_type = { .groups = cxl_memdev_attribute_groups, }; +bool is_cxl_memdev(struct device *dev) +{ + return dev->type == &cxl_memdev_type; +} + static void cxl_memdev_shutdown(struct cxl_memdev *cxlmd) { down_write(&cxl_memdev_rwsem); From patchwork Fri Jun 18 00:51:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12329961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0B25C48BE5 for ; Fri, 18 Jun 2021 00:52:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3E256120A for ; Fri, 18 Jun 2021 00:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232883AbhFRAyP (ORCPT ); Thu, 17 Jun 2021 20:54:15 -0400 Received: from mga05.intel.com ([192.55.52.43]:2051 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232889AbhFRAyP (ORCPT ); Thu, 17 Jun 2021 20:54:15 -0400 IronPort-SDR: /59NfB72BQEYnPx/Ul4ZCQBo5DKOu8Xeaj+z/jzKYS62avvRwgcTwjHknz8b/RI9IuiHYxjAxm znt4+yTxEdSA== X-IronPort-AV: E=McAfee;i="6200,9189,10018"; a="292105418" X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="292105418" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 IronPort-SDR: S7uElc/qAdDZzU8Cx8m5U8y3yGxxTpAO0XIpFdtWGEY4SGt66EMEvsrunagjstVVFYNVXErFcv NVRbPtr/zGrw== X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="622223121" Received: from mkalyani-mobl.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 3/5] cxl/memdev: Determine CXL.mem capability Date: Thu, 17 Jun 2021 17:51:58 -0700 Message-Id: <20210618005200.997804-4-ben.widawsky@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com> References: <20210618005200.997804-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org If the "upstream" port of the endpoint is an enumerated downstream CXL port the memdev driver can bind. This is useful for region configuration/creation because it provides a way for the region code to determine if the memdev is actually CXL capable. Signed-off-by: Ben Widawsky --- drivers/cxl/acpi.c | 9 ++++++++- drivers/cxl/core.c | 5 +++++ drivers/cxl/cxl.h | 1 + drivers/cxl/mem.c | 41 ++++++++++++++++++++++++++++++++++++++++- drivers/cxl/mem.h | 5 +---- 5 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index cf7c26fb2578..6192739fcf43 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -7,6 +7,7 @@ #include #include #include "cxl.h" +#include "mem.h" /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ #define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) @@ -398,9 +399,15 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (rc) goto out; - if (IS_ENABLED(CONFIG_CXL_PMEM)) + if (IS_ENABLED(CONFIG_CXL_PMEM)) { rc = device_for_each_child(&root_port->dev, root_port, add_root_nvdimm_bridge); + if (rc) + goto out; + } + + rc = bus_rescan_devices(&cxl_bus_type); + out: acpi_put_table(cedt_table); return rc; diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index 16a671722d4e..0a54c6eb84eb 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -303,6 +303,11 @@ static const struct device_type cxl_port_type = { .groups = cxl_port_attribute_groups, }; +bool is_cxl_port(struct device *dev) +{ + return dev->type == &cxl_port_type; +} + struct cxl_port *to_cxl_port(struct device *dev) { if (dev_WARN_ONCE(dev, dev->type != &cxl_port_type, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ce4b241c5dda..1a3800616f4a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -285,6 +285,7 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id, struct cxl_decoder *to_cxl_decoder(struct device *dev); bool is_root_decoder(struct device *dev); +bool is_cxl_port(struct device *dev); struct cxl_decoder * devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets, resource_size_t base, resource_size_t len, diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 2997a03abcb6..cbf18df24109 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -2,6 +2,7 @@ /* Copyright(c) 2021 Intel Corporation. All rights reserved. */ #include #include +#include #include "mem.h" /** @@ -13,9 +14,42 @@ * mechanisms. */ +static int port_match(struct device *dev, const void *data) +{ + struct cxl_dport *dport; + struct cxl_port *port; + int ret = 0; + + if (!is_cxl_port(dev)) + return 0; + + port = to_cxl_port(dev); + + device_lock(&port->dev); + list_for_each_entry(dport, &port->dports, list) + if (dport->dport == data) { + ret = 1; + break; + } + + device_unlock(&port->dev); + + return ret; +} + static int cxl_memdev_probe(struct device *dev) { - return -EOPNOTSUPP; + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_mem *cxlm = cxlmd->cxlm; + struct device *pdev_parent = cxlm->pdev->dev.parent; + struct device *port_dev; + + port_dev = + bus_find_device(&cxl_bus_type, NULL, pdev_parent, port_match); + if (!port_dev) + return -ENODEV; + + return 0; } static void cxl_memdev_remove(struct device *dev) @@ -29,6 +63,11 @@ static struct cxl_driver cxl_memdev_driver = { .id = CXL_DEVICE_ENDPOINT, }; +bool is_cxl_capable(struct cxl_memdev *cxlmd) +{ + return cxlmd->dev.driver == &cxl_memdev_driver.drv; +} + static __init int cxl_memdev_init(void) { return cxl_driver_register(&cxl_memdev_driver); diff --git a/drivers/cxl/mem.h b/drivers/cxl/mem.h index 2c20c1ccd6b8..e9333c2ea745 100644 --- a/drivers/cxl/mem.h +++ b/drivers/cxl/mem.h @@ -84,10 +84,7 @@ struct cxl_mem { struct range ram_range; }; -static inline bool is_cxl_capable(struct cxl_memdev *cxlmd) -{ - return false; -} +bool is_cxl_capable(struct cxl_memdev *cxlmd); bool is_cxl_memdev(struct device *dev); #endif /* __CXL_MEM_H__ */ From patchwork Fri Jun 18 00:51:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12329967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2DD4C49EA4 for ; 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d="scan'208";a="622223128" Received: from mkalyani-mobl.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:06 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 4/5] cxl/pci: Export CXL DVSEC functionality Date: Thu, 17 Jun 2021 17:51:59 -0700 Message-Id: <20210618005200.997804-5-ben.widawsky@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com> References: <20210618005200.997804-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Signed-off-by: Ben Widawsky --- drivers/cxl/pci.c | 2 +- drivers/cxl/pci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index f9c0eaf3ff4e..b1a5a18dba92 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -973,7 +973,7 @@ static void cxl_mem_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base) pci_iounmap(cxlm->pdev, base); } -static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) +int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) { int pos; diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h index dad7a831f65f..0d6f50f725bc 100644 --- a/drivers/cxl/pci.h +++ b/drivers/cxl/pci.h @@ -28,4 +28,6 @@ #define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) +int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec); + #endif /* __CXL_PCI_H__ */ From patchwork Fri Jun 18 00:52:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12329965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E31DC2B9F4 for ; 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d="scan'208";a="622223132" Received: from mkalyani-mobl.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.138.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 17:52:07 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Alison Schofield , Dan Williams , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable Date: Thu, 17 Jun 2021 17:52:00 -0700 Message-Id: <20210618005200.997804-6-ben.widawsky@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com> References: <20210618005200.997804-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Signed-off-by: Ben Widawsky --- drivers/cxl/mem.c | 18 ++++++++++++++++++ drivers/cxl/pci.h | 5 ++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index cbf18df24109..7f26937c7151 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -4,6 +4,7 @@ #include #include #include "mem.h" +#include "pci.h" /** * DOC: cxl mem @@ -41,14 +42,31 @@ static int cxl_memdev_probe(struct device *dev) { struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_mem *cxlm = cxlmd->cxlm; + struct pci_dev *pdev = cxlm->pdev; struct device *pdev_parent = cxlm->pdev->dev.parent; struct device *port_dev; + int pcie_dvsec; + u16 dvsec_ctrl; port_dev = bus_find_device(&cxl_bus_type, NULL, pdev_parent, port_match); if (!port_dev) return -ENODEV; + pcie_dvsec = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID); + if (!pcie_dvsec) { + dev_err(dev, "Unable to determine CXL protocol support"); + return -ENODEV; + } + + pci_read_config_word(pdev, + pcie_dvsec + PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET, + &dvsec_ctrl); + if (!(dvsec_ctrl & CXL_PCIE_MEM_ENABLE)) { + dev_err(dev, "CXL.cache protocol not supported on device"); + return -ENODEV; + } + return 0; } diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h index 0d6f50f725bc..ee26bc8c2ec8 100644 --- a/drivers/cxl/pci.h +++ b/drivers/cxl/pci.h @@ -11,7 +11,10 @@ */ #define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) #define PCI_DVSEC_VENDOR_ID_CXL 0x1E98 -#define PCI_DVSEC_ID_CXL 0x0 + +#define PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID 0x0 +#define PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET 0xC +#define CXL_PCIE_MEM_ENABLE BIT(2) #define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8 #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC