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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 10sm8352494pfh.174.2021.06.19.08.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Jun 2021 08:42:59 -0700 (PDT) Date: Sat, 19 Jun 2021 08:42:59 -0700 (PDT) X-Google-Original-Date: Sat, 19 Jun 2021 08:42:55 PDT (-0700) Subject: [GIT PULL] RISC-V Fixes for 5.13-rc7 CC: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: Linus Torvalds Message-ID: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210619_084301_067109_9A2F2ABC X-CRM114-Status: GOOD ( 10.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The following changes since commit 0ddd7eaffa644baa78e247bbd220ab7195b1eed6: riscv: Fix BUILTIN_DTB for sifive and microchip soc (2021-06-11 21:07:09 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.13-rc7 for you to fetch changes up to 7ede12b01b59dc67bef2e2035297dd2da5bfe427: riscv: dts: fu740: fix cache-controller interrupts (2021-06-19 00:11:53 -0700) ---------------------------------------------------------------- RISC-V Fixes for 5.13-rc7 * A build fix to always build modules with the medany code model, as the module loader doesn't support medlow. * A Kconfig warning fix for the SiFive errata. * A pair of fixes that for regressions to the recent memory layout changes. * A fix for the FU740 device tree. ---------------------------------------------------------------- David Abdurachmanov (1): riscv: dts: fu740: fix cache-controller interrupts Jisheng Zhang (2): riscv: kasan: Fix MODULES_VADDR evaluation due to local variables' name riscv: Ensure BPF_JIT_REGION_START aligned with PMD size Khem Raj (1): riscv32: Use medany C model for modules Randy Dunlap (1): riscv: sifive: fix Kconfig errata warning Documentation/riscv/vm-layout.rst | 4 ++-- arch/riscv/Kconfig.socs | 1 + arch/riscv/Makefile | 2 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- arch/riscv/include/asm/pgtable.h | 5 ++--- arch/riscv/mm/kasan_init.c | 10 +++++----- 6 files changed, 12 insertions(+), 12 deletions(-)