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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id 5sm727184oot.29.2021.06.22.13.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jun 2021 13:05:45 -0700 (PDT) From: trix@redhat.com To: hao.wu@intel.com, mdf@kernel.org, corbet@lwn.net, michal.simek@xilinx.com, gregkh@linuxfoundation.org, nava.manne@xilinx.com, dinguyen@kernel.org, krzysztof.kozlowski@canonical.com, yilun.xu@intel.com, davidgow@google.com, fpacheco@redhat.com, russell.h.weight@intel.com, richard.gong@intel.com, luca@lucaceresoli.net Cc: linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tom Rix Subject: [PATCH v5 1/4] fpga: dfl: reorganize to subdir layout Date: Tue, 22 Jun 2021 13:05:08 -0700 Message-Id: <20210622200511.3739914-3-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210622200511.3739914-1-trix@redhat.com> References: <20210622200511.3739914-1-trix@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210622_130551_505621_7AF0288C X-CRM114-Status: GOOD ( 29.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tom Rix Follow drivers/net/ethernet/ which has control configs NET_VENDOR_BLA that map to drivers/net/ethernet/bla Since fpgas do not have many vendors, drop the 'VENDOR' and use FPGA_BLA. There are several new subdirs altera/ dfl/ lattice/ xilinx/ Each subdir has a Kconfig that has a new/reused if FPGA_BLA ... existing configs ... endif FPGA_BLA Which is sourced into the main fpga/Kconfig Each subdir has a Makefile whose transversal is controlled in the fpga/Makefile by obj-$(CONFIG_FPGA_BLA) += bla/ This is the dfl/ subdir part. Create a dfl/ subdir Move dfl-* files to it. Add a Kconfig and Makefile Because FPGA_DFL is now used in dfl/Kconfig in a if/endif block, all the other configs in dfl/Kconfig implicitly depend on FPGA_DFL. Signed-off-by: Tom Rix --- Documentation/fpga/dfl.rst | 4 +- MAINTAINERS | 2 +- drivers/fpga/Kconfig | 80 +------------------- drivers/fpga/Makefile | 18 +---- drivers/fpga/dfl/Kconfig | 83 +++++++++++++++++++++ drivers/fpga/dfl/Makefile | 16 ++++ drivers/fpga/{ => dfl}/dfl-afu-dma-region.c | 0 drivers/fpga/{ => dfl}/dfl-afu-error.c | 0 drivers/fpga/{ => dfl}/dfl-afu-main.c | 0 drivers/fpga/{ => dfl}/dfl-afu-region.c | 0 drivers/fpga/{ => dfl}/dfl-afu.h | 0 drivers/fpga/{ => dfl}/dfl-fme-br.c | 0 drivers/fpga/{ => dfl}/dfl-fme-error.c | 0 drivers/fpga/{ => dfl}/dfl-fme-main.c | 0 drivers/fpga/{ => dfl}/dfl-fme-mgr.c | 0 drivers/fpga/{ => dfl}/dfl-fme-perf.c | 0 drivers/fpga/{ => dfl}/dfl-fme-pr.c | 0 drivers/fpga/{ => dfl}/dfl-fme-pr.h | 0 drivers/fpga/{ => dfl}/dfl-fme-region.c | 0 drivers/fpga/{ => dfl}/dfl-fme.h | 0 drivers/fpga/{ => dfl}/dfl-n3000-nios.c | 0 drivers/fpga/{ => dfl}/dfl-pci.c | 0 drivers/fpga/{ => dfl}/dfl.c | 0 drivers/fpga/{ => dfl}/dfl.h | 0 24 files changed, 104 insertions(+), 99 deletions(-) create mode 100644 drivers/fpga/dfl/Kconfig create mode 100644 drivers/fpga/dfl/Makefile rename drivers/fpga/{ => dfl}/dfl-afu-dma-region.c (100%) rename drivers/fpga/{ => dfl}/dfl-afu-error.c (100%) rename drivers/fpga/{ => dfl}/dfl-afu-main.c (100%) rename drivers/fpga/{ => dfl}/dfl-afu-region.c (100%) rename drivers/fpga/{ => dfl}/dfl-afu.h (100%) rename drivers/fpga/{ => dfl}/dfl-fme-br.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-error.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-main.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-mgr.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-perf.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-pr.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme-pr.h (100%) rename drivers/fpga/{ => dfl}/dfl-fme-region.c (100%) rename drivers/fpga/{ => dfl}/dfl-fme.h (100%) rename drivers/fpga/{ => dfl}/dfl-n3000-nios.c (100%) rename drivers/fpga/{ => dfl}/dfl-pci.c (100%) rename drivers/fpga/{ => dfl}/dfl.c (100%) rename drivers/fpga/{ => dfl}/dfl.h (100%) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3a..532fdc2e7d623 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -210,7 +210,7 @@ device and etc. Its driver module is always loaded first once the device is created by the system. This driver plays an infrastructural role in the driver architecture. It locates the DFLs in the device memory, handles them and related resources to common interfaces from DFL framework for enumeration. -(Please refer to drivers/fpga/dfl.c for detailed enumeration APIs). +(Please refer to drivers/fpga/dfl/dfl.c for detailed enumeration APIs). The FPGA Management Engine (FME) driver is a platform driver which is loaded automatically after FME platform device creation from the DFL device module. It @@ -499,7 +499,7 @@ In some cases, we may need to add some new private features to existing FIUs framework, as each private feature will be parsed automatically and related mmio resources can be found under FIU platform device created by DFL framework. Developer only needs to provide a sub feature driver with matched feature id. -FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) +FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl/dfl-fme-pr.c) could be a reference. Location of DFLs on a PCI Device diff --git a/MAINTAINERS b/MAINTAINERS index 9ae47618c857d..853997f755083 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7244,7 +7244,7 @@ L: linux-fpga@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-dfl* F: Documentation/fpga/dfl.rst -F: drivers/fpga/dfl* +F: drivers/fpga/dfl/ F: drivers/uio/uio_dfl.c F: include/linux/dfl.h F: include/uapi/linux/fpga-dfl.h diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 8cd454ee20c0c..7a290b2234576 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -145,85 +145,7 @@ config OF_FPGA_REGION Support for loading FPGA images by applying a Device Tree overlay. -config FPGA_DFL - tristate "FPGA Device Feature List (DFL) support" - select FPGA_BRIDGE - select FPGA_REGION - depends on HAS_IOMEM - help - Device Feature List (DFL) defines a feature list structure that - creates a linked list of feature headers within the MMIO space - to provide an extensible way of adding features for FPGA. - Driver can walk through the feature headers to enumerate feature - devices (e.g. FPGA Management Engine, Port and Accelerator - Function Unit) and their private features for target FPGA devices. - - Select this option to enable common support for Field-Programmable - Gate Array (FPGA) solutions which implement Device Feature List. - It provides enumeration APIs and feature device infrastructure. - -config FPGA_DFL_FME - tristate "FPGA DFL FME Driver" - depends on FPGA_DFL && HWMON && PERF_EVENTS - help - The FPGA Management Engine (FME) is a feature device implemented - under Device Feature List (DFL) framework. Select this option to - enable the platform device driver for FME which implements all - FPGA platform level management features. There shall be one FME - per DFL based FPGA device. - -config FPGA_DFL_FME_MGR - tristate "FPGA DFL FME Manager Driver" - depends on FPGA_DFL_FME && HAS_IOMEM - help - Say Y to enable FPGA Manager driver for FPGA Management Engine. - -config FPGA_DFL_FME_BRIDGE - tristate "FPGA DFL FME Bridge Driver" - depends on FPGA_DFL_FME && HAS_IOMEM - help - Say Y to enable FPGA Bridge driver for FPGA Management Engine. - -config FPGA_DFL_FME_REGION - tristate "FPGA DFL FME Region Driver" - depends on FPGA_DFL_FME && HAS_IOMEM - help - Say Y to enable FPGA Region driver for FPGA Management Engine. - -config FPGA_DFL_AFU - tristate "FPGA DFL AFU Driver" - depends on FPGA_DFL - help - This is the driver for FPGA Accelerated Function Unit (AFU) which - implements AFU and Port management features. A User AFU connects - to the FPGA infrastructure via a Port. There may be more than one - Port/AFU per DFL based FPGA device. - -config FPGA_DFL_NIOS_INTEL_PAC_N3000 - tristate "FPGA DFL NIOS Driver for Intel PAC N3000" - depends on FPGA_DFL - select REGMAP - help - This is the driver for the N3000 Nios private feature on Intel - PAC (Programmable Acceleration Card) N3000. It communicates - with the embedded Nios processor to configure the retimers on - the card. It also instantiates the SPI master (spi-altera) for - the card's BMC (Board Management Controller). - -config FPGA_DFL_PCI - tristate "FPGA DFL PCIe Device Driver" - depends on PCI && FPGA_DFL - help - Select this option to enable PCIe driver for PCIe-based - Field-Programmable Gate Array (FPGA) solutions which implement - the Device Feature List (DFL). This driver provides interfaces - for userspace applications to configure, enumerate, open and access - FPGA accelerators on the FPGA DFL devices, enables system level - management functions such as FPGA partial reconfiguration, power - management and virtualization with DFL framework and DFL feature - device drivers. - - To compile this as a module, choose M here. +source "drivers/fpga/dfl/Kconfig" config FPGA_MGR_ZYNQMP_FPGA tristate "Xilinx ZynqMP FPGA" diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 18dc9885883a2..bda74e54ce390 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -31,20 +31,4 @@ obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o obj-$(CONFIG_FPGA_REGION) += fpga-region.o obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o -# FPGA Device Feature List Support -obj-$(CONFIG_FPGA_DFL) += dfl.o -obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o -obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o -obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o -obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o -obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o - -dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o -dfl-fme-objs += dfl-fme-perf.o -dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o -dfl-afu-objs += dfl-afu-error.o - -obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o - -# Drivers for FPGAs which implement DFL -obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o +obj-$(CONFIG_FPGA_DFL) += dfl/ diff --git a/drivers/fpga/dfl/Kconfig b/drivers/fpga/dfl/Kconfig new file mode 100644 index 0000000000000..4c95e9072db46 --- /dev/null +++ b/drivers/fpga/dfl/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config FPGA_DFL + tristate "FPGA Device Feature List (DFL) support" + select FPGA_BRIDGE + select FPGA_REGION + depends on HAS_IOMEM + help + Device Feature List (DFL) defines a feature list structure that + creates a linked list of feature headers within the MMIO space + to provide an extensible way of adding features for FPGA. + Driver can walk through the feature headers to enumerate feature + devices (e.g. FPGA Management Engine, Port and Accelerator + Function Unit) and their private features for target FPGA devices. + + Select this option to enable common support for Field-Programmable + Gate Array (FPGA) solutions which implement Device Feature List. + It provides enumeration APIs and feature device infrastructure. + +if FPGA_DFL + +config FPGA_DFL_FME + tristate "FPGA DFL FME Driver" + depends on HWMON && PERF_EVENTS + help + The FPGA Management Engine (FME) is a feature device implemented + under Device Feature List (DFL) framework. Select this option to + enable the platform device driver for FME which implements all + FPGA platform level management features. There shall be one FME + per DFL based FPGA device. + +config FPGA_DFL_FME_MGR + tristate "FPGA DFL FME Manager Driver" + depends on FPGA_DFL_FME && HAS_IOMEM + help + Say Y to enable FPGA Manager driver for FPGA Management Engine. + +config FPGA_DFL_FME_BRIDGE + tristate "FPGA DFL FME Bridge Driver" + depends on FPGA_DFL_FME && HAS_IOMEM + help + Say Y to enable FPGA Bridge driver for FPGA Management Engine. + +config FPGA_DFL_FME_REGION + tristate "FPGA DFL FME Region Driver" + depends on FPGA_DFL_FME && HAS_IOMEM + help + Say Y to enable FPGA Region driver for FPGA Management Engine. + +config FPGA_DFL_AFU + tristate "FPGA DFL AFU Driver" + help + This is the driver for FPGA Accelerated Function Unit (AFU) which + implements AFU and Port management features. A User AFU connects + to the FPGA infrastructure via a Port. There may be more than one + Port/AFU per DFL based FPGA device. + +config FPGA_DFL_NIOS_INTEL_PAC_N3000 + tristate "FPGA DFL NIOS Driver for Intel PAC N3000" + select REGMAP + help + This is the driver for the N3000 Nios private feature on Intel + PAC (Programmable Acceleration Card) N3000. It communicates + with the embedded Nios processor to configure the retimers on + the card. It also instantiates the SPI master (spi-altera) for + the card's BMC (Board Management Controller). + +config FPGA_DFL_PCI + tristate "FPGA DFL PCIe Device Driver" + depends on PCI + help + Select this option to enable PCIe driver for PCIe-based + Field-Programmable Gate Array (FPGA) solutions which implement + the Device Feature List (DFL). This driver provides interfaces + for userspace applications to configure, enumerate, open and access + FPGA accelerators on the FPGA DFL devices, enables system level + management functions such as FPGA partial reconfiguration, power + management and virtualization with DFL framework and DFL feature + device drivers. + + To compile this as a module, choose M here. + +endif #FPGA_DFL diff --git a/drivers/fpga/dfl/Makefile b/drivers/fpga/dfl/Makefile new file mode 100644 index 0000000000000..1c22507c60aa0 --- /dev/null +++ b/drivers/fpga/dfl/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# FPGA Device Feature List (DFL) Support +obj-$(CONFIG_FPGA_DFL) += dfl.o +obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o +obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o +obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o +obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o +obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o +obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o +obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o + +dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o \ + dfl-fme-perf.o +dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o \ + dfl-afu-error.o diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl/dfl-afu-dma-region.c similarity index 100% rename from drivers/fpga/dfl-afu-dma-region.c rename to drivers/fpga/dfl/dfl-afu-dma-region.c diff --git a/drivers/fpga/dfl-afu-error.c b/drivers/fpga/dfl/dfl-afu-error.c similarity index 100% rename from drivers/fpga/dfl-afu-error.c rename to drivers/fpga/dfl/dfl-afu-error.c diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl/dfl-afu-main.c similarity index 100% rename from drivers/fpga/dfl-afu-main.c rename to drivers/fpga/dfl/dfl-afu-main.c diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl/dfl-afu-region.c similarity index 100% rename from drivers/fpga/dfl-afu-region.c rename to drivers/fpga/dfl/dfl-afu-region.c diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl/dfl-afu.h similarity index 100% rename from drivers/fpga/dfl-afu.h rename to drivers/fpga/dfl/dfl-afu.h diff --git a/drivers/fpga/dfl-fme-br.c b/drivers/fpga/dfl/dfl-fme-br.c similarity index 100% rename from drivers/fpga/dfl-fme-br.c rename to drivers/fpga/dfl/dfl-fme-br.c diff --git a/drivers/fpga/dfl-fme-error.c b/drivers/fpga/dfl/dfl-fme-error.c similarity index 100% rename from drivers/fpga/dfl-fme-error.c rename to drivers/fpga/dfl/dfl-fme-error.c diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl/dfl-fme-main.c similarity index 100% rename from drivers/fpga/dfl-fme-main.c rename to drivers/fpga/dfl/dfl-fme-main.c diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl/dfl-fme-mgr.c similarity index 100% rename from drivers/fpga/dfl-fme-mgr.c rename to drivers/fpga/dfl/dfl-fme-mgr.c diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl/dfl-fme-perf.c similarity index 100% rename from drivers/fpga/dfl-fme-perf.c rename to drivers/fpga/dfl/dfl-fme-perf.c diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl/dfl-fme-pr.c similarity index 100% rename from drivers/fpga/dfl-fme-pr.c rename to drivers/fpga/dfl/dfl-fme-pr.c diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl/dfl-fme-pr.h similarity index 100% rename from drivers/fpga/dfl-fme-pr.h rename to drivers/fpga/dfl/dfl-fme-pr.h diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl/dfl-fme-region.c similarity index 100% rename from drivers/fpga/dfl-fme-region.c rename to drivers/fpga/dfl/dfl-fme-region.c diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl/dfl-fme.h similarity index 100% rename from drivers/fpga/dfl-fme.h rename to drivers/fpga/dfl/dfl-fme.h diff --git a/drivers/fpga/dfl-n3000-nios.c b/drivers/fpga/dfl/dfl-n3000-nios.c similarity index 100% rename from drivers/fpga/dfl-n3000-nios.c rename to drivers/fpga/dfl/dfl-n3000-nios.c diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl/dfl-pci.c similarity index 100% rename from drivers/fpga/dfl-pci.c rename to drivers/fpga/dfl/dfl-pci.c diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl/dfl.c similarity index 100% rename from drivers/fpga/dfl.c rename to drivers/fpga/dfl/dfl.c diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl/dfl.h similarity index 100% rename from drivers/fpga/dfl.h rename to drivers/fpga/dfl/dfl.h From patchwork Tue Jun 22 20:05:09 2021 Content-Type: text/plain; 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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id 5sm727184oot.29.2021.06.22.13.05.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jun 2021 13:05:48 -0700 (PDT) From: trix@redhat.com To: hao.wu@intel.com, mdf@kernel.org, corbet@lwn.net, michal.simek@xilinx.com, gregkh@linuxfoundation.org, nava.manne@xilinx.com, dinguyen@kernel.org, krzysztof.kozlowski@canonical.com, yilun.xu@intel.com, davidgow@google.com, fpacheco@redhat.com, russell.h.weight@intel.com, richard.gong@intel.com, luca@lucaceresoli.net Cc: linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tom Rix Subject: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout Date: Tue, 22 Jun 2021 13:05:09 -0700 Message-Id: <20210622200511.3739914-4-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210622200511.3739914-1-trix@redhat.com> References: <20210622200511.3739914-1-trix@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210622_130552_905105_B5436B7E X-CRM114-Status: GOOD ( 21.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tom Rix Follow drivers/net/ethernet/ which has control configs NET_VENDOR_BLA that map to drivers/net/ethernet/bla Since fpgas do not have many vendors, drop the 'VENDOR' and use FPGA_BLA. There are several new subdirs altera/ dfl/ lattice/ xilinx/ Each subdir has a Kconfig that has a new/reused if FPGA_BLA ... existing configs ... endif FPGA_BLA Which is sourced into the main fpga/Kconfig Each subdir has a Makefile whose transversal is controlled in the fpga/Makefile by obj-$(CONFIG_FPGA_BLA) += bla/ This is the xilinx/ subdir part Create a xilinx/ subdir Move xilinx-* and zynq* files to it. Add a Kconfig and Makefile Signed-off-by: Tom Rix --- drivers/fpga/Kconfig | 40 +------------- drivers/fpga/Makefile | 5 +- drivers/fpga/xilinx/Kconfig | 55 +++++++++++++++++++ drivers/fpga/xilinx/Makefile | 6 ++ .../fpga/{ => xilinx}/xilinx-pr-decoupler.c | 0 drivers/fpga/{ => xilinx}/xilinx-spi.c | 0 drivers/fpga/{ => xilinx}/zynq-fpga.c | 0 drivers/fpga/{ => xilinx}/zynqmp-fpga.c | 0 8 files changed, 63 insertions(+), 43 deletions(-) create mode 100644 drivers/fpga/xilinx/Kconfig create mode 100644 drivers/fpga/xilinx/Makefile rename drivers/fpga/{ => xilinx}/xilinx-pr-decoupler.c (100%) rename drivers/fpga/{ => xilinx}/xilinx-spi.c (100%) rename drivers/fpga/{ => xilinx}/zynq-fpga.c (100%) rename drivers/fpga/{ => xilinx}/zynqmp-fpga.c (100%) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 7a290b2234576..28c261807b428 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -52,25 +52,12 @@ config FPGA_MGR_ALTERA_CVP FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. -config FPGA_MGR_ZYNQ_FPGA - tristate "Xilinx Zynq FPGA" - depends on ARCH_ZYNQ || COMPILE_TEST - help - FPGA manager driver support for Xilinx Zynq FPGAs. - config FPGA_MGR_STRATIX10_SOC tristate "Intel Stratix10 SoC FPGA Manager" depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE) help FPGA manager driver support for the Intel Stratix10 SoC. -config FPGA_MGR_XILINX_SPI - tristate "Xilinx Configuration over Slave Serial (SPI)" - depends on SPI - help - FPGA manager driver support for Xilinx FPGA configuration - over slave serial interface. - config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI @@ -113,23 +100,6 @@ config ALTERA_FREEZE_BRIDGE isolate one region of the FPGA from the busses while that region is being reprogrammed. -config XILINX_PR_DECOUPLER - tristate "Xilinx LogiCORE PR Decoupler" - depends on FPGA_BRIDGE - depends on HAS_IOMEM - help - Say Y to enable drivers for Xilinx LogiCORE PR Decoupler - or Xilinx Dynamic Function eXchnage AIX Shutdown Manager. - The PR Decoupler exists in the FPGA fabric to isolate one - region of the FPGA from the busses while that region is - being reprogrammed during partial reconfig. - The Dynamic Function eXchange AXI shutdown manager prevents - AXI traffic from passing through the bridge. The controller - safely handles AXI4MM and AXI4-Lite interfaces on a - Reconfigurable Partition when it is undergoing dynamic - reconfiguration, preventing the system deadlock that can - occur if AXI transactions are interrupted by DFX. - config FPGA_REGION tristate "FPGA Region" depends on FPGA_BRIDGE @@ -146,14 +116,6 @@ config OF_FPGA_REGION overlay. source "drivers/fpga/dfl/Kconfig" - -config FPGA_MGR_ZYNQMP_FPGA - tristate "Xilinx ZynqMP FPGA" - depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) - help - FPGA manager driver support for Xilinx ZynqMP FPGAs. - This driver uses the processor configuration port(PCAP) - to configure the programmable logic(PL) through PS - on ZynqMP SoC. +source "drivers/fpga/xilinx/Kconfig" endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index bda74e54ce390..0868c7c4264d8 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -15,9 +15,6 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o -obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o -obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o -obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o @@ -25,10 +22,10 @@ obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o -obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o obj-$(CONFIG_FPGA_DFL) += dfl/ +obj-$(CONFIG_FPGA_XILINX) += xilinx/ diff --git a/drivers/fpga/xilinx/Kconfig b/drivers/fpga/xilinx/Kconfig new file mode 100644 index 0000000000000..b907f9793195c --- /dev/null +++ b/drivers/fpga/xilinx/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config FPGA_XILINX + bool "Xilinx FPGAs" + default y + help + If you have a Xilinx FPGA, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Xilinx FPGAs. If you say Y, you will be asked + for your specific device in the following questions. + +if FPGA_XILINX + +config FPGA_MGR_ZYNQ_FPGA + tristate "Xilinx Zynq FPGA" + depends on ARCH_ZYNQ || COMPILE_TEST + help + FPGA manager driver support for Xilinx Zynq FPGAs. + +config FPGA_MGR_ZYNQMP_FPGA + tristate "Xilinx ZynqMP FPGA" + depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) + help + FPGA manager driver support for Xilinx ZynqMP FPGAs. + This driver uses the processor configuration port(PCAP) + to configure the programmable logic(PL) through PS + on ZynqMP SoC. + +config XILINX_PR_DECOUPLER + tristate "Xilinx LogiCORE PR Decoupler" + depends on FPGA_BRIDGE + depends on HAS_IOMEM + help + Say Y to enable drivers for Xilinx LogiCORE PR Decoupler + or Xilinx Dynamic Function eXchnage AIX Shutdown Manager. + The PR Decoupler exists in the FPGA fabric to isolate one + region of the FPGA from the busses while that region is + being reprogrammed during partial reconfig. + The Dynamic Function eXchange AXI shutdown manager prevents + AXI traffic from passing through the bridge. The controller + safely handles AXI4MM and AXI4-Lite interfaces on a + Reconfigurable Partition when it is undergoing dynamic + reconfiguration, preventing the system deadlock that can + occur if AXI transactions are interrupted by DFX. + +config FPGA_MGR_XILINX_SPI + tristate "Xilinx Configuration over Slave Serial (SPI)" + depends on SPI + help + FPGA manager driver support for Xilinx FPGA configuration + over slave serial interface. + +endif #FPGA_XILINX diff --git a/drivers/fpga/xilinx/Makefile b/drivers/fpga/xilinx/Makefile new file mode 100644 index 0000000000000..2361aa14eb549 --- /dev/null +++ b/drivers/fpga/xilinx/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx/xilinx-pr-decoupler.c similarity index 100% rename from drivers/fpga/xilinx-pr-decoupler.c rename to drivers/fpga/xilinx/xilinx-pr-decoupler.c diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx/xilinx-spi.c similarity index 100% rename from drivers/fpga/xilinx-spi.c rename to drivers/fpga/xilinx/xilinx-spi.c diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/xilinx/zynq-fpga.c similarity index 100% rename from drivers/fpga/zynq-fpga.c rename to drivers/fpga/xilinx/zynq-fpga.c diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/xilinx/zynqmp-fpga.c similarity index 100% rename from drivers/fpga/zynqmp-fpga.c rename to drivers/fpga/xilinx/zynqmp-fpga.c From patchwork Tue Jun 22 20:05:10 2021 Content-Type: text/plain; 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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id 5sm727184oot.29.2021.06.22.13.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jun 2021 13:05:52 -0700 (PDT) From: trix@redhat.com To: hao.wu@intel.com, mdf@kernel.org, corbet@lwn.net, michal.simek@xilinx.com, gregkh@linuxfoundation.org, nava.manne@xilinx.com, dinguyen@kernel.org, krzysztof.kozlowski@canonical.com, yilun.xu@intel.com, davidgow@google.com, fpacheco@redhat.com, russell.h.weight@intel.com, richard.gong@intel.com, luca@lucaceresoli.net Cc: linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tom Rix Subject: [PATCH v5 3/4] fpga: altera: reorganize to subdir layout Date: Tue, 22 Jun 2021 13:05:10 -0700 Message-Id: <20210622200511.3739914-5-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210622200511.3739914-1-trix@redhat.com> References: <20210622200511.3739914-1-trix@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210622_130556_970026_4D575450 X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tom Rix Follow drivers/net/ethernet/ which has control configs NET_VENDOR_BLA that map to drivers/net/ethernet/bla Since fpgas do not have many vendors, drop the 'VENDOR' and use FPGA_BLA. There are several new subdirs altera/ dfl/ lattice/ xilinx/ Each subdir has a Kconfig that has a new/reused if FPGA_BLA ... existing configs ... endif FPGA_BLA Which is sourced into the main fpga/Kconfig Each subdir has a Makefile whose transversal is controlled in the fpga/Makefile by obj-$(CONFIG_FPGA_BLA) += bla/ This is the altera/ subdir part. Create a altera/ subdir Move altera-* and soc* ts73xx* files to it. Add a Kconfig and Makefile Signed-off-by: Tom Rix --- drivers/fpga/Kconfig | 70 +-------------- drivers/fpga/Makefile | 11 +-- drivers/fpga/altera/Kconfig | 85 +++++++++++++++++++ drivers/fpga/altera/Makefile | 12 +++ drivers/fpga/{ => altera}/altera-cvp.c | 0 drivers/fpga/{ => altera}/altera-fpga2sdram.c | 0 .../fpga/{ => altera}/altera-freeze-bridge.c | 0 drivers/fpga/{ => altera}/altera-hps2fpga.c | 0 .../{ => altera}/altera-pr-ip-core-plat.c | 0 drivers/fpga/{ => altera}/altera-pr-ip-core.c | 0 drivers/fpga/{ => altera}/altera-ps-spi.c | 0 drivers/fpga/{ => altera}/socfpga-a10.c | 0 drivers/fpga/{ => altera}/socfpga.c | 0 drivers/fpga/{ => altera}/stratix10-soc.c | 0 drivers/fpga/{ => altera}/ts73xx-fpga.c | 0 15 files changed, 99 insertions(+), 79 deletions(-) create mode 100644 drivers/fpga/altera/Kconfig create mode 100644 drivers/fpga/altera/Makefile rename drivers/fpga/{ => altera}/altera-cvp.c (100%) rename drivers/fpga/{ => altera}/altera-fpga2sdram.c (100%) rename drivers/fpga/{ => altera}/altera-freeze-bridge.c (100%) rename drivers/fpga/{ => altera}/altera-hps2fpga.c (100%) rename drivers/fpga/{ => altera}/altera-pr-ip-core-plat.c (100%) rename drivers/fpga/{ => altera}/altera-pr-ip-core.c (100%) rename drivers/fpga/{ => altera}/altera-ps-spi.c (100%) rename drivers/fpga/{ => altera}/socfpga-a10.c (100%) rename drivers/fpga/{ => altera}/socfpga.c (100%) rename drivers/fpga/{ => altera}/stratix10-soc.c (100%) rename drivers/fpga/{ => altera}/ts73xx-fpga.c (100%) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 28c261807b428..2c829b1105925 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -12,52 +12,6 @@ menuconfig FPGA if FPGA -config FPGA_MGR_SOCFPGA - tristate "Altera SOCFPGA FPGA Manager" - depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST - help - FPGA manager driver support for Altera SOCFPGA. - -config FPGA_MGR_SOCFPGA_A10 - tristate "Altera SoCFPGA Arria10" - depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST - select REGMAP_MMIO - help - FPGA manager driver support for Altera Arria10 SoCFPGA. - -config ALTERA_PR_IP_CORE - tristate "Altera Partial Reconfiguration IP Core" - help - Core driver support for Altera Partial Reconfiguration IP component - -config ALTERA_PR_IP_CORE_PLAT - tristate "Platform support of Altera Partial Reconfiguration IP Core" - depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM - help - Platform driver support for Altera Partial Reconfiguration IP - component - -config FPGA_MGR_ALTERA_PS_SPI - tristate "Altera FPGA Passive Serial over SPI" - depends on SPI - select BITREVERSE - help - FPGA manager driver support for Altera Arria/Cyclone/Stratix - using the passive serial interface over SPI. - -config FPGA_MGR_ALTERA_CVP - tristate "Altera CvP FPGA Manager" - depends on PCI - help - FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, - Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. - -config FPGA_MGR_STRATIX10_SOC - tristate "Intel Stratix10 SoC FPGA Manager" - depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE) - help - FPGA manager driver support for the Intel Stratix10 SoC. - config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI @@ -71,35 +25,12 @@ config FPGA_MGR_MACHXO2_SPI FPGA manager driver support for Lattice MachXO2 configuration over slave SPI interface. -config FPGA_MGR_TS73XX - tristate "Technologic Systems TS-73xx SBC FPGA Manager" - depends on ARCH_EP93XX && MACH_TS72XX - help - FPGA manager driver support for the Altera Cyclone II FPGA - present on the TS-73xx SBC boards. - config FPGA_BRIDGE tristate "FPGA Bridge Framework" help Say Y here if you want to support bridges connected between host processors and FPGAs or between FPGAs. -config SOCFPGA_FPGA_BRIDGE - tristate "Altera SoCFPGA FPGA Bridges" - depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE - help - Say Y to enable drivers for FPGA bridges for Altera SOCFPGA - devices. - -config ALTERA_FREEZE_BRIDGE - tristate "Altera FPGA Freeze Bridge" - depends on FPGA_BRIDGE && HAS_IOMEM - help - Say Y to enable drivers for Altera FPGA Freeze bridges. A - freeze bridge is a bridge that exists in the FPGA fabric to - isolate one region of the FPGA from the busses while that - region is being reprogrammed. - config FPGA_REGION tristate "FPGA Region" depends on FPGA_BRIDGE @@ -115,6 +46,7 @@ config OF_FPGA_REGION Support for loading FPGA images by applying a Device Tree overlay. +source "drivers/fpga/altera/Kconfig" source "drivers/fpga/dfl/Kconfig" source "drivers/fpga/xilinx/Kconfig" diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 0868c7c4264d8..db83aeb997f24 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -7,25 +7,16 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers -obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o -obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o -obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o -obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o -obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o -obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o -obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o -obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o -obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o -obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o +obj-$(CONFIG_FPGA_ALTERA) += altera/ obj-$(CONFIG_FPGA_DFL) += dfl/ obj-$(CONFIG_FPGA_XILINX) += xilinx/ diff --git a/drivers/fpga/altera/Kconfig b/drivers/fpga/altera/Kconfig new file mode 100644 index 0000000000000..7075c6dc48e44 --- /dev/null +++ b/drivers/fpga/altera/Kconfig @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config FPGA_ALTERA + bool "Altera FPGAs" + default y + help + If you have an Altera FPGA, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Altera FPGAs. If you say Y, you will be asked + for your specific device in the following questions. + +if FPGA_ALTERA + +config FPGA_MGR_SOCFPGA + tristate "Altera SOCFPGA FPGA Manager" + depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST + help + FPGA manager driver support for Altera SOCFPGA. + +config FPGA_MGR_SOCFPGA_A10 + tristate "Altera SoCFPGA Arria10" + depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST + select REGMAP_MMIO + help + FPGA manager driver support for Altera Arria10 SoCFPGA. + +config ALTERA_PR_IP_CORE + tristate "Altera Partial Reconfiguration IP Core" + help + Core driver support for Altera Partial Reconfiguration IP component + +config ALTERA_PR_IP_CORE_PLAT + tristate "Platform support of Altera Partial Reconfiguration IP Core" + depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM + help + Platform driver support for Altera Partial Reconfiguration IP + component + +config FPGA_MGR_ALTERA_PS_SPI + tristate "Altera FPGA Passive Serial over SPI" + depends on SPI + select BITREVERSE + help + FPGA manager driver support for Altera Arria/Cyclone/Stratix + using the passive serial interface over SPI. + +config FPGA_MGR_ALTERA_CVP + tristate "Altera CvP FPGA Manager" + depends on PCI + help + FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, + Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. + +config FPGA_MGR_STRATIX10_SOC + tristate "Intel Stratix10 SoC FPGA Manager" + depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE) + help + FPGA manager driver support for the Intel Stratix10 SoC. + +config FPGA_MGR_TS73XX + tristate "Technologic Systems TS-73xx SBC FPGA Manager" + depends on ARCH_EP93XX && MACH_TS72XX + help + FPGA manager driver support for the Altera Cyclone II FPGA + present on the TS-73xx SBC boards. + +config ALTERA_FREEZE_BRIDGE + tristate "Altera FPGA Freeze Bridge" + depends on FPGA_BRIDGE && HAS_IOMEM + help + Say Y to enable drivers for Altera FPGA Freeze bridges. A + freeze bridge is a bridge that exists in the FPGA fabric to + isolate one region of the FPGA from the busses while that + region is being reprogrammed. + +config SOCFPGA_FPGA_BRIDGE + tristate "Altera SoCFPGA FPGA Bridges" + depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE + help + Say Y to enable drivers for FPGA bridges for Altera SOCFPGA + devices. + +endif #FPGA_ALTERA diff --git a/drivers/fpga/altera/Makefile b/drivers/fpga/altera/Makefile new file mode 100644 index 0000000000000..9c86057cff110 --- /dev/null +++ b/drivers/fpga/altera/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o +obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o +obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o +obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o +obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o +obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o +obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o +obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o +obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera/altera-cvp.c similarity index 100% rename from drivers/fpga/altera-cvp.c rename to drivers/fpga/altera/altera-cvp.c diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera/altera-fpga2sdram.c similarity index 100% rename from drivers/fpga/altera-fpga2sdram.c rename to drivers/fpga/altera/altera-fpga2sdram.c diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera/altera-freeze-bridge.c similarity index 100% rename from drivers/fpga/altera-freeze-bridge.c rename to drivers/fpga/altera/altera-freeze-bridge.c diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera/altera-hps2fpga.c similarity index 100% rename from drivers/fpga/altera-hps2fpga.c rename to drivers/fpga/altera/altera-hps2fpga.c diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera/altera-pr-ip-core-plat.c similarity index 100% rename from drivers/fpga/altera-pr-ip-core-plat.c rename to drivers/fpga/altera/altera-pr-ip-core-plat.c diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera/altera-pr-ip-core.c similarity index 100% rename from drivers/fpga/altera-pr-ip-core.c rename to drivers/fpga/altera/altera-pr-ip-core.c diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera/altera-ps-spi.c similarity index 100% rename from drivers/fpga/altera-ps-spi.c rename to drivers/fpga/altera/altera-ps-spi.c diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/altera/socfpga-a10.c similarity index 100% rename from drivers/fpga/socfpga-a10.c rename to drivers/fpga/altera/socfpga-a10.c diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/altera/socfpga.c similarity index 100% rename from drivers/fpga/socfpga.c rename to drivers/fpga/altera/socfpga.c diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/altera/stratix10-soc.c similarity index 100% rename from drivers/fpga/stratix10-soc.c rename to drivers/fpga/altera/stratix10-soc.c diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/altera/ts73xx-fpga.c similarity index 100% rename from drivers/fpga/ts73xx-fpga.c rename to drivers/fpga/altera/ts73xx-fpga.c From patchwork Tue Jun 22 20:05:11 2021 Content-Type: text/plain; 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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id 5sm727184oot.29.2021.06.22.13.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jun 2021 13:05:56 -0700 (PDT) From: trix@redhat.com To: hao.wu@intel.com, mdf@kernel.org, corbet@lwn.net, michal.simek@xilinx.com, gregkh@linuxfoundation.org, nava.manne@xilinx.com, dinguyen@kernel.org, krzysztof.kozlowski@canonical.com, yilun.xu@intel.com, davidgow@google.com, fpacheco@redhat.com, russell.h.weight@intel.com, richard.gong@intel.com, luca@lucaceresoli.net Cc: linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tom Rix Subject: [PATCH v5 4/4] fpga: lattice: reorganize to subdir layout Date: Tue, 22 Jun 2021 13:05:11 -0700 Message-Id: <20210622200511.3739914-6-trix@redhat.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210622200511.3739914-1-trix@redhat.com> References: <20210622200511.3739914-1-trix@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210622_130601_639780_AEFFE3B1 X-CRM114-Status: GOOD ( 18.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tom Rix Follow drivers/net/ethernet/ which has control configs NET_VENDOR_BLA that map to drivers/net/ethernet/bla Since fpgas do not have many vendors, drop the 'VENDOR' and use FPGA_BLA. There are several new subdirs altera/ dfl/ lattice/ xilinx/ Each subdir has a Kconfig that has a new/reused if FPGA_BLA ... existing configs ... endif FPGA_BLA Which is sourced into the main fpga/Kconfig Each subdir has a Makefile whose transversal is controlled in the fpga/Makefile by obj-$(CONFIG_FPGA_BLA) += bla/ This is the lattice/ subdir part. Create a lattice/ subdir Move ice40* and machxo2* files to it. Add a Kconfig and Makefile Signed-off-by: Tom Rix --- drivers/fpga/Kconfig | 14 +----------- drivers/fpga/Makefile | 13 ++++------- drivers/fpga/lattice/Kconfig | 29 ++++++++++++++++++++++++ drivers/fpga/lattice/Makefile | 4 ++++ drivers/fpga/{ => lattice}/ice40-spi.c | 0 drivers/fpga/{ => lattice}/machxo2-spi.c | 0 6 files changed, 39 insertions(+), 21 deletions(-) create mode 100644 drivers/fpga/lattice/Kconfig create mode 100644 drivers/fpga/lattice/Makefile rename drivers/fpga/{ => lattice}/ice40-spi.c (100%) rename drivers/fpga/{ => lattice}/machxo2-spi.c (100%) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 2c829b1105925..955b155da3575 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -12,19 +12,6 @@ menuconfig FPGA if FPGA -config FPGA_MGR_ICE40_SPI - tristate "Lattice iCE40 SPI" - depends on OF && SPI - help - FPGA manager driver support for Lattice iCE40 FPGAs over SPI. - -config FPGA_MGR_MACHXO2_SPI - tristate "Lattice MachXO2 SPI" - depends on SPI - help - FPGA manager driver support for Lattice MachXO2 configuration - over slave SPI interface. - config FPGA_BRIDGE tristate "FPGA Bridge Framework" help @@ -48,6 +35,7 @@ config OF_FPGA_REGION source "drivers/fpga/altera/Kconfig" source "drivers/fpga/dfl/Kconfig" +source "drivers/fpga/lattice/Kconfig" source "drivers/fpga/xilinx/Kconfig" endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index db83aeb997f24..9197698201e3a 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -4,19 +4,16 @@ # # Core FPGA Manager Framework -obj-$(CONFIG_FPGA) += fpga-mgr.o - -# FPGA Manager Drivers -obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o -obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o +obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Bridge Drivers -obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o +obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o # High Level Interfaces -obj-$(CONFIG_FPGA_REGION) += fpga-region.o -obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o +obj-$(CONFIG_FPGA_REGION) += fpga-region.o +obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o obj-$(CONFIG_FPGA_ALTERA) += altera/ obj-$(CONFIG_FPGA_DFL) += dfl/ +obj-$(CONFIG_FPGA_LATTICE) += lattice/ obj-$(CONFIG_FPGA_XILINX) += xilinx/ diff --git a/drivers/fpga/lattice/Kconfig b/drivers/fpga/lattice/Kconfig new file mode 100644 index 0000000000000..47f5a0c62aa4e --- /dev/null +++ b/drivers/fpga/lattice/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config FPGA_LATTICE + bool "Lattice FPGAs" + default y + help + If you have a Lattice FPGA, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Lattice FPGAs. If you say Y, you will be asked + for your specific device in the following questions. + +if FPGA_LATTICE + +config FPGA_MGR_ICE40_SPI + tristate "Lattice iCE40 SPI" + depends on OF && SPI + help + FPGA manager driver support for Lattice iCE40 FPGAs over SPI. + +config FPGA_MGR_MACHXO2_SPI + tristate "Lattice MachXO2 SPI" + depends on SPI + help + FPGA manager driver support for Lattice MachXO2 configuration + over slave SPI interface. + +endif #FPGA_LATTICE diff --git a/drivers/fpga/lattice/Makefile b/drivers/fpga/lattice/Makefile new file mode 100644 index 0000000000000..f542c96a73d40 --- /dev/null +++ b/drivers/fpga/lattice/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/lattice/ice40-spi.c similarity index 100% rename from drivers/fpga/ice40-spi.c rename to drivers/fpga/lattice/ice40-spi.c diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/lattice/machxo2-spi.c similarity index 100% rename from drivers/fpga/machxo2-spi.c rename to drivers/fpga/lattice/machxo2-spi.c