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Wed, 23 Jun 2021 19:20:32 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam , x86@kernel.org Subject: [PATCH v2 01/31] x86/MCE/AMD, EDAC/amd64: Move address translation to AMD64 EDAC Date: Wed, 23 Jun 2021 19:19:32 +0000 Message-Id: <20210623192002.3671647-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pfpuL45o/4SEVRto372l4mKULEny7CwmqYpJCEhhPI/LGml3iOw0OTO0xQjdR9DgKpFkln5hEVrinZuyBE9hNmwj2ecBmA9fQqrQYQq44rKu/vUwZVxcKz7kAPPxsMzOzNJmn9V9U6WwCJZIDAqzU8Lh0hUA9BzW9urPmy5sERrgqTBy+Y40GboYwS1tcOOdEV5y6aIMgiSYSDeV6BEXan9/sI2pBpgfKOSPpVaj3iG6WbdF1i2SONWpXWVNu6p4PF0A4LaRTxNXj8s0ixU/rYJXr+TsABV5l405Iy82r/ApXKtDHwxLDt62wWBsdRB9Xs2GMJqXfYrVNXjOcUttExQ1/v5/UWoiJSifSsQnlVviOAAkNx7flcq8Hmzl9xuZb+hf73GqZXI3ITM0AvuUHkNrCFKVqmtTZfoSfylmeO8sfvjj9eEVQ+Xe+74UZaMQBkU5e08tYwgfpc026rrZAMA2Y+KgWu3LSDoBT3S68+YcnZ7JR0iQqtzffs6sm8eOwNKHPda46saHVllVJW/cTpi0cp2V4uV+bJTDga0VypjdgDVmdlxmDJixHIilHSaezutpwFKYkcRxglAtVN+2H550bcElXY/hR5OXve3+8deWasxuLLWW/YNlRLQ2uO6bSrkPDrD41aY+dz0HYOXL5v+zIiM/PrDsZDn7wcSt6kYGdFMGXs5bHe0vVVsF/3XstApT9iqKae4zhBM/eiPxNf5r1YOuLeApwRPn9W8k0vI6tlgBuFrBEhsbgJ/7/qv0xZfkZIJG+4nokaytqgGvK7aM1UHSjajVTc+gv2JSWAD2QLTz+95PDj56XBVrgkUFQKZXoQChRGGW8Ee1OeXggynqyaRFCKCHun32miAW33tW4j8/FEg/756t43tvcSHA9fZHKlUclgLoV8v763nFjAs6vZoc4NV28YCB3B6vyJp7TuIzEhaDVw9QdIcTjnp9QHHSkRL9pdq7uoC69/o1rRkEiGUYfiatE4rd+kVxLAF5c2vSdp00ZpbGBAxPNXVEo1VedEfypQ3js68MlLkXNURqGlitSGO0fNSpPmPpe2082R7voEimj/BrL80HglHKpa9tbQFL0ZFsF20y3/gjlrkGOdOihHngkqgFmMD+JbmMoq/eBZg1CP1eOJ/8zqjkd7GdxahJXqHCrX7q1Ew68tIywdocEwQRi5zsj4dp2ougGqZy5kPKEDCGjQEj3dRWETJ5HBFiltwckjGe2ZKlNNJ9VJpf+RBR8KUs8o4nlIi7IY/lnaM90ZxF9kvSUdz70lTqP6Fm2AlV63zu5zXiTEAKl0hgnmcIKzjon4IX8tBDbYITpVUOeXRtSJ59QDt7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ae6e1ff-c512-4a1b-c9e9-08d9367bf868 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:32.7759 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +tEHvDuFz2tpqy5Iit0VGNN9AiLw7UccZ5R7LFhp5WQBkdqf0G/zE023BXfattJrCbr9NvyFlLtov6HJKyrryA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The address translation code used for current AMD systems is non-architectural. So move it to EDAC. Cc: Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/YKJoICQzD/o7ZPBp@zn.tnic v1->v2: * New in v2. arch/x86/include/asm/mce.h | 3 - arch/x86/kernel/cpu/mce/amd.c | 200 ---------------------------------- drivers/edac/amd64_edac.c | 199 +++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+), 203 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 2ac265e832de..a547ab5b0532 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -357,7 +357,6 @@ extern int mce_threshold_create_device(unsigned int cpu); extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); -int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr); #else @@ -365,8 +364,6 @@ static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } -static inline int -umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; }; #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1a2a90bd29e7..ce881f32ca41 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -689,206 +689,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } -int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) -{ - u64 dram_base_addr, dram_limit_addr, dram_hole_base; - /* We start from the normalized address */ - u64 ret_addr = norm_addr; - - u32 tmp; - - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en, base = 0; - u8 cs_mask, cs_id = 0; - bool hash_enabled = false; - - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) - goto out_err; - - /* Remove HiAddrOffset from normalized address, if enabled: */ - if (tmp & BIT(0)) { - u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; - - if (norm_addr >= hi_addr_offset) { - ret_addr -= hi_addr_offset; - base = 1; - } - } - - /* Read D18F0x110 (DramBaseAddress). */ - if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) - goto out_err; - - /* Check if address range is valid. */ - if (!(tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, tmp); - goto out_err; - } - - lgcy_mmio_hole_en = tmp & BIT(1); - intlv_num_chan = (tmp >> 4) & 0xF; - intlv_addr_sel = (tmp >> 8) & 0x7; - dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; - - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); - goto out_err; - } - - /* Read D18F0x114 (DramLimitAddress). */ - if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) - goto out_err; - - intlv_num_sockets = (tmp >> 8) & 0x1; - intlv_num_dies = (tmp >> 10) & 0x3; - dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - - intlv_addr_bit = intlv_addr_sel + 8; - - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ - switch (intlv_num_chan) { - case 0: intlv_num_chan = 0; break; - case 1: intlv_num_chan = 1; break; - case 3: intlv_num_chan = 2; break; - case 5: intlv_num_chan = 3; break; - case 7: intlv_num_chan = 4; break; - - case 8: intlv_num_chan = 1; - hash_enabled = true; - break; - default: - pr_err("%s: Invalid number of interleaved channels %d.\n", - __func__, intlv_num_chan); - goto out_err; - } - - num_intlv_bits = intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); - goto out_err; - } - - num_intlv_bits += intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; - - /* Assert num_intlv_bits <= 4 */ - if (num_intlv_bits > 4) { - pr_err("%s: Invalid interleave bits %d.\n", - __func__, num_intlv_bits); - goto out_err; - } - - if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; - u8 die_id_bit, sock_id_bit, cs_fabric_id; - - /* - * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. - * This is the fabric id for this coherent slave. Use - * umc/channel# as instance id of the coherent slave - * for FICAA. - */ - if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) - goto out_err; - - cs_fabric_id = (tmp >> 8) & 0xFF; - die_id_bit = 0; - - /* If interleaved over more than 1 channel: */ - if (intlv_num_chan) { - die_id_bit = intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; - } - - sock_id_bit = die_id_bit; - - /* Read D18F1x208 (SystemFabricIdMask). */ - if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) - goto out_err; - - /* If interleaved over more than 1 die. */ - if (intlv_num_dies) { - sock_id_bit = die_id_bit + intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; - - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; - } - - /* If interleaved over more than 1 socket. */ - if (intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; - - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; - } - - /* - * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). - */ - temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; - } - - /* Add dram base address */ - ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) - goto out_err; - - dram_hole_base = tmp & GENMASK(31, 24); - if (ret_addr >= dram_hole_base) - ret_addr += (BIT_ULL(32) - dram_hole_base); - } - - if (hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ret_addr >> 12) ^ - (ret_addr >> 18) ^ - (ret_addr >> 21) ^ - (ret_addr >> 30) ^ - cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); - } - - /* Is calculated system address is above DRAM limit address? */ - if (ret_addr > dram_limit_addr) - goto out_err; - - *sys_addr = ret_addr; - return 0; - -out_err: - return -EINVAL; -} -EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); - bool amd_mce_is_memory_error(struct mce *m) { /* ErrCodeExt[20:16] */ diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f0d8f60acee1..046b98fcc4fe 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -993,6 +993,205 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + /* We start from the normalized address */ + u64 ret_addr = norm_addr; + + u32 tmp; + + u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 intlv_addr_sel, intlv_addr_bit; + u8 num_intlv_bits, hashed_bit; + u8 lgcy_mmio_hole_en, base = 0; + u8 cs_mask, cs_id = 0; + bool hash_enabled = false; + + /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ + if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) + goto out_err; + + /* Remove HiAddrOffset from normalized address, if enabled: */ + if (tmp & BIT(0)) { + u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; + + if (norm_addr >= hi_addr_offset) { + ret_addr -= hi_addr_offset; + base = 1; + } + } + + /* Read D18F0x110 (DramBaseAddress). */ + if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) + goto out_err; + + /* Check if address range is valid. */ + if (!(tmp & BIT(0))) { + pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", + __func__, tmp); + goto out_err; + } + + lgcy_mmio_hole_en = tmp & BIT(1); + intlv_num_chan = (tmp >> 4) & 0xF; + intlv_addr_sel = (tmp >> 8) & 0x7; + dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; + + /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ + if (intlv_addr_sel > 3) { + pr_err("%s: Invalid interleave address select %d.\n", + __func__, intlv_addr_sel); + goto out_err; + } + + /* Read D18F0x114 (DramLimitAddress). */ + if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) + goto out_err; + + intlv_num_sockets = (tmp >> 8) & 0x1; + intlv_num_dies = (tmp >> 10) & 0x3; + dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + + intlv_addr_bit = intlv_addr_sel + 8; + + /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ + switch (intlv_num_chan) { + case 0: intlv_num_chan = 0; break; + case 1: intlv_num_chan = 1; break; + case 3: intlv_num_chan = 2; break; + case 5: intlv_num_chan = 3; break; + case 7: intlv_num_chan = 4; break; + + case 8: intlv_num_chan = 1; + hash_enabled = true; + break; + default: + pr_err("%s: Invalid number of interleaved channels %d.\n", + __func__, intlv_num_chan); + goto out_err; + } + + num_intlv_bits = intlv_num_chan; + + if (intlv_num_dies > 2) { + pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", + __func__, intlv_num_dies); + goto out_err; + } + + num_intlv_bits += intlv_num_dies; + + /* Add a bit if sockets are interleaved. */ + num_intlv_bits += intlv_num_sockets; + + /* Assert num_intlv_bits <= 4 */ + if (num_intlv_bits > 4) { + pr_err("%s: Invalid interleave bits %d.\n", + __func__, num_intlv_bits); + goto out_err; + } + + if (num_intlv_bits > 0) { + u64 temp_addr_x, temp_addr_i, temp_addr_y; + u8 die_id_bit, sock_id_bit, cs_fabric_id; + + /* + * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. + * This is the fabric id for this coherent slave. Use + * umc/channel# as instance id of the coherent slave + * for FICAA. + */ + if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) + goto out_err; + + cs_fabric_id = (tmp >> 8) & 0xFF; + die_id_bit = 0; + + /* If interleaved over more than 1 channel: */ + if (intlv_num_chan) { + die_id_bit = intlv_num_chan; + cs_mask = (1 << die_id_bit) - 1; + cs_id = cs_fabric_id & cs_mask; + } + + sock_id_bit = die_id_bit; + + /* Read D18F1x208 (SystemFabricIdMask). */ + if (intlv_num_dies || intlv_num_sockets) + if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + goto out_err; + + /* If interleaved over more than 1 die. */ + if (intlv_num_dies) { + sock_id_bit = die_id_bit + intlv_num_dies; + die_id_shift = (tmp >> 24) & 0xF; + die_id_mask = (tmp >> 8) & 0xFF; + + cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + } + + /* If interleaved over more than 1 socket. */ + if (intlv_num_sockets) { + socket_id_shift = (tmp >> 28) & 0xF; + socket_id_mask = (tmp >> 16) & 0xFF; + + cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + } + + /* + * The pre-interleaved address consists of XXXXXXIIIYYYYY + * where III is the ID for this CS, and XXXXXXYYYYY are the + * address bits from the post-interleaved address. + * "num_intlv_bits" has been calculated to tell us how many "I" + * bits there are. "intlv_addr_bit" tells us how many "Y" bits + * there are (where "I" starts). + */ + temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); + temp_addr_i = (cs_id << intlv_addr_bit); + temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; + ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + } + + /* Add dram base address */ + ret_addr += dram_base_addr; + + /* If legacy MMIO hole enabled */ + if (lgcy_mmio_hole_en) { + if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) + goto out_err; + + dram_hole_base = tmp & GENMASK(31, 24); + if (ret_addr >= dram_hole_base) + ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + if (hash_enabled) { + /* Save some parentheses and grab ls-bit at the end. */ + hashed_bit = (ret_addr >> 12) ^ + (ret_addr >> 18) ^ + (ret_addr >> 21) ^ + (ret_addr >> 30) ^ + cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) + ret_addr ^= BIT(intlv_addr_bit); + } + + /* Is calculated system address is above DRAM limit address? */ + if (ret_addr > dram_limit_addr) + goto out_err; + + *sys_addr = ret_addr; + return 0; + +out_err: + return -EINVAL; +} + static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); /* From patchwork Wed Jun 23 19:19:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74460C4743C for ; Wed, 23 Jun 2021 19:20:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 55BB360FF4 for ; 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dmarc=none action=none header.from=amd.com; Received: from BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) by BN6PR12MB1187.namprd12.prod.outlook.com (2603:10b6:404:1b::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19; Wed, 23 Jun 2021 19:20:37 +0000 Received: from BN8PR12MB3108.namprd12.prod.outlook.com ([fe80::c099:e7a1:249a:a8a2]) by BN8PR12MB3108.namprd12.prod.outlook.com ([fe80::c099:e7a1:249a:a8a2%7]) with mapi id 15.20.4242.025; Wed, 23 Jun 2021 19:20:36 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam , x86@kernel.org Subject: [PATCH v2 02/31] x86/amd_nb, EDAC/amd64: Move DF Indirect Read to AMD64 EDAC Date: Wed, 23 Jun 2021 19:19:33 +0000 Message-Id: <20210623192002.3671647-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WQy3b52S+gUaAnNOH/h4F7yWi7D8wNY0ytlzF3W2IdXVRXsryyRlk/dbAL5tILVAFezeg8bUaem4AXuke7CSQLZ1NbiSfZJ1F9RlP2BNJu4su4C2pyC36uxfHfR63fySLzRRGW7du0kfQg/hIN74Typomn4etrobf7atgRdecKYN/+LXQYoi9vG03wxX/IZJs7+dEIFDlJxmIJFTtZyKqv4CeKqaaaJjDeFROi/LxOBFtTemSseL0TPJtX66Byz3uEo+vupk+zN0ik/jN4MVYEfWoihpeRq2nL1ydr1YkoNXL47NIlGO0VbS0bs+Yytp70cO7hofVxvX6nnG28ynlQlOmaGZxgXEt9y8FRcJPKXitxI0k8TtZ2CEYF+d0mfoOEN3yuQMu1kToAQQYHy1s2VLuFDEjtwYqZwFttKaNyJvtt2uuzZyd6Hs/ZnWpVzWO4m9/dsvfXqEE80Q10olUTaaMbkio8g1t6uCQkSNievyk5cVKlNrFE4tFXxUlTyl5mtgTuLE1jo9FEqxtE/dq6EigPzcIKeyGZSHoqBBe9QzGyfcodEsYwP6Up38DtCt9Kxqh4vHRaZAzAcclz7i8hcSVR54AINu+FBWM2h+kO75C+/OeIXF2TyAr+sgzqGaNZHxF5JJAaq82qrs6a8tr/wmudZWsqYgVdJKsCUAnf3Qcf5KW7WNVqa91nKhAzht4jP9aP5LOUYw4unCMfXKI0m8HvwZthe43WrEM5s7wseK+igWORrEr5WmXX5Z4YM8fDQbOzvxZmymuGWdCjR9cWbldOY5I7IGg9p4kdO+vL36jT7nFkhjhony2bBYzOmwbTNSfyTvuOCCuwnATsQ8PXm8dWlkfs8TNihrxj6RxNRDNcvkMaTNYAXP2ZSQ8r3eNaoJliOGYQrJ9ykOwCjURJgKj3upCYxBW8eyuBdndT8zQ6467F6iXaPaTGjG5aBfWgutcWMAlOkNEV2JpHXh5/zUKmUlSfS8HyQeDKNzPZJKdJCl8+bs8Bdvhtxf7GDPAEjEB/PGNx7RPx4Qc4PQCcPLqgSwtRhoImiTNRtFG5jOpySnaEzeAPpxFOekjB8IZcOl/V49jef0i0zriaTkuZYAGu8NRXtFY6dfiwW6tMwBGLzedea7WJaIgUuo8IDwSXjXT+3Rw4IilR4deg/V2qnopsjXp5G+w387NwOysYBRaVnqCNRxeBKkMUpZO//qi1s4QA+Mpp78D16gH1jI5VGC+ChpTEmjYhFdZjda2vU7mCP2FTn36QGxU5A0jMXNiMxHJc6n7pHYn+1SIkot3qn9RN9dQ5hy7RLtK5jBH29GfIro8qqkSMPAKKHfp2lU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e14d03bf-5fa1-49c7-da3d-08d9367bfad4 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:36.8225 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NTdCxOee/ypNsIRmbwJ0opmcbC7Il57OHTrEAiIaAWiFPTSW1P0Ci/MRzKHtWJISYKExeYao2xm3rnBv5jk8PA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The df_indirect_read() function is only used for address translation. Move this to EDAC along with the translation code. Cc: Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/YKJoICQzD/o7ZPBp@zn.tnic v1->v2: * New in v2. arch/x86/include/asm/amd_nb.h | 1 - arch/x86/kernel/amd_nb.c | 50 +---------------------------------- drivers/edac/amd64_edac.c | 50 +++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 50 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 455066a06f60..00d1a400b7a1 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -24,7 +24,6 @@ extern int amd_set_subcaches(int, unsigned long); extern int amd_smn_read(u16 node, u32 address, u32 *value); extern int amd_smn_write(u16 node, u32 address, u32 value); -extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); struct amd_l3_cache { unsigned indices; diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 23dda362dc0f..5884dfa619ff 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -27,7 +27,7 @@ #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e -/* Protect the PCI config register pairs used for SMN and DF indirect access. */ +/* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); static u32 *flush_words; @@ -177,54 +177,6 @@ int amd_smn_write(u16 node, u32 address, u32 value) } EXPORT_SYMBOL_GPL(amd_smn_write); -/* - * Data Fabric Indirect Access uses FICAA/FICAD. - * - * Fabric Indirect Configuration Access Address (FICAA): Constructed based - * on the device's Instance Id and the PCI function and register offset of - * the desired register. - * - * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO - * and FICAD HI registers but so far we only need the LO register. - */ -int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) -{ - struct pci_dev *F4; - u32 ficaa; - int err = -ENODEV; - - if (node >= amd_northbridges.num) - goto out; - - F4 = node_to_amd_nb(node)->link; - if (!F4) - goto out; - - ficaa = 1; - ficaa |= reg & 0x3FC; - ficaa |= (func & 0x7) << 11; - ficaa |= instance_id << 16; - - mutex_lock(&smn_mutex); - - err = pci_write_config_dword(F4, 0x5C, ficaa); - if (err) { - pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); - goto out_unlock; - } - - err = pci_read_config_dword(F4, 0x98, lo); - if (err) - pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); - -out_unlock: - mutex_unlock(&smn_mutex); - -out: - return err; -} -EXPORT_SYMBOL_GPL(amd_df_indirect_read); - int amd_cache_northbridges(void) { const struct pci_device_id *misc_ids = amd_nb_misc_ids; diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 046b98fcc4fe..e9342d7d693f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -993,6 +993,56 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* Protect the PCI config register pairs used for DF indirect access. */ +static DEFINE_MUTEX(df_indirect_mutex); + +/* + * Data Fabric Indirect Access uses FICAA/FICAD. + * + * Fabric Indirect Configuration Access Address (FICAA): Constructed based + * on the device's Instance Id and the PCI function and register offset of + * the desired register. + * + * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO + * and FICAD HI registers but so far we only need the LO register. + */ +static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +{ + struct pci_dev *F4; + u32 ficaa; + int err = -ENODEV; + + if (node >= amd_nb_num()) + goto out; + + F4 = node_to_amd_nb(node)->link; + if (!F4) + goto out; + + ficaa = 1; + ficaa |= reg & 0x3FC; + ficaa |= (func & 0x7) << 11; + ficaa |= instance_id << 16; + + mutex_lock(&df_indirect_mutex); + + err = pci_write_config_dword(F4, 0x5C, ficaa); + if (err) { + pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); + goto out_unlock; + } + + err = pci_read_config_dword(F4, 0x98, lo); + if (err) + pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); + +out_unlock: + mutex_unlock(&df_indirect_mutex); + +out: + return err; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; From patchwork Wed Jun 23 19:19:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE850C48BC2 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K0aiUdBaZgjvE1yxJQxyWpGX50Qs3KIj63NXvmeleIgPdKze6/ZTrEmfFZLs+RTs2mSeaBtqjgtjMAEWe02FQaqdvXkKPnrKxOSorlqUE+Aaom9fsPkLztVeaueJracZ4+3an1x9hY1cStfrcHeKjShrrrIFvOnH7hMli8LuhBdKdJjEiBfQ9Kr4++uwR2dZ9ZiJvKW28oAmk67eXQTiFsW9gMcKTso7+IyHPUIs6Gc4CNd8cWykU0s4fXF46VV1neXU5Lnpm55i2hO6lM8bki2qOC2K0W1k7HCcJ8YlbXeJofO01cTCm8cAeOEPVo+An/D4lTujzeczkMrug17X6KywfSJAoC7eS56Epe9GGuUBVDWJMK8fFhZMAoLRf+XqueTmXYPTARIzH5i+Klop4XgXk2bfFXjdY5ZDwpyVNxDTWgqoNx5IMu/LGUw9PVzD9d84INIgMSnsH/SI9O3jGDZ27NHxQtDk4GKf2yL4/0of4227a6fVZr1xayFZkWMOT3LyTN9Lib4mSPl6Buvw0Beh/8EU1oD7/r6dm3J8bYQ0A89QSJwxM1Y6bXjoTXuHHft7xaBzEwIYwz4PUoTeH5EyMdyNMj+Ov6WglBd8Ak+Ws6823kC4DE/++mbmByWh8eImb4m38pKZPcDG4LDqRA2Y5NTUIsXvPfVqMeTTu8BizofYvklh3f9bDSS3Z19ktN3iml7teXrCR48V/Nwm3L0TQKDSbMdqpSGDPO3h64+pr1pEdRX+l4oUyrFPg6dVzcloappH7QsDa1iFdg/qFooznqE+/XpW0e67JuChHnc1txeKF9zigNu+pcKsmuO+OyBHo600j+elZU5vVy/nwvohDXV4NmkDYTaYwTRyP4YVAwxF4kjboOyfEVmHnvR7FDJNFu1uv1xaf9+RaWkXyreQpIRV8S9FJgbiBr23Sh2fg/OVUBPRNmWEHufKpuIphntlq7JDe6t/xdDybvkiNI30wrefAMkpvbAf2P/a/UPOk5eR1hyA4xmd9Z1nKABG4AYEDfYx7uTFIdyzWtCjDN2yQ136CGIavj4fkabWBm1FGeDiJeLO4yLLKgSPuf5VaF7PYiuJxPHOJG66yU1iG+DGDAGHctEbvqLPa3og99jLS06178foTyeeflt35Wlt4pbxb8xfoKXb+0psXq/pb+0R3RGTO5s662gP+jbBpb6SYKl56R2MKqHuEUH56tXuEvG3BLFm99C3wuW7nS3+bzrENG6jddFWml5Ry681ub0h5oUZ9pILEc2L/jZyxIjjcPFtpt6TJrDwdCJ6qJ6wNRjMsVr5at1h5mMoDDRlUTpDZh82BBowvZHGe7SbcECZ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a0e7ce57-58c4-404e-ff1d-08d9367bfcd7 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:40.1966 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QvfExIq6L1CvoDDA7ZJAAVCoONXwByLDFTL6e2tmb9tMLpYyqDvcgqJG2/m9p5nsKUMVgQsahitbbEhGu7qI0Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org AMD Data Fabric registers are defined using a combination of PCI function number and offset. Define a struct to hold these values, and update the DF Indirect Access function to accept a struct of this type. Update the address translation code to include a list of the needed DF registers using this new format. Define an enumeration to give the registers more human-readable names. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-2-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 60 ++++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e9342d7d693f..b94067e3952b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -996,6 +996,11 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* Protect the PCI config register pairs used for DF indirect access. */ static DEFINE_MUTEX(df_indirect_mutex); +struct df_reg { + u8 func; + u16 offset; +}; + /* * Data Fabric Indirect Access uses FICAA/FICAD. * @@ -1006,7 +1011,7 @@ static DEFINE_MUTEX(df_indirect_mutex); * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO * and FICAD HI registers but so far we only need the LO register. */ -static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +static int amd_df_indirect_read(u16 node, struct df_reg reg, u8 instance_id, u32 *lo) { struct pci_dev *F4; u32 ficaa; @@ -1020,8 +1025,8 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 goto out; ficaa = 1; - ficaa |= reg & 0x3FC; - ficaa |= (func & 0x7) << 11; + ficaa |= reg.offset & 0x3FC; + ficaa |= (reg.func & 0x7) << 11; ficaa |= instance_id << 16; mutex_lock(&df_indirect_mutex); @@ -1043,6 +1048,33 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 return err; } +enum df_reg_names { + /* Function 0 */ + FAB_BLK_INST_INFO_3, + DRAM_HOLE_CTL, + DRAM_BASE_ADDR, + DRAM_LIMIT_ADDR, + DRAM_OFFSET, + + /* Function 1 */ + SYS_FAB_ID_MASK, +}; + +static struct df_reg df_regs[] = { + /* D18F0x50 (FabricBlockInstanceInformation3_CS) */ + [FAB_BLK_INST_INFO_3] = {0, 0x50}, + /* D18F0x104 (DramHoleControl) */ + [DRAM_HOLE_CTL] = {0, 0x104}, + /* D18F0x110 (DramBaseAddress) */ + [DRAM_BASE_ADDR] = {0, 0x110}, + /* D18F0x114 (DramLimitAddress) */ + [DRAM_LIMIT_ADDR] = {0, 0x114}, + /* D18F0x1B4 (DramOffset) */ + [DRAM_OFFSET] = {0, 0x1B4}, + /* D18F1x208 (SystemFabricIdMask) */ + [SYS_FAB_ID_MASK] = {1, 0x208}, +}; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1059,8 +1091,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 cs_mask, cs_id = 0; bool hash_enabled = false; - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) + struct df_reg reg; + + if (amd_df_indirect_read(nid, df_regs[DRAM_OFFSET], umc, &tmp)) goto out_err; /* Remove HiAddrOffset from normalized address, if enabled: */ @@ -1073,8 +1106,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } } - /* Read D18F0x110 (DramBaseAddress). */ - if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) + reg = df_regs[DRAM_BASE_ADDR]; + reg.offset += base * 8; + if (amd_df_indirect_read(nid, reg, umc, &tmp)) goto out_err; /* Check if address range is valid. */ @@ -1096,8 +1130,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x114 (DramLimitAddress). */ - if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) + reg = df_regs[DRAM_LIMIT_ADDR]; + reg.offset += base * 8; + if (amd_df_indirect_read(nid, reg, umc, &tmp)) goto out_err; intlv_num_sockets = (tmp >> 8) & 0x1; @@ -1153,7 +1188,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[FAB_BLK_INST_INFO_3], umc, &tmp)) goto out_err; cs_fabric_id = (tmp >> 8) & 0xFF; @@ -1168,9 +1203,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr sock_id_bit = die_id_bit; - /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[SYS_FAB_ID_MASK], umc, &tmp)) goto out_err; /* If interleaved over more than 1 die. */ @@ -1209,7 +1243,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr /* If legacy MMIO hole enabled */ if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[DRAM_HOLE_CTL], umc, &tmp)) goto out_err; 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Wed, 23 Jun 2021 19:20:42 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 04/31] EDAC/amd64: Allow for DF Indirect Broadcast reads Date: Wed, 23 Jun 2021 19:19:35 +0000 Message-Id: <20210623192002.3671647-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jrP/SQqsp4TylvPCPAwVmlElbnkJSeQzbTzcCfYr4uXhWZVOA/X2c6hmmnYlth2assajJuQc8YsP0bzQZlL95aa8kDMu8jPKw5mkQbKJQH7HQtx2yCuigCDiZIh/gzmuP4P1XdsrnhEzqRvj27Mdtl6ZnBjGOZEjZIkJxY8COBaYl31Jza6+hcxZCrrywW6R5lRHdAL7JjuwHpOj0TQTNmsMoGbWMOMRF4hjQMKqrhNbZvAaw3j/xj2xG1lzAGL4L09bmfJBunyqfTXA29CsGf3tCK4jnrbi6UsxUxYrVNO4gCpy2isCf4+46hA24KDJBeeS8Bw+Me7vyqap4AW63JDjb2pmRM2a7IOFPDQc4wxcwqZoilEh1yAyzMBEI6L4ZkuRZ73H+Jg3TTQ3fJaVu3u1rYLq8Q94GBaKfE4wFQdzQkC71XWe9mfaPRfKN9iRpqAItkvnOBZAIbbkq47WFJv0r7JpwdxRLqlLOWqXXAmsx2SAm2OqehZW/oDtN6qsB4DUR/qTjtNgnLsv4GHGNFGDhXGhSc0TToqSYLFcQEtBQLlPWtSpW6G+nFfKR0BKSVOLIk6sV5oDjb+9GDxFlaOarPYwVUFvAChOkGQ6DRa6CxxflDP3OEBopBH6eXaDvw3ca+IyqPaFginQQYygL3Uw4Zbjhvc8c4S3lzDCi3B90OUrwRekyUuWUr48Pg14Aru+YmTxLwCuH3Gy7gIdAzB/+1uB/ydmCKO7Vw81JcTclE17J/Xx+/dzoJjfM5Hafn4mr2ybqxe8bqSKaNvvpo88D/9FjFp+lKKMgqGD7jgtOBeOBNsHL9Xv/9VeRATkUm4P7heMFv65zpfOSjdpdf55n2uzaluTHOrtShO9cwpvJwzYis+wg/Qbj1bQazSBWcMbvR0aFUZ+Ty0yr6JrcjKihwQsjrTOR9kwd44R2W9bdLR564x9Mle8MK/Bc+d1OlhwyGcCqUitERJPMFaEKsQnetRsw1VLFqpRFJq7x/RjyGXIbWFj0J5EEIaM0qGUsAgn9qMI5hDAT9nqOhvixk570B5DE97RroH3eadMjk2e0lbPlbuLLu/G7vvx+olqyVuYtttxL4GApCCrn2T7elnFkvaf3y6IaAmO2+y0uYLxvaeL37lHMmxwwylNNssGD7Jlm4VLWFpKVW2PjTiyHI8TlsPVPcUud6nTDOPQqaNbpZ1Bn8H2n0eFPNM1OnEXlR2vheGsIWImQbLzdnacswQAWqI47M4cuHxnNys8HQ6PqJBqrRy9OLR5VqiTqvvkWMqlfOUYbByKkho683N2sQ6jhw4p4CXC31UNNrg9uxi1y63PbBMYyEnvZtuTX/Hk X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c5cebf7d-8873-4558-4b1f-08d9367bfde7 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:42.0005 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 37U7pIR3XZeqXTjloFpG3sErtfGFIl0SdmkhcWGnAr6y6Nj9cK8zdm9qRwZBtPBD2qEP+eMcupD+Q75oGvRNZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The DF Indirect Access method allows for "Broadcast" accesses in which case no specific instance is targeted. Add support using a reserved instance ID of 0xFF to indicate a broadcast access. Set the FICAA register appropriately. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-1-Yazen.Ghannam@amd.com v1->v2: * New in v2. drivers/edac/amd64_edac.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b94067e3952b..d67cd8f57b94 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1010,7 +1010,11 @@ struct df_reg { * * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO * and FICAD HI registers but so far we only need the LO register. + * + * Use Instance Id 0xFF to indicate a broadcast read. */ + +#define DF_BROADCAST 0xFF static int amd_df_indirect_read(u16 node, struct df_reg reg, u8 instance_id, u32 *lo) { struct pci_dev *F4; @@ -1024,7 +1028,7 @@ static int amd_df_indirect_read(u16 node, struct df_reg reg, u8 instance_id, u32 if (!F4) goto out; - ficaa = 1; + ficaa = (instance_id == DF_BROADCAST) ? 0 : 1; ficaa |= reg.offset & 0x3FC; ficaa |= (reg.func & 0x7) << 11; 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Wed, 23 Jun 2021 19:20:42 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 05/31] EDAC/amd64: Add context struct Date: Wed, 23 Jun 2021 19:19:36 +0000 Message-Id: <20210623192002.3671647-6-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: y/ZtNZscaWHAh4bUYPR09JsA658fUHFax3kb2ajiiSFiSSOlgbrAt4DmzxvpJEwAfBSwA+Xfq5Ap7v3MnTsObMj7GaBgby+G1GTVraPW5QjZUe5ySvXXFPosL289ixUOn0gl2W9M2PcydDqqeAct+mtv/xxc3i/y7Lu/Ix6tGXCOTIz/2JGMTxB8V7a4rJtFeNT59pMzCoVrjxZ5uJxh+1I9j4+/U981Us/zy/bJGazqGpnRsSEatMouJtrlRjw6pFRcK7SQXiZXXxxj5TJHNRbYH1HxuFt1PS717PXifVq3bNVjd2L82O7xhiYCPuGyNPges3w4ZdrgjAGe7tA9wfQGeeB46vEEVriqsSBCwvmiYAqRNXA1kcYbEOhOZuY31q57FyWqwzCIxMCR01LxoLvetTEG1UqXT4vedq6poVsQTih4af7WSm3/FBDdhEq2SCcs8nPeUO2RC20zaooXl+AEnmToeZHyD9VwfKOSoSvCw4Nt981CuQ5ZyBJW2oHZBNmYy77cSi/gj/dedf3TVzGMOMzWElWFM5HBziKrVKPWfxR7fvHzJvjU4skiyQCc/B3ppqOrnImTBE3yE+yUDpG2MkAWXHytUt6KaWdR1HkTeNG+kGxaTj0scPLF0PHQNRuLD8uxRRVhWuExy7l/VMM5oPW7L+txr1OPpUHbkVlyejP4GikeV81NLQmc7k1F+iiYmpE0d5Z+vaQXH0VcXpzn+xdj/KkwKj3zqYmhuAeovvF8T9CHedNFtijEH2Pq/UMREY7JKETr9o2o+XhDRJgBJ2JHXnGSiLXwJQuC8IDJvL8xH1qRPnGVsTgNPtmE1oVXjMgRl30QN+SmfQRW9Lfl0w245pnMGe1vMWUjnKjExpXvL9wnCxBfS6IX524rOAgrfL29riOgrsTKaglP3w1ls8WU6Eoxyu0rFLm2uF9vvOY3YQ5dJBKZWwL5U5qXiuiGl3JaWziT4EaxxUVsDImwmzWFf5PmSxISIfLAt+806qbFJClKjUbiEnuTJIm/IPcZLvLm8PI4EoD2rW7mcvM95EJagwvEofNoBCVal0549HMcCvMX+hLdi3ZhGCgNrvBpQa1K+aZsqdhe2YwjgVq3SxV5FxmCZed7Am0g2/Z/CRfLmPrKqm3YiSIfSN5b9KQ+UuPD12pESR+8Masc/7AqdCqbVtoX4WGgjpsAnULm6QNfKR5eZtlDQQkrDWTjkB2gckeu0RQ5Ne6uLKJbIlkjGQCORLCUAIhWNWs0okWKOVrpDiYd8pleCJQfE1w7IsYu8siI3pqukIz21ehXSRKv16SgR4ztVgDBpOMIw7IeFZuTEuXwycOKY59Qsj/y X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64496256-0b58-4c63-eb15-08d9367bfe68 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:42.8660 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NLPuHT4LVh6XuOBRP7jrUp3XbG5xh6hcT3mrotaJQCi/bNFmyOX81WSvGr6xdugDnhUNwTww3lTsACnRxzSE3g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define an address translation context struct. This will hold values that will be passed between multiple functions. Save return address, Node ID, and the Instance ID number to start. Currently, we use the UMC number as the Instance ID, but future DF versions may use another value. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-3-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Changed "umc" variable to "inst_id". * Drop df_types enum. drivers/edac/amd64_edac.c | 49 +++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d67cd8f57b94..62eca188458f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1079,12 +1079,15 @@ static struct df_reg df_regs[] = { [SYS_FAB_ID_MASK] = {1, 0x208}, }; +struct addr_ctx { + u64 ret_addr; + u16 nid; + u8 inst_id; +}; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; - /* We start from the normalized address */ - u64 ret_addr = norm_addr; - u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; @@ -1097,6 +1100,16 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr struct df_reg reg; + struct addr_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + if (amd_df_indirect_read(nid, df_regs[DRAM_OFFSET], umc, &tmp)) goto out_err; @@ -1105,7 +1118,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; if (norm_addr >= hi_addr_offset) { - ret_addr -= hi_addr_offset; + ctx.ret_addr -= hi_addr_offset; base = 1; } } @@ -1236,14 +1249,14 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); + temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; + ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } /* Add dram base address */ - ret_addr += dram_base_addr; + ctx.ret_addr += dram_base_addr; /* If legacy MMIO hole enabled */ if (lgcy_mmio_hole_en) { @@ -1251,29 +1264,29 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; dram_hole_base = tmp & GENMASK(31, 24); - if (ret_addr >= dram_hole_base) - ret_addr += (BIT_ULL(32) - dram_hole_base); + if (ctx.ret_addr >= dram_hole_base) + ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } if (hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ret_addr >> 12) ^ - (ret_addr >> 18) ^ - (ret_addr >> 21) ^ - (ret_addr >> 30) ^ + hashed_bit = (ctx.ret_addr >> 12) ^ + (ctx.ret_addr >> 18) ^ + (ctx.ret_addr >> 21) ^ + (ctx.ret_addr >> 30) ^ cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); + if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(intlv_addr_bit); } /* Is calculated system address is above DRAM limit address? */ - if (ret_addr > dram_limit_addr) + if (ctx.ret_addr > dram_limit_addr) goto out_err; - *sys_addr = ret_addr; + *sys_addr = ctx.ret_addr; return 0; out_err: From patchwork Wed Jun 23 19:19:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D218DC49EA5 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YQDzw88TX1RNo+k2E0ijelk29PSGk39cEcM2bPo7GNBUfptHvIOtmn+sAYPaHAGZiW7bTwUKY499pNsF7DCuBpfR3FnSDS/+47QXJoJMsum/ylsWeIKIVQlh2HKYxzuYzqKeDkIdAj9LcGgWtxkqBL2z78W57KZXINv4T8dtHNCrpop1JHWDEEzSkCP6qbnXvdUS1S+aAKIiLu65FXfnvOcpvH6sCNhioMp+bY2EdEfS1wrLgLZknwUc8YZDzpQNwffJNGT45EhYWS+1wUTh/saG+XOZisPB1rOAYpcMeB1kSGoUlJZn5mXrTmHNNjB76HbpPd7P7GkCTfOQSzE9nVyeFfYjErLrJmDsgjsI8VZ58MCW/lSNe7+yY0T2GjuE0cbxhhYvMSi0aMU2+MolOv2+41qwnUQHsdupuXQcaWctBmGLJyTFRMmab+NlVWd6gBAeB9C3B5/0b0ANwb+b05k0H8JLSL92t5P1WKvk7yMj5VxmJjDzkuGQqFeSQjgUF9gk1XPtC9cxQQ3NQI6O9eQbTl7WgV0BwEcO5GJ719qJb+vt0ro56oHO038sh3SiRVohW8PADeEZ3JpOGfG1vgoAf7FLIbAPQirLUtQXX3LymO41DsM8AUQOMd6iz/KnlsRQ9Ph6r9EhOxvqBw7FO3bsws/s96JYo/+EFpGGVNCZyxd9gMxm6Q65hKIMDcbrzVI+mj37WqokatnPATW+TH10BwjtaB6oGPlta2Ar8xTaqqVvC9MUJbkn6Juc1oy7Pnb+ztNKBBUzx887pZw+Mza+FtxfAoFyJPFghDCJP/AH9tYDKlthjkRRzvOlpgfoJ6FrsYkCN+TFFTLB7OFWfDFqRM29HtUFKr4F6b/c0CD737tAnCL8ko5YLFmzJrm5SuFfOG4m22FpJAEi8d+FuL1DoY0CZsqOmx+GZZDdvsQfnUBcbeE7nEpDxCZvm1zYFS24MvWXLuaaP/HC0a6dY6Ytg9emldDqyHheQIpXTQvYUb/69lPyzG8ExOAtFmxza++l3QvD7aE5z7DjG8p0ACTe2P9kauYQeHRlhvfgCSjpl2wjYMVS5oUuBR3guBuudM7C9En0oM/h1GtOa36gUwUHVzobROW65ir8LPAM5MvsjKpGj18m/7gjK32ZOFN4Nmsk/07Ndx3WTxX+ZemJIp2G9RiPZ2YoDvpE+XeY/YfOHygsjb4IFYCyVvNpRed41ZWHvy81inIK8l5ltKjUTfm0K3XSbyO3G3Su6s6SAFT4qzjsAhge3GGw6NKHSDrtEmVpuaS7f66ygtleevMHTv2rmcl9tkLFzz3HuAu33BF6h8fpHgZ1JqbjQHu0Rff7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 81812adf-2d7a-4601-03f2-08d9367bfef2 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:43.7245 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: aaqRRRfHxAFJIIjVuBSQ6COkyU+qXTKwOBeZ4wWoRjygf7PX/maU68gEcvVvXjFpGakFoCVSDL4lFmAZywtBag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a stub to hold operations for different Data Fabric versions. This will be filled in following patches. Define a function to set the appropriate operations. Use a return code because future updates have checks that may fail. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-3-Yazen.Ghannam@amd.com v1->v2: * New in v2. drivers/edac/amd64_edac.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 62eca188458f..f769353ef7e4 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1085,6 +1085,21 @@ struct addr_ctx { u8 inst_id; }; +struct data_fabric_ops { +}; + +struct data_fabric_ops df2_ops = { +}; + +struct data_fabric_ops *df_ops; + +static int set_df_ops(struct addr_ctx *ctx) +{ + df_ops = &df2_ops; + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1110,6 +1125,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.nid = nid; ctx.inst_id = umc; + if (set_df_ops(&ctx)) + return -EINVAL; + if (amd_df_indirect_read(nid, df_regs[DRAM_OFFSET], umc, &tmp)) goto out_err; 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Wed, 23 Jun 2021 19:20:44 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 07/31] EDAC/amd64: Define functions for DramOffset Date: Wed, 23 Jun 2021 19:19:38 +0000 Message-Id: <20210623192002.3671647-8-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jOJ9dJqbHEF7HuQF4iMdt/a3vu0D7GlE1PdMiqbBZ+mGl80TdBi5uvw4yesqn+61oFprFExmtYzpRQnlHn1eCwqQhyBlFTRAH9AMZ0ZHF9oUteKRMUlHvcBW5NrRn2O8+/nsc1P29RjSC04MCsiamxhNihmCtiLrcsdO6Crz/b0OaglBEi/c/I4u34PkcidxKQ+ZudgB2K3G3AUVo3201ThQLUr9NkJ15znQHq/Q2V3jXEcDM7fiBhN4fxbruaytS6c3A041H1O9bP8ljg+qOAiMuLLl7Cb2YYJ9QuEbxfSK/SBatAK+jUyCdiWqx7sR7l1SNnWqfaeePWXmu5r4bZYMDoQfDK3aElZWeiekC5Py5auLnqo10bsY5RaamQsCbXn9RkQ7/gT8Id31fFYklKwLTvaZFxT1uuyKdzWz34jX0i4gq1O3GsZwM2eBtg6XuzG8i5Z0VrcxO6hIzk+KhX8Nt4+QaZ9ClKHq1sW24Klku1HhKbna0sDVcmLmDB0y5jtuRqMMW92VNGUvpgu3JdvxodVwRZphu/uGjphEESR9qBuEbTy1wK95C0BR+tZPzWDQ0QaNCsYT2gW+SEEBjONvQ1lnjWwchQ9g0gf13sue6+0sMkBpJW/lXoiC9S+KJMbyZ7onC1Ch1PFRRUUXxRXDykB3WgmNbTu5SMVYa+FsXpFEiUj98E5k0H167Qs8W7ivK0F7HOQgj9OOrs3e+7gbvMsRBctcbOpWKOONy8ra+5OP51b1vg5LDU2Rn+QHVRn85vmDQvvAgwoROMvIzR8gWKaWN4Xkrk7yxGivr5rKP9o1bUmsImKMfaYTGGJFC6RuHAYCKOPCwiC+W9e9Pzh1V0Z/zeNIZOBpqOJniJXSKNvXgH6B90P6I0TF3qWBl+EJcdjUYovmwanvEoaJR4Qq9fyPel0HtZUZbMJna723owhRsg8WSiaDLdS1doHJdDpMCJyjrhwTwzFhlFJhvNeeuCiDGsxu6GQkUi8MVDJ6F1dm/2sEOLlUmfpF4Q0DZy+jxABAB4ErF7fmrGlENhnupY4ByxHVUBdu6QBnUMtlCSnuMiQiiqs4zcXU9BoRECXAz/PQjaZk6kT0mXZImDQWkVQQduymWhb31DLYgYEIGWKaE4B2MzMsODzwSxCZo5qBf64aZyJ4Rojgu6E40IMBOa3lpIGgAZKafzngNNQZ2Q6IQ8p/y78vGujmxYFMOMiLxG6s4Mza3dgjIqr508IxdaUaAi0xLfOq2K94FogCFP1p0TnkyDMGTrEpSorZgwERU6qmlmrFIIRaCkGWqapEc2A+uB+iCOwjB4jg8HQKaac5cS64F0nB4k99fzwi X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b4b0f75-ec82-4a95-d008-08d9367bff68 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:44.5551 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YoM36TgHgsxjjR8N6quUo8JvbjppoPwk70hfvDiMzbFYO2UiOD7TtoZKseIIeiY9OkqbAmF06vDv+Wr+yVVppg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add helper functions to read the DramOffset register and to remove the offset from the calculated address. The helper functions will be expanded in future DF versions. Rename the "base" variable to "map_num" to indicate that this is the address map number. An address map is defined with a base and limit value. The map_num variable is used to select the proper base and limit registers to use for the address translation. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-4-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add function to data_fabric_ops. drivers/edac/amd64_edac.c | 57 +++++++++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f769353ef7e4..389f0621e885 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1079,16 +1079,26 @@ static struct df_reg df_regs[] = { [SYS_FAB_ID_MASK] = {1, 0x208}, }; +/* Use "reg_" prefix for raw register values. */ struct addr_ctx { u64 ret_addr; + u32 reg_dram_offset; u16 nid; u8 inst_id; + u8 map_num; }; struct data_fabric_ops { + u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); }; +static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; +} + struct data_fabric_ops df2_ops = { + .get_hi_addr_offset = &get_hi_addr_offset_df2, }; struct data_fabric_ops *df_ops; @@ -1100,6 +1110,35 @@ static int set_df_ops(struct addr_ctx *ctx) return 0; } +static int get_dram_offset_reg(struct addr_ctx *ctx) +{ + if (amd_df_indirect_read(ctx->nid, df_regs[DRAM_OFFSET], + ctx->inst_id, &ctx->reg_dram_offset)) + return -EINVAL; + + return 0; +} + +static int remove_dram_offset(struct addr_ctx *ctx) +{ + if (get_dram_offset_reg(ctx)) + return -EINVAL; + + ctx->map_num = 0; + + /* Remove HiAddrOffset from normalized address, if enabled: */ + if (ctx->reg_dram_offset & BIT(0)) { + u64 hi_addr_offset = df_ops->get_hi_addr_offset(ctx); + + if (ctx->ret_addr >= hi_addr_offset) { + ctx->ret_addr -= hi_addr_offset; + ctx->map_num = 1; + } + } + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1109,7 +1148,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 intlv_addr_sel, intlv_addr_bit; u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en, base = 0; + u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; bool hash_enabled = false; @@ -1128,21 +1167,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (set_df_ops(&ctx)) return -EINVAL; - if (amd_df_indirect_read(nid, df_regs[DRAM_OFFSET], umc, &tmp)) + if (remove_dram_offset(&ctx)) goto out_err; - /* Remove HiAddrOffset from normalized address, if enabled: */ - if (tmp & BIT(0)) { - u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; - - if (norm_addr >= hi_addr_offset) { - ctx.ret_addr -= hi_addr_offset; - base = 1; - } - } - reg = df_regs[DRAM_BASE_ADDR]; - reg.offset += base * 8; + reg.offset += ctx.map_num * 8; if (amd_df_indirect_read(nid, reg, umc, &tmp)) goto out_err; @@ -1166,7 +1195,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } reg = df_regs[DRAM_LIMIT_ADDR]; - reg.offset += base * 8; + reg.offset += ctx.map_num * 8; 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Wed, 23 Jun 2021 19:20:45 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 08/31] EDAC/amd64: Define function to read DRAM address map registers Date: Wed, 23 Jun 2021 19:19:39 +0000 Message-Id: <20210623192002.3671647-9-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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Save the raw values in the context struct as they will be parsed later. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-5-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 58 +++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 389f0621e885..867ab32caab2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1083,6 +1083,8 @@ static struct df_reg df_regs[] = { struct addr_ctx { u64 ret_addr; u32 reg_dram_offset; + u32 reg_base_addr; + u32 reg_limit_addr; u16 nid; u8 inst_id; u8 map_num; @@ -1139,6 +1141,30 @@ static int remove_dram_offset(struct addr_ctx *ctx) return 0; } +static int get_dram_addr_map(struct addr_ctx *ctx) +{ + struct df_reg reg = df_regs[DRAM_BASE_ADDR]; + + reg.offset += ctx->map_num * 8; + + if (amd_df_indirect_read(ctx->nid, reg, ctx->inst_id, &ctx->reg_base_addr)) + return -EINVAL; + + /* Check if address range is valid. */ + if (!(ctx->reg_base_addr & BIT(0))) { + pr_debug("Invalid DramBaseAddress range: 0x%x.\n", ctx->reg_base_addr); + return -EINVAL; + } + + reg = df_regs[DRAM_LIMIT_ADDR]; + reg.offset += ctx->map_num * 8; + + if (amd_df_indirect_read(ctx->nid, reg, ctx->inst_id, &ctx->reg_limit_addr)) + return -EINVAL; + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1152,8 +1178,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 cs_mask, cs_id = 0; bool hash_enabled = false; - struct df_reg reg; - struct addr_ctx ctx; memset(&ctx, 0, sizeof(ctx)); @@ -1170,22 +1194,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (remove_dram_offset(&ctx)) goto out_err; - reg = df_regs[DRAM_BASE_ADDR]; - reg.offset += ctx.map_num * 8; - if (amd_df_indirect_read(nid, reg, umc, &tmp)) - goto out_err; - - /* Check if address range is valid. */ - if (!(tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, tmp); + if (get_dram_addr_map(&ctx)) goto out_err; - } - lgcy_mmio_hole_en = tmp & BIT(1); - intlv_num_chan = (tmp >> 4) & 0xF; - intlv_addr_sel = (tmp >> 8) & 0x7; - dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; + intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { @@ -1194,14 +1209,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - reg = df_regs[DRAM_LIMIT_ADDR]; - reg.offset += ctx.map_num * 8; - if (amd_df_indirect_read(nid, reg, umc, &tmp)) - goto out_err; - - intlv_num_sockets = (tmp >> 8) & 0x1; - intlv_num_dies = (tmp >> 10) & 0x3; - dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 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Wed, 23 Jun 2021 19:20:46 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 09/31] EDAC/amd64: Define function to find interleaving mode Date: Wed, 23 Jun 2021 19:19:40 +0000 Message-Id: <20210623192002.3671647-10-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Lr2Uc98ZhxLqPKz2HEfQ895j5jM10ais5w6D7sESFwwADlgwRojUo7S8yh033enXITF8776uPivVHZOhd/l07L+CyqFSxplYWYc+Wt3pj/GAwWvpXo8WoV9KA9530TDOjCGamZhfYvxxVLCq6zxaBvWFTq4WiqJOedGSv3pwEWktYmatG3nfzN6GyXke2602BXvngFMCwa9glgujJ4nnheXNzFNGCbhStL/I3pR6R8ZgPkcHs/LyO8uKG3mLtCzv4O0tnaSqkW/JzpMn6UQTnJKsYZvxg897X7190dhZB1AjNaVjBTmj+fFL/SAULwqIXPYVeRsIh9PqJjfhIlDJDsiQTwDSpRw1AA4+KfxHTriJA0f2QArWmsAuyDFIwWibsQJqbUA/o7mBEicomv1xE9MzM3G8hUblr/ihoZacCtTGRZ/jwCVbX6apbFkIFpyLTRhUK87k+GG2AYgjJxrN8ePkJQuV5hwFlOGvn8K7iBCN3jex/n4ahmLFXzicZAQXxD4M/Qdl25hELndg9fToMkNGokpUIfYZl2lsm5B3xFV3k6BOBctt92PDmSJc/KVf2Kj9sGzQGmUyyXSh2VJ9zptxaNowvXVHhEz4hUG3n+HWkqMOkZY4V72fFM8PKXrY4JJkVi2+SHNppxXv0fcY5HwC1kmtK3YAWMRdKfk+lVMgYhMYiY8/Fet7TmMY5Gd38f3MAmO0Jtv3A+3EIugQazibtzCmZJPzcm8HyOO+5CaCmg4nfC4LahKA5mkUcyVSEr0B8iefkKtvjxGazKvhlP+T2VzhwxaAAUCweJK1vHc/atEE2PPA3NCLAm4AzFsC4bU8SGMixZsM9C5LOaD094LYcEn4iOk91jZ9IHkEYuiiQeCAn/4YIbYm+ioMB2HYfc4sSHn/cpckBAjGskOcayn3FxHdi98ck9vF815U44bl5ScTKlIEJ+yzoB49N5JHTP0BJ+IPsyZYkQadfFrcJPzK5V+zFsgvyUKfryNViZTqVASgyC2GAF8ZoYSRGOU51+AHplvaZlFxpjXtTwd98mSLvefGmU5x76SV5sH4JeyJhjupgVpL6lyB68fujcrTOlO3Fjnc4VeUA+xnVWEBgXItfW8qaq6bo2ECgfT0eDxZg4kBZFTXiwEPkLNXMljWvzx5CiWJdSbGv4w2bzx0aFL6IKOu5Vwt9jvTJRbZQ5eVj+1NHZpzrwNJU/pNSiAp0CxLwrvWQaIsBnRwSEWHKSB/qdSiwTm4+48z+GugjHX8tg1i0u05skmDdef/QDcb1/JtX5hNQYWdCYQsVd736aVL/j2qYKf9u0Payqg9fbGg3C1lsXeaHJ3/j7O5zJnn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98d3f658-2783-4151-6d57-08d9367c0088 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:46.3930 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: f+SCa/yRfZtSIaUpyubsWED3U9rXOy6/f0aya0d1gBctxos9XaovKtFi4dHuy4EKs0RTHJpFo+AqGMU7wgwOZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-6-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 867ab32caab2..93a4ce9eb735 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1079,8 +1079,16 @@ static struct df_reg df_regs[] = { [SYS_FAB_ID_MASK] = {1, 0x208}, }; +/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ +enum intlv_modes { + NONE = 0x00, + NOHASH_2CH = 0x01, + DF2_HASH_2CH = 0x21, +}; + /* Use "reg_" prefix for raw register values. */ struct addr_ctx { + enum intlv_modes intlv_mode; u64 ret_addr; u32 reg_dram_offset; u32 reg_base_addr; @@ -1088,10 +1096,12 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + bool hash_enabled; }; struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + int (*get_intlv_mode)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1099,8 +1109,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int get_intlv_mode_df2(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; + + if (ctx->intlv_mode == 8) { + ctx->intlv_mode = DF2_HASH_2CH; + ctx->hash_enabled = true; + } + + if (ctx->intlv_mode != NONE && + ctx->intlv_mode != NOHASH_2CH && + ctx->intlv_mode != DF2_HASH_2CH) + return -EINVAL; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, + .get_intlv_mode = &get_intlv_mode_df2, }; struct data_fabric_ops *df_ops; @@ -1176,7 +1204,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 num_intlv_bits, hashed_bit; u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; - bool hash_enabled = false; struct addr_ctx ctx; @@ -1197,6 +1224,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (get_dram_addr_map(&ctx)) goto out_err; + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; @@ -1224,7 +1254,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr case 7: intlv_num_chan = 4; break; case 8: intlv_num_chan = 1; - hash_enabled = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -1325,7 +1354,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { + if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ hashed_bit = (ctx.ret_addr >> 12) ^ (ctx.ret_addr >> 18) ^ From patchwork Wed Jun 23 19:19:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C40E4C48BC2 for ; Wed, 23 Jun 2021 19:20:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADF63611C1 for ; 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This will be further refactored in later patches. Add the interleave address bit and the CS ID to the context struct. These values will be used by multiple functions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-7-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 128 ++++++++++++++++++++++---------------- 1 file changed, 73 insertions(+), 55 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 93a4ce9eb735..ebb82b5e155b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1096,6 +1096,8 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + u8 intlv_addr_bit; + u8 cs_id; bool hash_enabled; }; @@ -1193,57 +1195,26 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int denormalize_addr(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en; - u8 cs_mask, cs_id = 0; - - struct addr_ctx ctx; - - memset(&ctx, 0, sizeof(ctx)); - - /* We start from the normalized address */ - ctx.ret_addr = norm_addr; - - ctx.nid = nid; - ctx.inst_id = umc; - - if (set_df_ops(&ctx)) - return -EINVAL; - - if (remove_dram_offset(&ctx)) - goto out_err; - - if (get_dram_addr_map(&ctx)) - goto out_err; - - if (df_ops->get_intlv_mode(&ctx)) - goto out_err; - - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; - intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { pr_err("%s: Invalid interleave address select %d.\n", __func__, intlv_addr_sel); - goto out_err; + return -EINVAL; } - intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - intlv_addr_bit = intlv_addr_sel + 8; + ctx->intlv_addr_bit = intlv_addr_sel + 8; /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { @@ -1258,7 +1229,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr default: pr_err("%s: Invalid number of interleaved channels %d.\n", __func__, intlv_num_chan); - goto out_err; + return -EINVAL; } num_intlv_bits = intlv_num_chan; @@ -1266,7 +1237,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", __func__, intlv_num_dies); - goto out_err; + return -EINVAL; } num_intlv_bits += intlv_num_dies; @@ -1278,7 +1249,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (num_intlv_bits > 4) { pr_err("%s: Invalid interleave bits %d.\n", __func__, num_intlv_bits); - goto out_err; + return -EINVAL; } if (num_intlv_bits > 0) { @@ -1291,8 +1262,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (amd_df_indirect_read(nid, df_regs[FAB_BLK_INST_INFO_3], umc, &tmp)) - goto out_err; + if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], + ctx->inst_id, &tmp)) + return -EINVAL; cs_fabric_id = (tmp >> 8) & 0xFF; die_id_bit = 0; @@ -1301,14 +1273,15 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_chan) { die_id_bit = intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, df_regs[SYS_FAB_ID_MASK], umc, &tmp)) - goto out_err; + if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], + ctx->inst_id, &tmp)) + return -EINVAL; /* If interleaved over more than 1 die. */ if (intlv_num_dies) { @@ -1316,7 +1289,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr die_id_shift = (tmp >> 24) & 0xF; die_id_mask = (tmp >> 8) & 0xFF; - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((cs_fabric_id & die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ @@ -1324,7 +1298,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr socket_id_shift = (tmp >> 28) & 0xF; socket_id_mask = (tmp >> 16) & 0xFF; - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } /* @@ -1335,12 +1310,55 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); + temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); + temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) + << num_intlv_bits; + ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + + u32 tmp; + + u8 hashed_bit; + u8 lgcy_mmio_hole_en; + + struct addr_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + + if (set_df_ops(&ctx)) + return -EINVAL; + + if (remove_dram_offset(&ctx)) + return -EINVAL; + + if (get_dram_addr_map(&ctx)) + goto out_err; + + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + + if (denormalize_addr(&ctx)) + goto out_err; + + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + /* Add dram base address */ ctx.ret_addr += dram_base_addr; @@ -1360,12 +1378,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr (ctx.ret_addr >> 18) ^ (ctx.ret_addr >> 21) ^ (ctx.ret_addr >> 30) ^ - cs_id; + ctx.cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(intlv_addr_bit); + if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); } /* Is calculated system address is above DRAM limit address? */ From patchwork Wed Jun 23 19:19:42 2021 Content-Type: text/plain; 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Wed, 23 Jun 2021 19:20:48 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 11/31] EDAC/amd64: Define function to add DRAM base and hole Date: Wed, 23 Jun 2021 19:19:42 +0000 Message-Id: <20210623192002.3671647-12-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-8-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 45 ++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index ebb82b5e155b..68c4aecd5e7a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1320,14 +1320,34 @@ static int denormalize_addr(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int add_base_and_hole(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; + u64 dram_base_addr = (ctx->reg_base_addr & GENMASK_ULL(31, 12)) << 16; - u32 tmp; + /* Add dram base address */ + ctx->ret_addr += dram_base_addr; + + /* If legacy MMIO hole enabled */ + if (ctx->reg_base_addr & BIT(1)) { + u32 dram_hole_base; + + if (amd_df_indirect_read(0, df_regs[DRAM_HOLE_CTL], + DF_BROADCAST, &dram_hole_base)) + return -EINVAL; + + dram_hole_base &= GENMASK(31, 24); + if (ctx->ret_addr >= dram_hole_base) + ctx->ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_limit_addr; u8 hashed_bit; - u8 lgcy_mmio_hole_en; struct addr_ctx ctx; @@ -1354,23 +1374,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (denormalize_addr(&ctx)) goto out_err; - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - /* Add dram base address */ - ctx.ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, df_regs[DRAM_HOLE_CTL], umc, &tmp)) - goto out_err; - - dram_hole_base = tmp & GENMASK(31, 24); - if (ctx.ret_addr >= dram_hole_base) - ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); - } + if (add_base_and_hole(&ctx)) + goto out_err; if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ From patchwork Wed Jun 23 19:19:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F0AC4743C for ; Wed, 23 Jun 2021 19:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7212B610A0 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 44SK/AETLKwb++fViIq6Z0ZxQiu7LBD3GzbWzQQu80rwi7m1r6l51sJGOoL46VHNKEbjXDQQaiPEcTV5AK5RzdsZ6ahIJZzSrP93Y44yfNyFJEezPl5WGDga4RKYOqMVDKYZo3VKzRNW4unG5LrQ5XPDiZA09rWe+J779ISXJCy5l9ZAP0xL8bqTpDF8CQA2DKn4rV3fjMBbySLJuHofTKYeKkQtKy9iGuoJgOIgQFU7gZao6/vh4RrRXAgvMnxpEcfjkP7wYqiC0CU9Se/7gvmn3iH2QGEaCIbiCSCY+gDb5gDXt/yGbhiEdue7dhqXRjcMtzter00G6Mr/07ATb+mLZrC2MzJVYALfTSmJ/rAkEsOkREnzJ9lr4aIjqgGqJjg19R3zO4FyoLemLvSQjsOuEWbKGRi3YTYykf0bHawUxplP+Mlzc4LV6coWofpJxcKeI83e6XPUluGuUmAFKi4UQehiT7l0YfEnnK9/CwWWb02nXO4UVW4ibd4ae3kkDtK4gCWM275S+Uo49g6W53MkJ5i75KIm38WiZJ52lhsDb3jCfCBryoS5AsUf5gJ+BqkG554dOBPS80qeODa2dIHrd6cDNE0zHcrQw0b4l8B9FH+P+uM7IitiuiClHNyC0gGCioYvwvOkESIJLBnv8Y8/vQuf16VnCsB5fEw/brjfj7KgR6NjBLdJawtgViDJEO78AEElIjQgcyWqvJ5tsruGjXKdyHMgU87ROoyH960PRz/5Iljlh5pAyBcvrrX95X3ndXHk7NAc7aqwaUZ3aUJaKWT231IpCIMYwJcgGYqsswHOyhiD6adSFgKyS4hg/adRxRaWob2XCaWR0Nkbwhiyq8CyBfI8EJBGd9Xr/4w9TtrivBC+IFAHZyBySS/7NabnHVlRQYusuf/9PdRu54mH04LaPAxV80lM5M/u3qcCWw80wVOJNh31k/UjZtgd3f0OOXmI7ZjSYCotzkDAZI/0h1IRHfcTIttJ9rMhHnL9MBgnkWlVu4FEtb9UHxAuv0aJGub3mvq81cRtC6+BUzK3tDpmtblw2UK6CCD6LqH30y0YuD9XwNu1CyByCpg4famyXIFbK3JS1UxxVu87/tqoDkhNAFYwojSGkeAzwbiW9/v58gBS4xFB0LQRLvM1AeBK0+bwvxSXZBsDa9EeaYrCUXwwJh1XMF0zrosRivUQHJ7CmI2p/HsV73YXZ4g+a7taqHAX3DSnwuGjb2ftXqx42+jMHDeUye8aE3o5NWMVSqo/CsvpCebxm4V5m2Vh/ZziSofWbkQSryXNKYCLwYkohF6UqeDgjfDG4nIJxlDB8oatVVKrh5r07dAji/jA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c6d73653-6272-4b35-cbdf-08d9367c0200 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:48.8836 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: x9hVH3e4y3s7P724imFNmE/QoPHOc8zLThUdMXsZq3LBY19zRPPXEeG7r/yQYAwSvlWw7ofTyRxTp5Fx5YY73g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the dehashing code into a separate helper function. Define a DF2-specific function for the current code. Specific helper functions will be added for future DF versions. The dehashing code is tied to interleaving mode rather than Data Fabric version, so save the function pointer in the ctx struct. The name include "df2" because this mode only exists on DF2. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-9-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add new function pointer in ctx struct. drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 68c4aecd5e7a..46b0279a2e12 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1098,7 +1098,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 cs_id; - bool hash_enabled; + int (*dehash_addr)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1111,13 +1111,29 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int dehash_addr_df2(struct addr_ctx *ctx) +{ + u8 hashed_bit = (ctx->ret_addr >> 12) ^ + (ctx->ret_addr >> 18) ^ + (ctx->ret_addr >> 21) ^ + (ctx->ret_addr >> 30) ^ + ctx->cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + return 0; +} + static int get_intlv_mode_df2(struct addr_ctx *ctx) { ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; if (ctx->intlv_mode == 8) { ctx->intlv_mode = DF2_HASH_2CH; - ctx->hash_enabled = true; + ctx->dehash_addr = &dehash_addr_df2; } if (ctx->intlv_mode != NONE && @@ -1347,8 +1363,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr { u64 dram_limit_addr; - u8 hashed_bit; - struct addr_ctx ctx; memset(&ctx, 0, sizeof(ctx)); @@ -1379,19 +1393,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (add_base_and_hole(&ctx)) goto out_err; - if (ctx.hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ctx.ret_addr >> 12) ^ - (ctx.ret_addr >> 18) ^ - (ctx.ret_addr >> 21) ^ - (ctx.ret_addr >> 30) ^ - ctx.cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); - } + if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) + goto out_err; /* Is calculated system address is above DRAM limit address? */ if (ctx.ret_addr > dram_limit_addr) From patchwork Wed Jun 23 19:19:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F225C48BE5 for ; Wed, 23 Jun 2021 19:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78B8461075 for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-10-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 46b0279a2e12..de80a224ef12 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1359,10 +1359,20 @@ static int add_base_and_hole(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int addr_over_limit(struct addr_ctx *ctx) { - u64 dram_limit_addr; + u64 dram_limit_addr = ((ctx->reg_limit_addr & GENMASK_ULL(31, 12)) << 16) + | GENMASK_ULL(27, 0); + + /* Is calculated system address above DRAM limit address? */ + if (ctx->ret_addr > dram_limit_addr) + return -EINVAL; + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ struct addr_ctx ctx; memset(&ctx, 0, sizeof(ctx)); @@ -1388,16 +1398,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (denormalize_addr(&ctx)) goto out_err; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - if (add_base_and_hole(&ctx)) goto out_err; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) goto out_err; - /* Is calculated system address is above DRAM limit address? */ - if (ctx.ret_addr > dram_limit_addr) + if (addr_over_limit(&ctx)) goto out_err; *sys_addr = ctx.ret_addr; From patchwork Wed Jun 23 19:19:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DDB3C48BE5 for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-11-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index de80a224ef12..3f1ff5adce4a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1390,28 +1390,25 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr return -EINVAL; if (get_dram_addr_map(&ctx)) - goto out_err; + return -EINVAL; if (df_ops->get_intlv_mode(&ctx)) - goto out_err; + return -EINVAL; if (denormalize_addr(&ctx)) - goto out_err; + return -EINVAL; if (add_base_and_hole(&ctx)) - goto out_err; + return -EINVAL; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) - goto out_err; + return -EINVAL; if (addr_over_limit(&ctx)) - goto out_err; + return -EINVAL; *sys_addr = ctx.ret_addr; return 0; - -out_err: - return -EINVAL; } static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); From patchwork Wed Jun 23 19:19:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18B58C4743C for ; Wed, 23 Jun 2021 19:20:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 024F960FF4 for ; Wed, 23 Jun 2021 19:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230157AbhFWTXO (ORCPT ); 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Wed, 23 Jun 2021 19:20:51 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 15/31] EDAC/amd64: Simplify function parameters Date: Wed, 23 Jun 2021 19:19:46 +0000 Message-Id: <20210623192002.3671647-16-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-12-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 3f1ff5adce4a..496ca863f45a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1371,14 +1371,14 @@ static int addr_over_limit(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 umc) { struct addr_ctx ctx; memset(&ctx, 0, sizeof(ctx)); /* We start from the normalized address */ - ctx.ret_addr = norm_addr; + ctx.ret_addr = *addr; ctx.nid = nid; ctx.inst_id = umc; @@ -1407,7 +1407,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (addr_over_limit(&ctx)) return -EINVAL; - *sys_addr = ctx.ret_addr; + *addr = ctx.ret_addr; return 0; } @@ -3314,7 +3314,7 @@ static void decode_umc_error(int node_id, struct mce *m) struct mem_ctl_info *mci; struct amd64_pvt *pvt; struct err_info err; - u64 sys_addr; + u64 sys_addr = m->addr; mci = edac_mc_find(node_id); if (!mci) @@ -3345,7 +3345,7 @@ static void decode_umc_error(int node_id, struct mce *m) err.csrow = m->synd & 0x7; - if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { + if (umc_normaddr_to_sysaddr(&sys_addr, pvt->mc_node_id, err.channel)) { err.err_code = ERR_NORM_ADDR; goto log_error; } From patchwork Wed Jun 23 19:19:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8126FC48BE5 for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-13-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 496ca863f45a..233f8cec4fe8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1211,27 +1211,35 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } +static int get_intlv_addr_bit(struct addr_ctx *ctx) +{ + u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + + /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ + if (intlv_addr_sel > 3) { + pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); + return -EINVAL; + } + + ctx->intlv_addr_bit = intlv_addr_sel + 8; + + return 0; +} + static int denormalize_addr(struct addr_ctx *ctx) { u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; u8 num_intlv_bits, cs_mask = 0; - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { - pr_err("%s: Invalid interleave address select %d.\n", - __func__, intlv_addr_sel); + if (get_intlv_addr_bit(ctx)) return -EINVAL; - } intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - ctx->intlv_addr_bit = intlv_addr_sel + 8; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { case 0: intlv_num_chan = 0; break; From patchwork Wed Jun 23 19:19:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD47BC48BC2 for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-14-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 233f8cec4fe8..02dc34c13d65 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1234,6 +1234,10 @@ static int denormalize_addr(struct addr_ctx *ctx) u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; + /* Return early if no interleaving. */ + if (ctx->intlv_mode == NONE) + return 0; + if (get_intlv_addr_bit(ctx)) return -EINVAL; From patchwork Wed Jun 23 19:19:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E6F4C4743C for ; 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Drop unused cases. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-15-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 42 +++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 02dc34c13d65..80192a05bb93 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1097,6 +1097,7 @@ struct addr_ctx { u8 inst_id; u8 map_num; u8 intlv_addr_bit; + u8 intlv_num_chan; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1226,12 +1227,29 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_chan(struct addr_ctx *ctx) +{ + /* Save the log2(# of channels). */ + switch (ctx->intlv_mode) { + case NONE: + ctx->intlv_num_chan = 0; + break; + case NOHASH_2CH: + case DF2_HASH_2CH: + ctx->intlv_num_chan = 1; + break; + default: + /* Valid interleaving modes where checked earlier. */ + break; + } +} + static int denormalize_addr(struct addr_ctx *ctx) { u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; + u8 intlv_num_dies, intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1244,23 +1262,9 @@ static int denormalize_addr(struct addr_ctx *ctx) intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ - switch (intlv_num_chan) { - case 0: intlv_num_chan = 0; break; - case 1: intlv_num_chan = 1; break; - case 3: intlv_num_chan = 2; break; - case 5: intlv_num_chan = 3; break; - case 7: intlv_num_chan = 4; break; - - case 8: intlv_num_chan = 1; - break; - default: - pr_err("%s: Invalid number of interleaved channels %d.\n", - __func__, intlv_num_chan); - return -EINVAL; - } + get_intlv_num_chan(ctx); - num_intlv_bits = intlv_num_chan; + num_intlv_bits = ctx->intlv_num_chan; if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", @@ -1298,8 +1302,8 @@ static int denormalize_addr(struct addr_ctx *ctx) die_id_bit = 0; /* If interleaved over more than 1 channel: */ - if (intlv_num_chan) { - die_id_bit = intlv_num_chan; + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; ctx->cs_id = cs_fabric_id & cs_mask; } From patchwork Wed Jun 23 19:19:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CD2BC48BE5 for ; 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This will be expanded for future DF versions. Also, drop an unneeded assert to match the reference code. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-16-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 80192a05bb93..360fbecf0d8b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1098,6 +1098,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 intlv_num_chan; + u8 intlv_num_dies; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1105,6 +1106,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); + void (*get_intlv_num_dies)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1145,9 +1147,15 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static void get_intlv_num_dies_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, + .get_intlv_num_dies = &get_intlv_num_dies_df2, }; struct data_fabric_ops *df_ops; @@ -1249,7 +1257,7 @@ static int denormalize_addr(struct addr_ctx *ctx) u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_dies, intlv_num_sockets; + u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1260,19 +1268,12 @@ static int denormalize_addr(struct addr_ctx *ctx) return -EINVAL; intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; get_intlv_num_chan(ctx); + df_ops->get_intlv_num_dies(ctx); num_intlv_bits = ctx->intlv_num_chan; - - if (intlv_num_dies > 2) { - pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", - __func__, intlv_num_dies); - return -EINVAL; - } - - num_intlv_bits += intlv_num_dies; + num_intlv_bits += ctx->intlv_num_dies; /* Add a bit if sockets are interleaved. */ num_intlv_bits += intlv_num_sockets; @@ -1310,14 +1311,14 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; - if (intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || intlv_num_sockets) if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], ctx->inst_id, &tmp)) return -EINVAL; /* If interleaved over more than 1 die. */ - if (intlv_num_dies) { - sock_id_bit = die_id_bit + intlv_num_dies; + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; die_id_shift = (tmp >> 24) & 0xF; die_id_mask = (tmp >> 8) & 0xFF; From patchwork Wed Jun 23 19:19:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DEFFC4743C for ; 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This will be expanded for future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-17-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 360fbecf0d8b..09cdc0466ae2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1099,6 +1099,7 @@ struct addr_ctx { u8 intlv_addr_bit; u8 intlv_num_chan; u8 intlv_num_dies; + u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); }; @@ -1107,6 +1108,7 @@ struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); + void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1152,10 +1154,16 @@ static void get_intlv_num_dies_df2(struct addr_ctx *ctx) ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; } +static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, .get_intlv_num_dies = &get_intlv_num_dies_df2, + .get_intlv_num_sockets = &get_intlv_num_sockets_df2, }; struct data_fabric_ops *df_ops; @@ -1257,7 +1265,6 @@ static int denormalize_addr(struct addr_ctx *ctx) u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 intlv_num_sockets; u8 num_intlv_bits, cs_mask = 0; /* Return early if no interleaving. */ @@ -1267,16 +1274,13 @@ static int denormalize_addr(struct addr_ctx *ctx) if (get_intlv_addr_bit(ctx)) return -EINVAL; - intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; - get_intlv_num_chan(ctx); df_ops->get_intlv_num_dies(ctx); + df_ops->get_intlv_num_sockets(ctx); num_intlv_bits = ctx->intlv_num_chan; num_intlv_bits += ctx->intlv_num_dies; - - /* Add a bit if sockets are interleaved. */ - num_intlv_bits += intlv_num_sockets; + num_intlv_bits += ctx->intlv_num_sockets; /* Assert num_intlv_bits <= 4 */ if (num_intlv_bits > 4) { @@ -1311,7 +1315,7 @@ static int denormalize_addr(struct addr_ctx *ctx) sock_id_bit = die_id_bit; - if (ctx->intlv_num_dies || intlv_num_sockets) + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], ctx->inst_id, &tmp)) return -EINVAL; @@ -1327,7 +1331,7 @@ static int denormalize_addr(struct addr_ctx *ctx) } /* If interleaved over more than 1 socket. */ - if (intlv_num_sockets) { + if (ctx->intlv_num_sockets) { socket_id_shift = (tmp >> 28) & 0xF; socket_id_mask = (tmp >> 16) & 0xFF; From patchwork Wed Jun 23 19:19:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C143CC4743C for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-18-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 09cdc0466ae2..e5c296b00f5c 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1282,13 +1282,6 @@ static int denormalize_addr(struct addr_ctx *ctx) num_intlv_bits += ctx->intlv_num_dies; num_intlv_bits += ctx->intlv_num_sockets; - /* Assert num_intlv_bits <= 4 */ - if (num_intlv_bits > 4) { - pr_err("%s: Invalid interleave bits %d.\n", - __func__, num_intlv_bits); - return -EINVAL; - } - if (num_intlv_bits > 0) { u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; From patchwork Wed Jun 23 19:19:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF76AC48BC2 for ; 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The exact bits to use vary based on interleaving mode. New interleaving modes in future DF versions will be added as new cases. Also, introduce a helper function that does the bit manipulation to make the gap. The current version of this function is "simple", and future interleaving modes may reuse this or use a more advanced function. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-19-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Added new function pointer to ctx struct. drivers/edac/amd64_edac.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e5c296b00f5c..b497af7c3561 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1102,6 +1102,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); + void (*make_space_for_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1111,6 +1112,29 @@ struct data_fabric_ops { void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; +static void expand_bits(u8 start_bit, u8 num_bits, u64 *value) +{ + u64 temp1, temp2; + + if (start_bit == 0) { + *value <<= num_bits; + return; + } + + temp1 = *value & GENMASK_ULL(start_bit - 1, 0); + temp2 = (*value & GENMASK_ULL(63, start_bit)) << num_bits; + *value = temp1 | temp2; +} + +static void make_space_for_cs_id_simple(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_dies; + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1141,6 +1165,8 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) ctx->dehash_addr = &dehash_addr_df2; } + ctx->make_space_for_cs_id = &make_space_for_cs_id_simple; + if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && ctx->intlv_mode != DF2_HASH_2CH) @@ -1278,13 +1304,11 @@ static int denormalize_addr(struct addr_ctx *ctx) df_ops->get_intlv_num_dies(ctx); df_ops->get_intlv_num_sockets(ctx); - num_intlv_bits = ctx->intlv_num_chan; - num_intlv_bits += ctx->intlv_num_dies; - num_intlv_bits += ctx->intlv_num_sockets; + ctx->make_space_for_cs_id(ctx); if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; + u64 temp_addr_i; /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. @@ -1340,11 +1364,8 @@ static int denormalize_addr(struct addr_ctx *ctx) * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) - << num_intlv_bits; - ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + ctx->ret_addr |= temp_addr_i; } return 0; From patchwork Wed Jun 23 19:19:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03FE9C48BC2 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YANHg0vbQTl7PTp2hqsNQwk4kFCEE+qr4wQ7YLv96vlr94n9DlpcvI4oNXE52Em1fVZqulQVjEYyC77+l5TfkvyGjMXjlHZpaCAHIa+Et1VXKykSVoL7hVKRLrqzFhL7QvR11UWBSfZNzONqZ3qR8z9QLCcw2yAkStWHEUffM2when41tagMrDoFWnQoQo33iqpyY7HZbv2SZcDY2FReu88/lKpEvMz/acb5ZiTHM3vcPvHagNMYQgW/OkghXuDH9bvLi47FzCFm3yRSe4DYy/sGgpdcRed3Em18S93wFMlNXdEy1LEzR4ccHQ0Tdyf1O6IHT4v6YIsIXxwLq3CqYR0X3ot+q5M4ZwYS83HstoWJnqiy2RNEkBAF18lenn9a5unGZB2DNRiuKBfBg0RB8CDIFrYICAKJLAWfuG6BkmtT8RscahHdyK20ruwGuV+Bek63wAAljuV0LVcuev1OZLyZVdgAjybfPD5L0nx9muAAflaBhbO1uNmLtp7xncUE4bXLEsP1ziiXsU+ccz2TQ9PHYFACUvtxc+STmhrN2Oe0ruRWzG1wJ2EnLLKpMzlip3KgmaPhlZwZ0u6dJdwuYl/61f3FjpXdZf5ciX+AaF9cP3PhGg4hJE95ybNec8XZ0VO9KPfluvGWXek/+pBarIg4eVSFfxVL2Av0RfS7ltr1wJdt8HWMgxT27062oRVEyEP7SsXuLSe3C13LAKg+dmEV1wmu1RZ5wfgT8ucKECekdmnWnJznKpqXKrnGrvTMjdAEybrt3W406fEN1MZBHq9T40C6FAKF1k/Psg8+AZ/QJZ7cr1ZBes1ZuAaWCC0HP4YTSmTjCSLDgsiw4AlPFMRAbeJoWCJGn9bG0Jhol/zjbqbKrCiwkNi6ML8vlYLi8IqxM+MfUb4oXlVNjzUIuIbagwa0vbaUtX6xH2mWc0iLN87Q7xCiWg8hlTZMIcIXlI6rmGjz0XyaBdK+Xr3cDgdXek4KYS+jCWK0FPZGORaFbfTLOa9L61qwxdU/4FgnCkxB7CAdfpWROVP5Mg9xAhNJWfTtZc70KVLzvYVQpscgvqWR3lwssDH/3Ax33ODIlHP330P7OpkLQ/drV3Ht4TA7x38GicNWMBQV523RFRIQctx+pLqsVudKXKBBCgK088UyIkZyeklj35isSifymugnNGWMKLUyyVtmzMK56S+RMgSGalgVRPx+CRPYBuk7a1XH7SCbnRd9U98b37bb50a95LELVtzPqRZLph8vkPWQuAdnHdcI7Y0cBL0n7/efQybnBMhjFCriUA/yBZeHw+pTF68QFndq6kDubfTmlUdosk2PBoUeUalOjdx7Jfn/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e5a44db7-a71f-4b2b-a884-08d9367c07f3 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:58.9158 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rV8d8nvTTzVwxGphgbwb91WediuZIASgzeHgyrUpnCDIxxwr2VIxlKr6AQQCX4hSErZ6QnjdZfNsmVj/SPGlPw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0211 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move code used to calculate the CS ID into a separate helper function. Drop redundant code comment about reading DF register. The "num_intlv_bits" variable is left uninitialized as it will be removed in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-20-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 98 +++++++++++++++++++-------------------- 1 file changed, 48 insertions(+), 50 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b497af7c3561..0270bf4f1f90 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1286,12 +1286,54 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int denormalize_addr(struct addr_ctx *ctx) +static int calculate_cs_id(struct addr_ctx *ctx) { + u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; + u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; u32 tmp; - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 num_intlv_bits, cs_mask = 0; + if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], ctx->inst_id, &tmp)) + return -EINVAL; + + cs_fabric_id = (tmp >> 8) & 0xFF; + die_id_bit = 0; + + /* If interleaved over more than 1 channel: */ + if (ctx->intlv_num_chan) { + die_id_bit = ctx->intlv_num_chan; + cs_mask = (1 << die_id_bit) - 1; + ctx->cs_id = cs_fabric_id & cs_mask; + } + + sock_id_bit = die_id_bit; + + if (ctx->intlv_num_dies || ctx->intlv_num_sockets) + if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], ctx->inst_id, &tmp)) + return -EINVAL; + + /* If interleaved over more than 1 die: */ + if (ctx->intlv_num_dies) { + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + die_id_shift = (tmp >> 24) & 0xF; + die_id_mask = (tmp >> 8) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + } + + /* If interleaved over more than 1 socket: */ + if (ctx->intlv_num_sockets) { + socket_id_shift = (tmp >> 28) & 0xF; + socket_id_mask = (tmp >> 16) & 0xFF; + + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + } + + return 0; +} + +static int denormalize_addr(struct addr_ctx *ctx) +{ + u8 num_intlv_bits; /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) @@ -1306,56 +1348,12 @@ static int denormalize_addr(struct addr_ctx *ctx) ctx->make_space_for_cs_id(ctx); + if (calculate_cs_id(ctx)) + return -EINVAL; + if (num_intlv_bits > 0) { - u8 die_id_bit, sock_id_bit, cs_fabric_id; u64 temp_addr_i; - /* - * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. - * This is the fabric id for this coherent slave. Use - * umc/channel# as instance id of the coherent slave - * for FICAA. - */ - if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], - ctx->inst_id, &tmp)) - return -EINVAL; - - cs_fabric_id = (tmp >> 8) & 0xFF; - die_id_bit = 0; - - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; - } - - sock_id_bit = die_id_bit; - - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], - ctx->inst_id, &tmp)) - return -EINVAL; - - /* If interleaved over more than 1 die. */ - if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & die_id_mask) - >> die_id_shift) << die_id_bit; - } - - /* If interleaved over more than 1 socket. */ - if (ctx->intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; - - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) - >> socket_id_shift) << sock_id_bit; - } - /* * The pre-interleaved address consists of XXXXXXIIIYYYYY * where III is the ID for this CS, and XXXXXXYYYYY are the From patchwork Wed Jun 23 19:19:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA8BBC48BE5 for ; Wed, 23 Jun 2021 19:21:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE3B5610A0 for ; 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This will be expanded for future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-21-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Added function pointer to ctx struct. drivers/edac/amd64_edac.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0270bf4f1f90..d09a17747abd 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1103,6 +1103,7 @@ struct addr_ctx { u8 cs_id; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); + void (*insert_cs_id)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1135,6 +1136,11 @@ static void make_space_for_cs_id_simple(struct addr_ctx *ctx) expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); } +static void insert_cs_id_simple(struct addr_ctx *ctx) +{ + ctx->ret_addr |= (ctx->cs_id << ctx->intlv_addr_bit); +} + static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) { return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; @@ -1166,6 +1172,7 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) } ctx->make_space_for_cs_id = &make_space_for_cs_id_simple; + ctx->insert_cs_id = &insert_cs_id_simple; if (ctx->intlv_mode != NONE && ctx->intlv_mode != NOHASH_2CH && @@ -1333,8 +1340,6 @@ static int calculate_cs_id(struct addr_ctx *ctx) static int denormalize_addr(struct addr_ctx *ctx) { - u8 num_intlv_bits; - /* Return early if no interleaving. */ if (ctx->intlv_mode == NONE) return 0; @@ -1351,20 +1356,7 @@ static int denormalize_addr(struct addr_ctx *ctx) if (calculate_cs_id(ctx)) return -EINVAL; - if (num_intlv_bits > 0) { - u64 temp_addr_i; - - /* - * The pre-interleaved address consists of XXXXXXIIIYYYYY - * where III is the ID for this CS, and XXXXXXYYYYY are the - * address bits from the post-interleaved address. - * "num_intlv_bits" has been calculated to tell us how many "I" - * bits there are. "intlv_addr_bit" tells us how many "Y" bits - * there are (where "I" starts). - */ - temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - ctx->ret_addr |= temp_addr_i; - } + ctx->insert_cs_id(ctx); return 0; } From patchwork Wed Jun 23 19:19:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F6ABC4743C for ; Wed, 23 Jun 2021 19:21:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 353A461075 for ; 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This will be expanded for future DF versions. The bitfield used for this value may be larger than the 8 bits currently used. So make it a u16 type which is large enough to hold all known sizes of this bitfield across DF versions. Also, call this function early as future DF versions may need the value early. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-22-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Added function to data_fabric_ops. drivers/edac/amd64_edac.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d09a17747abd..f5ac3b63376d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1093,6 +1093,7 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u16 cs_fabric_id; u16 nid; u8 inst_id; u8 map_num; @@ -1109,6 +1110,7 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); + int (*get_cs_fabric_id)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; @@ -1192,11 +1194,24 @@ static void get_intlv_num_sockets_df2(struct addr_ctx *ctx) ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; } +static int get_cs_fabric_id_df2(struct addr_ctx *ctx) +{ + u32 tmp; + + if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], ctx->inst_id, &tmp)) + return -EINVAL; + + ctx->cs_fabric_id = (tmp >> 8) & 0xFF; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, .get_intlv_num_dies = &get_intlv_num_dies_df2, .get_intlv_num_sockets = &get_intlv_num_sockets_df2, + .get_cs_fabric_id = &get_cs_fabric_id_df2, }; struct data_fabric_ops *df_ops; @@ -1296,20 +1311,16 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 die_id_bit, sock_id_bit, cs_fabric_id, cs_mask = 0; + u8 die_id_bit, sock_id_bit, cs_mask = 0; u32 tmp; - if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], ctx->inst_id, &tmp)) - return -EINVAL; - - cs_fabric_id = (tmp >> 8) & 0xFF; die_id_bit = 0; /* If interleaved over more than 1 channel: */ if (ctx->intlv_num_chan) { die_id_bit = ctx->intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = ctx->cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; @@ -1324,7 +1335,7 @@ static int calculate_cs_id(struct addr_ctx *ctx) die_id_shift = (tmp >> 24) & 0xF; die_id_mask = (tmp >> 8) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ @@ -1332,7 +1343,8 @@ static int calculate_cs_id(struct addr_ctx *ctx) socket_id_shift = (tmp >> 28) & 0xF; socket_id_mask = (tmp >> 16) & 0xFF; - ctx->cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } return 0; @@ -1411,6 +1423,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 umc) if (set_df_ops(&ctx)) return -EINVAL; + if (df_ops->get_cs_fabric_id(&ctx)) + return -EINVAL; + if (remove_dram_offset(&ctx)) return -EINVAL; From patchwork Wed Jun 23 19:19:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E40EFC49EA4 for ; Wed, 23 Jun 2021 19:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCAB361075 for ; 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These will be expanded for future DF versions. Make the die_id_mask and socket_id_mask values u16 type to accommodate larger bitfields in future DF versions. Also, move reading of the System Fabric ID Mask register into set_df_ops(). This will be expanded for future DF versions and will be used to determine DF version levels. And call this function early since future DF versions may need these values early. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-23-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 61 +++++++++++++++++++++++++++++---------- 1 file changed, 45 insertions(+), 16 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f5ac3b63376d..fa8046e2b055 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1093,7 +1093,10 @@ struct addr_ctx { u32 reg_dram_offset; u32 reg_base_addr; u32 reg_limit_addr; + u32 reg_fab_id_mask0; u16 cs_fabric_id; + u16 die_id_mask; + u16 socket_id_mask; u16 nid; u8 inst_id; u8 map_num; @@ -1109,8 +1112,11 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + u8 (*get_die_id_shift)(struct addr_ctx *ctx); + u8 (*get_socket_id_shift)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); int (*get_cs_fabric_id)(struct addr_ctx *ctx); + int (*get_masks)(struct addr_ctx *ctx); void (*get_intlv_num_dies)(struct addr_ctx *ctx); void (*get_intlv_num_sockets)(struct addr_ctx *ctx); }; @@ -1206,18 +1212,43 @@ static int get_cs_fabric_id_df2(struct addr_ctx *ctx) return 0; } +static int get_masks_df2(struct addr_ctx *ctx) +{ + ctx->die_id_mask = (ctx->reg_fab_id_mask0 >> 8) & 0xFF; + ctx->socket_id_mask = (ctx->reg_fab_id_mask0 >> 16) & 0xFF; + + return 0; +} + +static u8 get_die_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 24) & 0xF; +} + +static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask0 >> 28) & 0xF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, .get_intlv_num_dies = &get_intlv_num_dies_df2, .get_intlv_num_sockets = &get_intlv_num_sockets_df2, .get_cs_fabric_id = &get_cs_fabric_id_df2, + .get_masks = &get_masks_df2, + .get_die_id_shift = &get_die_id_shift_df2, + .get_socket_id_shift = &get_socket_id_shift_df2, }; struct data_fabric_ops *df_ops; static int set_df_ops(struct addr_ctx *ctx) { + if (amd_df_indirect_read(0, df_regs[SYS_FAB_ID_MASK], + DF_BROADCAST, &ctx->reg_fab_id_mask0)) + return -EINVAL; + df_ops = &df2_ops; return 0; @@ -1310,11 +1341,7 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) static int calculate_cs_id(struct addr_ctx *ctx) { - u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; - u8 die_id_bit, sock_id_bit, cs_mask = 0; - u32 tmp; - - die_id_bit = 0; + u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; /* If interleaved over more than 1 channel: */ if (ctx->intlv_num_chan) { @@ -1323,27 +1350,26 @@ static int calculate_cs_id(struct addr_ctx *ctx) ctx->cs_id = ctx->cs_fabric_id & cs_mask; } - sock_id_bit = die_id_bit; + /* Return early if no die interleaving and no socket interleaving. */ + if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) + return 0; - if (ctx->intlv_num_dies || ctx->intlv_num_sockets) - if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], ctx->inst_id, &tmp)) - return -EINVAL; + sock_id_bit = die_id_bit; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - die_id_shift = (tmp >> 24) & 0xF; - die_id_mask = (tmp >> 8) & 0xFF; + u8 die_id_shift = df_ops->get_die_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + sock_id_bit = die_id_bit + ctx->intlv_num_dies; + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { - socket_id_shift = (tmp >> 28) & 0xF; - socket_id_mask = (tmp >> 16) & 0xFF; + u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & socket_id_mask) + ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) >> socket_id_shift) << sock_id_bit; } @@ -1423,6 +1449,9 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 umc) if (set_df_ops(&ctx)) return -EINVAL; + if (df_ops->get_masks(&ctx)) + return -EINVAL; + if (df_ops->get_cs_fabric_id(&ctx)) return -EINVAL; From patchwork Wed Jun 23 19:19:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E2AAC48BC2 for ; Wed, 23 Jun 2021 19:21:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0AABD610A0 for ; Wed, 23 Jun 2021 19:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230380AbhFWTYN (ORCPT ); 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Wed, 23 Jun 2021 19:21:02 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 27/31] EDAC/amd64: Update CS ID calculation to match reference code Date: Wed, 23 Jun 2021 19:19:58 +0000 Message-Id: <20210623192002.3671647-28-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oRs/AIYbY3LnVhj7LiEPN9jMfhNspmWqNu4lgcYLEj0YL3aGnPn4rE7ecCxCmYyXi+qMY4tfpMidamaB6S93DYtc99CuzjBE+U7a1HKFgvs0oFn6FQ5o4AxTx0N8QehiEkMfKt/LeH9bIEOJDFY8+ufUzIAQj/d78af0KnV9vsAsOp7avWpk48PTVy/fKFOHdwN011sN/RlpxmTQxaPWfTMT2MLPAKTcTOCDAQROqkP9KuEoXgmURZdGnDMRArjzcF0PoPhYtqqbmjMnMMeKJFlKWVxFwdkFSIUylLu4vqZxiMMSlLaQ4SFkC3wqO7QVJTJ1HLucpWZDFr7EB6w256fSgs8KxJPpgMG/52H+mmDh2pt5W93wtRdaxmbpH1oWuaJ882mOnAaTgdOQece9ISAn1pAR8x4x9rWHXWogGjeg86tcQiiHloCn13pMxW8dDzF8mt/+ziBqO6dd/cJNP8pUptmSh6lCzM9pRsUyO8OsY0qCSkPTakFAT+sgwjCGPC5EVFdsQQN/P1JnJfSIEoRM9Qg+e5JgMwqVe02IHw15fqlliKCVIzvlcy+w2Ub1UxYCgzlRUuVv/IgVt+Bulr5ynhrFEVBMx2D5HK6K07ME5sJGn+dzrbSdB2xLWcTBO0LpjxNJAD85HUHn+0pMJ+52qHVv8UYDRMYAN9DsR75/Gx66vjNOQZMFSlNkHAPTwdqoR6sFj2rVaiT7Xypk1s4j8gt7d0/7lvQrak9UKnBrABLDP8FCkzZHOJfdqtZ7f8Vo4+yXLXN+NqX82r5MDpcBSEQLzclwNlOTKaiMIKfxIaiBMUCqsY4OrJBQvxqUCD5noYu2sRXvJhI60zQlzUuS8JpKKy1Km9LmTq4dJncrUxcD5pPVGneCE3dF++SuPaYV82RO9QugInJB2gXNAFQLJJCDQ724px2tPRTx17PO3U4XWJNKV3aVg+6GMn5HPcM75XEDldCfMzYVmz02/ubLaLKJXsz0Tn5f4+Y1zE4zAZMrgb2n1bVICyI57F9l2d/Tcxp771DX9BmwdPIKRoL0bqcVnTlQkOjVWUlEqI8HkRK2q7+bemXaEeS3se6l2GZFfpTd/+IBZfXnt716erc/NW9hrFWYdqsgbIQTEu8UaTC6qLyfxEqlctuA8G5yi5b/rNeDsHavjVVCNdgV/hBIPSfz8Sz9nj//ngV7Lvxo8o1s2YWxlT4jOdXCM05qgptUcKYvCK4tgUt/LKn2oQktv2nXj6aYIzaAnWjzwyXXyIIJpYqH+UDv8MYVb07K4CHtyPXqzaIlqYz23ppfuuhjs+NU0S2H3IQmSUstTUIYflyffHONNbUWLDT75FjP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 39e9ecbb-3571-42c5-6fe5-08d9367c0a17 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:21:02.4517 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gl741UvEGJlJNTjMdyvMNYwCa5lMtyojQ7abkWhVDPzmFh5JQdQJE75dyrD3Rnbe3bnD9T5N4WcU/AcONYburg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Redo the current CS ID calculations to match the reference code. Helper functions are introduced that will be expanded for future DF versions. Use u16 type for dst_fabric_id and component_id_mask values to accommodate larger bitfields in future DF versions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-24-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Added functions to data_fabric_ops. drivers/edac/amd64_edac.c | 52 ++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index fa8046e2b055..fc2cd288df0f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1112,6 +1112,8 @@ struct addr_ctx { struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + u16 (*get_dst_fabric_id)(struct addr_ctx *ctx); + u16 (*get_component_id_mask)(struct addr_ctx *ctx); u8 (*get_die_id_shift)(struct addr_ctx *ctx); u8 (*get_socket_id_shift)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); @@ -1230,6 +1232,16 @@ static u8 get_socket_id_shift_df2(struct addr_ctx *ctx) return (ctx->reg_fab_id_mask0 >> 28) & 0xF; } +static u16 get_dst_fabric_id_df2(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0xFF; +} + +static u16 get_component_id_mask_df2(struct addr_ctx *ctx) +{ + return (~(ctx->socket_id_mask | ctx->die_id_mask)) & 0xFF; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, @@ -1239,6 +1251,8 @@ struct data_fabric_ops df2_ops = { .get_masks = &get_masks_df2, .get_die_id_shift = &get_die_id_shift_df2, .get_socket_id_shift = &get_socket_id_shift_df2, + .get_dst_fabric_id = &get_dst_fabric_id_df2, + .get_component_id_mask = &get_component_id_mask_df2, }; struct data_fabric_ops *df_ops; @@ -1339,38 +1353,42 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) } } -static int calculate_cs_id(struct addr_ctx *ctx) +static u8 calc_level_bits(u8 id, u8 level_mask, u8 shift, u8 mask, u8 num_bits) { - u8 die_id_bit = 0, sock_id_bit, cs_mask = 0; + return (((id & level_mask) >> shift) & mask) << num_bits; +} - /* If interleaved over more than 1 channel: */ - if (ctx->intlv_num_chan) { - die_id_bit = ctx->intlv_num_chan; - cs_mask = (1 << die_id_bit) - 1; - ctx->cs_id = ctx->cs_fabric_id & cs_mask; - } +static int calculate_cs_id(struct addr_ctx *ctx) +{ + u16 dst_fabric_id = df_ops->get_dst_fabric_id(ctx); + u16 mask, num_intlv_bits = ctx->intlv_num_chan; - /* Return early if no die interleaving and no socket interleaving. */ - if (!(ctx->intlv_num_dies || ctx->intlv_num_sockets)) - return 0; + mask = df_ops->get_component_id_mask(ctx); + ctx->cs_id = (ctx->cs_fabric_id & mask) - (dst_fabric_id & mask); - sock_id_bit = die_id_bit; + mask = (1 << num_intlv_bits) - 1; + ctx->cs_id &= mask; /* If interleaved over more than 1 die: */ if (ctx->intlv_num_dies) { u8 die_id_shift = df_ops->get_die_id_shift(ctx); - sock_id_bit = die_id_bit + ctx->intlv_num_dies; - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->die_id_mask) - >> die_id_shift) << die_id_bit; + mask = (1 << ctx->intlv_num_dies) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->die_id_mask, + die_id_shift, mask, num_intlv_bits); + + num_intlv_bits += ctx->intlv_num_dies; } /* If interleaved over more than 1 socket: */ if (ctx->intlv_num_sockets) { u8 socket_id_shift = df_ops->get_socket_id_shift(ctx); - ctx->cs_id |= ((ctx->cs_fabric_id & ctx->socket_id_mask) - >> socket_id_shift) << sock_id_bit; + mask = (1 << ctx->intlv_num_sockets) - 1; + + ctx->cs_id |= calc_level_bits(ctx->cs_fabric_id, ctx->socket_id_mask, + socket_id_shift, mask, num_intlv_bits); } return 0; From patchwork Wed Jun 23 19:19:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3718FC48BE5 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LhK6gzqoSxRjJuRt7d6JJ1qQlkPmTEeFFfi5WndDE6nFN8Z2lJFk9C7WvhthStFyAEKBz+RBMLq1Nj5yltGFJQS6r1pdCgrD1tuj28SiZj00IDUX26gKQsMcOPRRFYWu9g125bzMaLEQMFZ89+Jnziw/63SZkDWDcpCBsffPWwlHRub0MO7Egrlc8bN8Cx9AG68pIt9msqcrmHE1WCL3ZzkGAtnDX+fSgHbDlQgLufGIxmrIghd7EzpCP7BCBMmPH0JiYRorHL6jrkmy9fYUA1j+taa7T+r3VgbHj87KdkS61L4kgo/zoXX0mqf5ZHLb/sOCGFLJA5PJrLW6QqJynzKs5CabZihhbxk344eJ7rpyHF6Nh23XqGzub0OVp3hjh4T6FWxUhvnKe5pVyWvmP5AbmEQkX+rb9kxY7np6nTHxLjz2jitoEgVhRtHZHXD3RehFVTpSa1mFbyv/JY3l/9IhFCC7yv9JQwkCOz3G5lp3XGNi2RXwtzDkt1dQaJs5OePnUH97F2TthFBRW4Y2SOulFe3CAA4kRyjBPnu/PV4qe5UAs/4ToZdZtnnIfXe0V+GMmi8Si1UW14078Y7cd7Ziw/vinhX6sypomHZXc7DlzHpCzRg2w11Ys8oqPsS8HrGi5WkiksCVsQa+eIULcoOCAyKAQq/IW2aLXPy/4EOuNbWTqybiQl+f5A5Pqgmba3021mz1a53t6Kz+gLrbkXEw3IyKldCfTvVBB1vQBDcRY+yftQw83G49vNd7djpUkXIwBM9NLCGra09DKEosnZdZ8lj7ut8mfatN6DC/tHe+d4dv/pDErYF07nDHtqaZrSAHQ3fa2MNE1/0Vp4Ync0y6sSNC/Sc9bPmonO62FIHnKZhWJSepb5ql+tYRWwvWsS8nV24CR+ko+nv+ODLUtnLDC+9LvJdMpaq9UFLIHbGTpMCPhJDgmi5nqY0oM5/PEtQ34+M481NTCXx8WfZyXok4oGeY7mJFfTxyRNUU+YslXjxqwjpA/oyPbG/oBu6RWWHRwqqtIsbQro3CFmJ3dpXcfj91MI7BHGj0VYoZWEZISlfMolH2alxznDZpuvdiYjsX+ZrDPfxit/arrIsZhyWM/4mO1zEz1AORmMX6B07e8UFQPPevBmNzn2ZIYxTMRJqm/xMJ95aEtizJvr4IxshLyAONOn062pYIBegzZeS4Hq3GqOf0KzASODOpGaMsH6F7wGp88Sx8BuAU0QFyvutIlH7jalHrYWJLaSy3zdPg4GWxKWdLuSoK59HpUfQzz4RNfbsqXq/y45n6GANIbrIHo59iDzRBVd1AiSfRpzhYaQCTs099QYfGW4THl5jj X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc944a60-af92-48e9-7fd7-08d9367c0aa4 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:21:03.4541 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pbPJIcgx+xNM5jV0lu6Redz9C8ukPJxSlfA14BZpHmRHYd8+y3xgjyQuqCGvl340MM1LHoChBzRxvVKzbecGjw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The reference code for DF2 hashing was changed to XOR the interleave address bit rather than the CS ID. Match that here. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-25-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index fc2cd288df0f..7ba6aa97e80d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1162,7 +1162,7 @@ static int dehash_addr_df2(struct addr_ctx *ctx) (ctx->ret_addr >> 18) ^ (ctx->ret_addr >> 21) ^ (ctx->ret_addr >> 30) ^ - ctx->cs_id; + (ctx->ret_addr >> ctx->intlv_addr_bit); hashed_bit &= BIT(0); From patchwork Wed Jun 23 19:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51789C4743C for ; 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Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-1-Yazen.Ghannam@amd.com v1->v2: * New in v2. drivers/edac/amd64_edac.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 7ba6aa97e80d..aa8b8d0b319d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1116,6 +1116,7 @@ struct data_fabric_ops { u16 (*get_component_id_mask)(struct addr_ctx *ctx); u8 (*get_die_id_shift)(struct addr_ctx *ctx); u8 (*get_socket_id_shift)(struct addr_ctx *ctx); + u8 (*get_intlv_addr_sel)(struct addr_ctx *ctx); int (*get_intlv_mode)(struct addr_ctx *ctx); int (*get_cs_fabric_id)(struct addr_ctx *ctx); int (*get_masks)(struct addr_ctx *ctx); @@ -1192,6 +1193,11 @@ static int get_intlv_mode_df2(struct addr_ctx *ctx) return 0; } +static u8 get_intlv_addr_sel_df2(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 8) & 0x7; +} + static void get_intlv_num_dies_df2(struct addr_ctx *ctx) { ctx->intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; @@ -1245,6 +1251,7 @@ static u16 get_component_id_mask_df2(struct addr_ctx *ctx) struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, .get_intlv_mode = &get_intlv_mode_df2, + .get_intlv_addr_sel = &get_intlv_addr_sel_df2, .get_intlv_num_dies = &get_intlv_num_dies_df2, .get_intlv_num_sockets = &get_intlv_num_sockets_df2, .get_cs_fabric_id = &get_cs_fabric_id_df2, @@ -1323,7 +1330,7 @@ static int get_dram_addr_map(struct addr_ctx *ctx) static int get_intlv_addr_bit(struct addr_ctx *ctx) { - u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { From patchwork Wed Jun 23 19:20:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF3B2C4743C for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iEgUmMfjk2JY06QPCvRO1XKUkmg764BN79kf6BOB0hYcrITY1noT4sYKxQGTZwrpVMAAdY5zLeZkKVnGkEr6f7Kam4yI207U1ewVV9fraEY1vsGZwYahYKpSv4qFzSeKl1xQx8KFJd1xuVay7eM3LqGZgsDdYX+EnXk5hDRPfU4fyQOj99fvNc3Tj6nYGl+7KA3tbuAPu8EKt7AKJK9G4vZT2BLIfAqhxUluRFMqcoS/dnLWv4vsuNanA9Y7/csINXbRMvdRzmlX1j9RlPuGeX3yWJP749opboXaUXs3WQIxLKS207z3Gx1BAFRu27eThS7AlL7j0h5kjxTmss9aMIvbxnPfZDQo4JtDx2Xr98shkx4J7of8YVDGoasgyW9dLENQxPz/pjySlNBoloE8srZc6oTjChukuIlGl9PhYDnkiXzni83zFMbvu2UBFWPj12t7Q+7uc7TZhSyENzBJRsUu0VW3Tz5N8Nsh94NQVNo4FBOQl+/x8KhW2tfEG9MWoBV2N/uQuD6xOLLOLpEtMO7g1XKszK8MLfICN0oBg3ss3eoYaH/pr38KbWzxhp8vaa3rJvuwPTuG0EHr9O/l97qBcLoPyiZvZpJkAuwPixW+RS0NPFhS3RLdnBwkgXxwE/dWbhSZYe5hkGGsSuPLXiQJ3v8rhydsjCZuOwSFlRKOOArWPtnAPU3qAmkIVj+GBa01t0jsrFtqiCeqCqI03JeLUiH+l4MpG6LQgblUbMp8XCKP7ikxICGTumsSZ0vfal4SDvC++x/6jVRNaJNWfrfvStnoaJFd92huTEz1wkPo32helGLKlQPtJ3ScMyaGP3UcHuJd7dLZz0XMD8R6zY4hijYgGiH3XfquzYe8Gos/2UkoxPMOAOC9l20tyxFmXpwjSiaGfh2gsNU4FXen2L/ySK/LcTfux+2v1/QErcAzUDVEzMBntcjwYS3NuAD3RcG4SVD948f0O3Pldr1Ki/9EbnU9yMN3Uax1TCajCJvWrwrlY5cK1t5oBkk4zDx/xTsQRjslzYzEkc8TeDElGAkhms/jk/aZwhKIwtw9YsLioobdnUiI7tLq1qMyxtu0WcRQ1rHsV3xiW2Xc6iZnq/MQ5m1y3DtoqLycvSEsuSb+cDqQHs5ry8BIoqIVSUAav/im7wUuIqajVXa2EgNKiQUykCZB98+NwMiA1tek0uuNl0T46BPqy7GgSuD5vo2x315D6ENBwDkUOHaSXQCRWQEADgmWKkNjmXKd9OJIm2l295NYgjdkuWlQVSNQixC9XhlzFNiSESzOLWWkdGbzO9gCOlj1vKLzgm4IPzVeTJdqHLg57ijVs7d1V/ajen2I X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d8e4b337-709e-49d5-c9ea-08d9367c0bce X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:21:05.3300 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YWs1h2bZdzn7yIgoKke/stxjCz1Or/z+GHQPUouJ43zB8ns0X7tH61SkdEXfZZkRXDG+Brl8jk5yoYWJqbb21w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DF3-based systems (Rome and later) support new interleaving modes and a number of bit fields have changed or moved entirely. Add support for these new modes and fields. Refactoring should be minimal due to earlier changes, and most updates will be additions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-26-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Use function pointers as needed. drivers/edac/amd64_edac.c | 189 +++++++++++++++++++++++++++++++++++++- 1 file changed, 187 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index aa8b8d0b319d..882ac3fbc832 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1059,9 +1059,11 @@ enum df_reg_names { DRAM_BASE_ADDR, DRAM_LIMIT_ADDR, DRAM_OFFSET, + DF_GLOBAL_CTL, /* Function 1 */ SYS_FAB_ID_MASK, + SYS_FAB_ID_MASK_1, }; static struct df_reg df_regs[] = { @@ -1075,14 +1077,23 @@ static struct df_reg df_regs[] = { [DRAM_LIMIT_ADDR] = {0, 0x114}, /* D18F0x1B4 (DramOffset) */ [DRAM_OFFSET] = {0, 0x1B4}, + /* D18F0x3F8 (DfGlobalCtrl) */ + [DF_GLOBAL_CTL] = {0, 0x3F8}, /* D18F1x208 (SystemFabricIdMask) */ [SYS_FAB_ID_MASK] = {1, 0x208}, + /* D18F1x20C (SystemFabricIdMask1) */ + [SYS_FAB_ID_MASK_1] = {1, 0x20C}, }; /* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ enum intlv_modes { NONE = 0x00, NOHASH_2CH = 0x01, + NOHASH_4CH = 0x03, + NOHASH_8CH = 0x05, + HASH_COD4_2CH = 0x0C, + HASH_COD2_4CH = 0x0D, + HASH_COD1_8CH = 0x0E, DF2_HASH_2CH = 0x21, }; @@ -1094,6 +1105,7 @@ struct addr_ctx { u32 reg_base_addr; u32 reg_limit_addr; u32 reg_fab_id_mask0; + u32 reg_fab_id_mask1; u16 cs_fabric_id; u16 die_id_mask; u16 socket_id_mask; @@ -1105,6 +1117,7 @@ struct addr_ctx { u8 intlv_num_dies; u8 intlv_num_sockets; u8 cs_id; + u8 node_id_shift; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); void (*insert_cs_id)(struct addr_ctx *ctx); @@ -1262,6 +1275,164 @@ struct data_fabric_ops df2_ops = { .get_component_id_mask = &get_component_id_mask_df2, }; +static u64 get_hi_addr_offset_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_dram_offset & GENMASK_ULL(31, 12)) << 16; +} + +static void make_space_for_cs_id_cod_hash(struct addr_ctx *ctx) +{ + u8 num_intlv_bits = ctx->intlv_num_chan; + + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, 1, &ctx->ret_addr); + if (num_intlv_bits > 1) + expand_bits(12, num_intlv_bits - 1, &ctx->ret_addr); +} + +static void insert_cs_id_cod_hash(struct addr_ctx *ctx) +{ + ctx->ret_addr |= ((ctx->cs_id & 0x1) << ctx->intlv_addr_bit); + ctx->ret_addr |= ((ctx->cs_id & 0xE) << 11); +} + +static int dehash_addr_df3(struct addr_ctx *ctx) +{ + u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G; + u32 tmp; + + if (amd_df_indirect_read(0, df_regs[DF_GLOBAL_CTL], DF_BROADCAST, &tmp)) + return -EINVAL; + + intlv_ctl_64k = !!((tmp >> 20) & 0x1); + intlv_ctl_2M = !!((tmp >> 21) & 0x1); + intlv_ctl_1G = !!((tmp >> 22) & 0x1); + + hashed_bit = (ctx->ret_addr >> 14) ^ + ((ctx->ret_addr >> 18) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 23) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 32) & intlv_ctl_1G) ^ + (ctx->ret_addr >> ctx->intlv_addr_bit); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + if (ctx->intlv_mode != HASH_COD2_4CH && + ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 12) ^ + ((ctx->ret_addr >> 16) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 21) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 30) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 12) & BIT(0))) + ctx->ret_addr ^= BIT(12); + + if (ctx->intlv_mode != HASH_COD1_8CH) + return 0; + + hashed_bit = (ctx->ret_addr >> 13) ^ + ((ctx->ret_addr >> 17) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> 22) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> 31) & intlv_ctl_1G); + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> 13) & BIT(0))) + ctx->ret_addr ^= BIT(13); + + return 0; +} + +static int get_intlv_mode_df3(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0xF; + + if (ctx->intlv_mode == HASH_COD4_2CH || + ctx->intlv_mode == HASH_COD2_4CH || + ctx->intlv_mode == HASH_COD1_8CH) { + ctx->make_space_for_cs_id = &make_space_for_cs_id_cod_hash; + ctx->insert_cs_id = &insert_cs_id_cod_hash; + ctx->dehash_addr = &dehash_addr_df3; + } else { + ctx->make_space_for_cs_id = &make_space_for_cs_id_simple; + ctx->insert_cs_id = &insert_cs_id_simple; + } + + return 0; +} + +static u8 get_intlv_addr_sel_df3(struct addr_ctx *ctx) +{ + return (ctx->reg_base_addr >> 9) & 0x7; +} + +static void get_intlv_num_dies_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_base_addr >> 6) & 0x3; +} + +static void get_intlv_num_sockets_df3(struct addr_ctx *ctx) +{ + ctx->intlv_num_sockets = (ctx->reg_base_addr >> 8) & 0x1; +} + +static u8 get_die_id_shift_df3(struct addr_ctx *ctx) +{ + return ctx->node_id_shift; +} + +static u8 get_socket_id_shift_df3(struct addr_ctx *ctx) +{ + return ((ctx->reg_fab_id_mask1 >> 8) & 0x3) + ctx->node_id_shift; +} + +static int get_masks_df3(struct addr_ctx *ctx) +{ + if (amd_df_indirect_read(0, df_regs[SYS_FAB_ID_MASK_1], + DF_BROADCAST, &ctx->reg_fab_id_mask1)) + return -EINVAL; + + ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF; + + ctx->die_id_mask = (ctx->reg_fab_id_mask1 >> 16) & 0x7; + ctx->die_id_mask <<= ctx->node_id_shift; + + ctx->socket_id_mask = (ctx->reg_fab_id_mask1 >> 24) & 0x7; + ctx->socket_id_mask <<= ctx->node_id_shift; + + return 0; +} + +static u16 get_dst_fabric_id_df3(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0x3FF; +} + +static u16 get_component_id_mask_df3(struct addr_ctx *ctx) +{ + return ctx->reg_fab_id_mask0 & 0x3FF; +} + +struct data_fabric_ops df3_ops = { + .get_hi_addr_offset = &get_hi_addr_offset_df3, + .get_intlv_mode = &get_intlv_mode_df3, + .get_intlv_addr_sel = &get_intlv_addr_sel_df3, + .get_intlv_num_dies = &get_intlv_num_dies_df3, + .get_intlv_num_sockets = &get_intlv_num_sockets_df3, + .get_cs_fabric_id = &get_cs_fabric_id_df2, + .get_masks = &get_masks_df3, + .get_die_id_shift = &get_die_id_shift_df3, + .get_socket_id_shift = &get_socket_id_shift_df3, + .get_dst_fabric_id = &get_dst_fabric_id_df3, + .get_component_id_mask = &get_component_id_mask_df3, +}; + struct data_fabric_ops *df_ops; static int set_df_ops(struct addr_ctx *ctx) @@ -1270,6 +1441,11 @@ static int set_df_ops(struct addr_ctx *ctx) DF_BROADCAST, &ctx->reg_fab_id_mask0)) return -EINVAL; + if ((ctx->reg_fab_id_mask0 & 0xFF) != 0) { + df_ops = &df3_ops; + return 0; + } + df_ops = &df2_ops; return 0; @@ -1332,8 +1508,8 @@ static int get_intlv_addr_bit(struct addr_ctx *ctx) { u8 intlv_addr_sel = df_ops->get_intlv_addr_sel(ctx); - /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ - if (intlv_addr_sel > 3) { + /* {0, 1, 2, 3, 4} map to address bits {8, 9, 10, 11, 12} respectively */ + if (intlv_addr_sel > 4) { pr_debug("Invalid interleave address select %d.\n", intlv_addr_sel); return -EINVAL; } @@ -1351,9 +1527,18 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) ctx->intlv_num_chan = 0; break; case NOHASH_2CH: + case HASH_COD4_2CH: case DF2_HASH_2CH: ctx->intlv_num_chan = 1; break; + case NOHASH_4CH: + case HASH_COD2_4CH: + ctx->intlv_num_chan = 2; + break; + case NOHASH_8CH: + case HASH_COD1_8CH: + ctx->intlv_num_chan = 3; + break; default: /* Valid interleaving modes where checked earlier. */ break; From patchwork Wed Jun 23 19:20:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 12340457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38FADC4743C for ; Wed, 23 Jun 2021 19:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AEAE611AD for ; Wed, 23 Jun 2021 19:23:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230151AbhFWTZh (ORCPT ); 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Wed, 23 Jun 2021 19:21:36 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 31/31] EDAC/amd64: Add glossary of acronyms for address translation Date: Wed, 23 Jun 2021 19:20:02 +0000 Message-Id: <20210623192002.3671647-32-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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Some terms may be seen with other AMD code, and some are only used within the translation code. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/YJqwpKBsKL1QKR5z@zn.tnic v1->v2: * New in v2. drivers/edac/amd64_edac.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 882ac3fbc832..d8557716d65e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -993,6 +993,15 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* + * Glossary of acronyms used in address translation for Zen-based systems + * + * COD = Cluster-on-Die + * CS = Coherent Slave + * DF = Data Fabric + * UMC = Unified Memory Controller + */ + /* Protect the PCI config register pairs used for DF indirect access. */ static DEFINE_MUTEX(df_indirect_mutex);