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Wed, 30 Jun 2021 14:50:46 +0000 From: Naveen Krishna Chatradhi To: linux-edac@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mingo@redhat.com, mchehab@kernel.org Subject: [PATCH 1/7] x86/amd_nb: Add Aldebaran device to PCI IDs Date: Wed, 30 Jun 2021 20:58:22 +0530 Message-Id: <20210630152828.162659-2-nchatrad@amd.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210630152828.162659-1-nchatrad@amd.com> References: <20210630152828.162659-1-nchatrad@amd.com> X-Originating-IP: [165.204.156.251] X-ClientProxiedBy: MAXPR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::24) To BL1PR12MB5286.namprd12.prod.outlook.com (2603:10b6:208:31d::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from SLES15.amd.com (165.204.156.251) by MAXPR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.22 via Frontend Transport; Wed, 30 Jun 2021 14:50:43 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 338b5eed-3769-4340-1c03-08d93bd67141 X-MS-TrafficTypeDiagnostic: BL1PR12MB5045: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; 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Since this device has a configurable PCIe endpoint, it could be used with different drivers. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- include/linux/pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 4bac1831de80..d9aae90dfce9 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -554,6 +554,7 @@ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443 +#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F3 0x14d3 #define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 From patchwork Wed Jun 30 15:28:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12352285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B49C11F6B for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YwinvCKr7lsyU7qZhecfWD4lGtIIYW1yey03pRufPR9Tdo8xrYYK1p9w8hwq3w8hIYpZtdNtd4kmtzBa5UBRieOBwIiX21vSbKHV7hdNh9yONUgJU/H6HwhH8HebuxA9ynkVX9x0wCT0YTEf0SttW3E+ML3hPbNr5SO2sxrmoX5/oFRBkd9Wysiw0nV8U+iYqIJ1JT9AqYRkJzYLsO7Y8PQUmAuyUAfMGL4B1Q1Q/wpLnbLDHIhVqR6wRb63l5HHMxqYUD61rqCOmUi3HNoldSYpdhCfOFYVqsKup38PLcdWTeffVsvpxSh8v4BCP/ulglKCogb7Zsy6zhInElvuUJ/iRLPKbY19P6V2wqHN+ivs2L4yy69HAAgXXYy0TWmyCkZ/PKAQXYGji9McocDw/2XdeHxelOwaruRAPJAYjOzHE7uUoqiwsD6Ig6R/72fk4qhDudkzbBjVm/iq+K+ujTWQoisIK7Vr2Zd+sXq3chC9jmPJcs4g0aMTpNs2tbr9X9Wn99ZNonBQlXMjL4DI1qA73FAwiOC5pt5lQoPjsr3lRX+HMfoOkb+n0jB8zUaHX/iyKfcRsWYCQjI86K+OvMWfcUiLLVhO+kC6rfPdMwpTZ20pVHEawesjHFFSwJFI+E1Gl/Wiem5S46n4mlDcZdlKweTaz4hyz+/Il42htrdoOnyC6VYJHGZ8sqnw/cOxJi/ZUGkI2d41FY/vstR6zyMheJ9h3PJwX1Bnqw3ZJMBFoGNFunQe+QgdL/+QKCpvZKw0YdmShE2Ibyo51Bf/7csTJzty2R5vQ91JXuqMiUG6iPuzcs6iLotmY8LHBEiqiSFDlVmF4dONwsYTOaNBRfOJ5Y68ETdjVidq8xnJ5Y0Ex2WpA0JHtGFpw5EoBZG3dvw4k/nErAzNy8gFq/ZILRZuJCxmG7NpKmLlRlCAOxGe+WSVeyOpEj8KmgeQmP2Tez/ZPXrV7VDjxFwKgKE8ZQZyjvcL53od1WtFSpLIGmX0Dgeaw8VWcvdSgLxIPrNotRmE1mttrl7AURAK1aK7DdVUum0okpJ4lvJwAq7H2zCJ7yZBzATBxjZgL+wNJF3UY9/cYUVV00KI+sVMkhAf/nMblUSKqF/VCTNNgq1D5/AlQUuI48d2cASnXRUqjcsQmECj9jGuEKhJt5xVvIqoGtH6Md7EDqTVeoRrwM66QN5K708jRB/qiMSQFUSHWhwtm+7BRSwYjYwgNztSSod/eRH7Iaehd7xjoZIePowCKriG8B1pbA9mtQQiy+Z1jooq3l8gUxYS7eRF2gwdfDjFH5Cx5aw+Bk4CnDkMaUjZJORV7FVHxqSoPwwu9FESuxIm X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 13fd25ae-731f-4710-cd27-08d93bd67332 X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2021 14:50:49.4929 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mUW1+PDp3DIkknJRb8lrAUodopL5QJDnDlHR4ytDee6SvpTvEnhO+2cb3YyfolQeHGtXMMVBHI/06mku5OU55Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5045 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K On newer heterogeneous systems from AMD, there is a possibility of having GPU nodes along with CPU nodes with the MCA banks. The GPU nodes (noncpu nodes) starts enumerating from northbridge index 8. Aldebaran GPUs have 2 root ports, with 4 misc port for each root. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- arch/x86/include/asm/amd_nb.h | 6 ++++ arch/x86/kernel/amd_nb.c | 62 ++++++++++++++++++++++++++++++++--- 2 files changed, 63 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 00d1a400b7a1..e71581cf00e3 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -79,6 +79,12 @@ struct amd_northbridge_info { #ifdef CONFIG_AMD_NB +/* + * On Newer heterogeneous systems from AMD with CPU and GPU nodes connected + * via xGMI links, the NON CPU Nodes are enumerated from index 8 + */ +#define NONCPU_NODE_INDEX 8 + u16 amd_nb_num(void); bool amd_nb_has_feature(unsigned int feature); struct amd_northbridge *node_to_amd_nb(int node); diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 5884dfa619ff..489003e850dd 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -26,6 +26,8 @@ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e +#define PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT 0x14bb +#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4 0x14d4 /* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); @@ -94,6 +96,21 @@ static const struct pci_device_id hygon_nb_link_ids[] = { {} }; +static const struct pci_device_id amd_noncpu_root_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT) }, + {} +}; + +static const struct pci_device_id amd_noncpu_nb_misc_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F3) }, + {} +}; + +static const struct pci_device_id amd_noncpu_nb_link_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4) }, + {} +}; + const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { { 0x00, 0x18, 0x20 }, { 0xff, 0x00, 0x20 }, @@ -182,11 +199,16 @@ int amd_cache_northbridges(void) const struct pci_device_id *misc_ids = amd_nb_misc_ids; const struct pci_device_id *link_ids = amd_nb_link_ids; const struct pci_device_id *root_ids = amd_root_ids; + + const struct pci_device_id *noncpu_misc_ids = amd_noncpu_nb_misc_ids; + const struct pci_device_id *noncpu_link_ids = amd_noncpu_nb_link_ids; + const struct pci_device_id *noncpu_root_ids = amd_noncpu_root_ids; + struct pci_dev *root, *misc, *link; struct amd_northbridge *nb; u16 roots_per_misc = 0; - u16 misc_count = 0; - u16 root_count = 0; + u16 misc_count = 0, misc_count_noncpu = 0; + u16 root_count = 0, root_count_noncpu = 0; u16 i, j; if (amd_northbridges.num) @@ -205,10 +227,16 @@ int amd_cache_northbridges(void) if (!misc_count) return -ENODEV; + while ((misc = next_northbridge(misc, noncpu_misc_ids)) != NULL) + misc_count_noncpu++; + root = NULL; while ((root = next_northbridge(root, root_ids)) != NULL) root_count++; + while ((root = next_northbridge(root, noncpu_root_ids)) != NULL) + root_count_noncpu++; + if (root_count) { roots_per_misc = root_count / misc_count; @@ -222,15 +250,27 @@ int amd_cache_northbridges(void) } } - nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL); + /* + * The valid amd_northbridges are in between (0 ~ misc_count) and + * (NONCPU_NODE_INDEX ~ NONCPU_NODE_INDEX + misc_count_noncpu) + */ + if (misc_count_noncpu) + /* + * There are NONCPU Nodes with pci root ports starting at index 8 + * allocate few extra cells for simplicity in handling the indexes + */ + amd_northbridges.num = NONCPU_NODE_INDEX + misc_count_noncpu; + else + amd_northbridges.num = misc_count; + + nb = kcalloc(amd_northbridges.num, sizeof(struct amd_northbridge), GFP_KERNEL); if (!nb) return -ENOMEM; amd_northbridges.nb = nb; - amd_northbridges.num = misc_count; link = misc = root = NULL; - for (i = 0; i < amd_northbridges.num; i++) { + for (i = 0; i < misc_count; i++) { node_to_amd_nb(i)->root = root = next_northbridge(root, root_ids); node_to_amd_nb(i)->misc = misc = @@ -251,6 +291,18 @@ int amd_cache_northbridges(void) root = next_northbridge(root, root_ids); } + link = misc = root = NULL; + if (misc_count_noncpu) { + for (i = NONCPU_NODE_INDEX; i < NONCPU_NODE_INDEX + misc_count_noncpu; i++) { + node_to_amd_nb(i)->root = root = + next_northbridge(root, noncpu_root_ids); + node_to_amd_nb(i)->misc = misc = + next_northbridge(misc, noncpu_misc_ids); + node_to_amd_nb(i)->link = link = + next_northbridge(link, noncpu_link_ids); + } + } + if (amd_gart_present()) amd_northbridges.flags |= AMD_NB_GART; From patchwork Wed Jun 30 15:28:24 2021 Content-Type: text/plain; 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Wed, 30 Jun 2021 14:50:52 +0000 From: Naveen Krishna Chatradhi To: linux-edac@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mingo@redhat.com, mchehab@kernel.org Subject: [PATCH 3/7] EDAC/mc: Add new HBM2 memory type Date: Wed, 30 Jun 2021 20:58:24 +0530 Message-Id: <20210630152828.162659-4-nchatrad@amd.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210630152828.162659-1-nchatrad@amd.com> References: <20210630152828.162659-1-nchatrad@amd.com> X-Originating-IP: [165.204.156.251] X-ClientProxiedBy: MAXPR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::24) To BL1PR12MB5286.namprd12.prod.outlook.com (2603:10b6:208:31d::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from SLES15.amd.com (165.204.156.251) by MAXPR01CA0082.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.22 via Frontend Transport; Wed, 30 Jun 2021 14:50:49 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 275ddce6-f39e-473a-c162-08d93bd67509 X-MS-TrafficTypeDiagnostic: BL1PR12MB5045: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2043; 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Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi Reviewed-by: Yazen Ghannam --- drivers/edac/edac_mc.c | 1 + include/linux/edac.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index f6d462d0be2d..2c5975674723 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -166,6 +166,7 @@ const char * const edac_mem_types[] = { [MEM_DDR5] = "Unbuffered-DDR5", [MEM_NVDIMM] = "Non-volatile-RAM", [MEM_WIO2] = "Wide-IO-2", + [MEM_HBM2] = "High-bandwidth-memory-Gen2", }; EXPORT_SYMBOL_GPL(edac_mem_types); diff --git a/include/linux/edac.h b/include/linux/edac.h index 76d3562d3006..4207d06996a4 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -184,6 +184,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * @MEM_DDR5: Unbuffered DDR5 RAM * @MEM_NVDIMM: Non-volatile RAM * @MEM_WIO2: Wide I/O 2. + * @MEM_HBM2: High bandwidth Memory Gen 2. */ enum mem_type { MEM_EMPTY = 0, @@ -212,6 +213,7 @@ enum mem_type { MEM_DDR5, MEM_NVDIMM, MEM_WIO2, + MEM_HBM2, }; #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) @@ -239,6 +241,7 @@ enum mem_type { #define MEM_FLAG_DDR5 BIT(MEM_DDR5) #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) #define MEM_FLAG_WIO2 BIT(MEM_WIO2) +#define MEM_FLAG_HBM2 BIT(MEM_HBM2) /** * enum edac_type - Error Detection and Correction capabilities and mode From patchwork Wed Jun 30 15:28:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12352289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B83CC11F65 for ; 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Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- drivers/edac/mce_amd.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 27d56920b469..364dfb6e359d 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1049,6 +1049,7 @@ static void decode_smca_error(struct mce *m) enum smca_bank_types bank_type; const char *ip_name; u8 xec = XEC(m->status, xec_mask); + u32 node_id = 0; if (m->bank >= ARRAY_SIZE(smca_banks)) return; @@ -1072,8 +1073,18 @@ static void decode_smca_error(struct mce *m) if (xec < smca_mce_descs[bank_type].num_descs) pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]); - if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) - decode_dram_ecc(topology_die_id(m->extcpu), m); + /* + * SMCA_UMC_V2 is used on the noncpu nodes, extract the node id + * from the InstanceHI[47:44] of the IPID register. + */ + if (bank_type == SMCA_UMC_V2 && xec == 0) + node_id = ((m->ipid >> 44) & 0xF); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UJy6klG1B0w2v5PBV4Q3yvYyvNGYTWBF2GNvtsO3rvbRJrVDSHmFhGsyLQNHZF3qmw3N4+mk4r82QyeYvhXJK4ClQBFTP1eeJVab/rusOWfqQcGzQlcKNpBHGJbpPlseYsZ7pYS3xm8pfvpslengNlmz5JCCEyKNfDzvl4Sa9LzjwktGfnXIbbFtTvwdbYlQVLlroMPJ2syPsLNeqx/7unmWcl4jPJySZdn637S7CaKPW8Op1Oyk9Y6CEEdPL0UyTFFqw3jQ9cq4c0DyxSijrgURnsenjHBVUEvByQ/5OiZMviZYxkzrHKeUg6Hr4fjQcIJNSmAdBwoHCfutFBASuAQlSJcryMUahSFm1SgLzVeqRwwtBl/Wfcf3RjtIXnKKuIpqMzKl1oZatD4Xv1OFUNShJBTqZ4dT5DJ8mP9oIHjvZcUq+/fwoTch4D3CSSIMxGRDonAiojkd7+sSdw5RVFSxXOnJExT0pkUXFCkFoLaocsrkeOjoSeneTY97TbvNK7apoMt5Jr82aOmjayhyad9TfKuN7yytVw65LrjkAbASxOVrUmi9iXWztr3yFpjbXtfJrfeA3cLMj6RTtdHZ9EUMSblsj27l6yHw9Mlvj2JgVJ9/sX6LyKTh6pyig+meNMQWADDAkeEwaOijUVMxC2CK7GF1KKDVh5zcFHCzsZ3qsXt+zXNgAtg1MOu9BlisKZJzuhD3pJoLnVFoHEQTxurfUf9IfpYbk6eAp7lC+BmWNLLATH74OEnuMDNpg/9NrpcU5PSyNMbh+riM7RfFpGw50kgYELItSsDeKVCpPy+FB5LCq7edqjnRgTek5VFM8psDF+DfdyCt2vOirNIjj6hSOldxjOxDbWvUMHmSasos3cSuFol55TWdmno6dlx1XJLw0r9jIBPmVqFmvrZzqnn145y2NS3gTR2tdhOyZAgn3YqiJ/vfNtC6TwvBsj9ZAUwLpASI6nzV+8ozK7HeT2YRM+DW5IVJdoHEd4g7LBcz1j6tczHkZ9iLmfxCZtmEoeVVDtF1ttIXxWq9iJsTLYuItvvpBPa1e9FrOTQHdMlSpoMpJdEF0AyrecwVy2i8uNFyYwTKaJ8VmhBPyQHgZ+SrdPgzEBpPbstfrd3N76Ht0cO4oTDe6vJk3JJOzAT7nhGLBjmsWVc1eCHca5Jev0oSOf2+12yDCB3M34E/caDO8Ci2Dt0WDzxBNAgYr4foHMi9s9Z9LsOP80CJhVHNnKJWdrUm8vX3Xd6DB0Vzm2P01BqK1RNJwIuePpqzsDQhKZzIqrsTjFtbhzU8AgujkiD+FzztNOXma46hgYlG5hfPZLtjDJLQCnDKhYd90FGS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5339eceb-daab-40f5-2109-08d93bd678a5 X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2021 14:50:58.5312 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Mh68rNrlvlI+IIgPeJ1qBDaowpa1pLvcw8m8fBxJ6TFSL4vuZWcVhwTSB2xA8Ij0Yvv7kG1dN2cyxz+0HJzSjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5045 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On newer heterogeneous systems from AMD with GPU nodes connected via xGMI links to the CPUs, the GPU dies are interfaced with HBM2 memory. This patch modifies the amd64_edac module to handle the HBM memory enumeration leveraging the existing edac and the amd64 specific data structures. The UMC Phys on GPU nodes are enumerated as csrows The UMC channels connected to HBMs are enumerated as ranks Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- drivers/edac/amd64_edac.c | 300 +++++++++++++++++++++++++++++--------- drivers/edac/amd64_edac.h | 27 ++++ 2 files changed, 259 insertions(+), 68 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 25c6362e414b..8fe0a5e3c8f2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1741,6 +1741,9 @@ static unsigned long determine_edac_cap(struct amd64_pvt *pvt) if (umc_en_mask == dimm_ecc_en_mask) edac_cap = EDAC_FLAG_SECDED; + + if (pvt->is_noncpu) + edac_cap = EDAC_FLAG_EC; } else { bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) ? 19 @@ -1799,6 +1802,9 @@ static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) { int cs_mode = 0; + if (pvt->is_noncpu) + return CS_EVEN_PRIMARY | CS_ODD_PRIMARY; + if (csrow_enabled(2 * dimm, ctrl, pvt)) cs_mode |= CS_EVEN_PRIMARY; @@ -1818,6 +1824,15 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl); + if (pvt->is_noncpu) { + cs_mode = f17_get_cs_mode(cs0, ctrl, pvt); + for_each_chip_select(cs0, ctrl, pvt) { + size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); + amd64_info(EDAC_MC ": %d: %5dMB\n", cs0, size0); + } + return; + } + for (dimm = 0; dimm < 2; dimm++) { cs0 = dimm * 2; cs1 = dimm * 2 + 1; @@ -1833,43 +1848,53 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) } } -static void __dump_misc_regs_df(struct amd64_pvt *pvt) +static void dump_umcch_regs(struct amd64_pvt *pvt, int i) { - struct amd64_umc *umc; - u32 i, tmp, umc_base; - - for_each_umc(i) { - umc_base = get_umc_base(i); - umc = &pvt->umc[i]; + struct amd64_umc *umc = &pvt->umc[i]; + u32 tmp, umc_base; - edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); + if (pvt->is_noncpu) { edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); + edac_dbg(1, "UMC%d All HBMs support ECC: yes\n", i); + return; + } - amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); - edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp); - - amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); - edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp); - edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); - - edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n", - i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", - (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); - edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n", - i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); - edac_dbg(1, "UMC%d x4 DIMMs present: %s\n", - i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); - edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", - i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); - - if (pvt->dram_type == MEM_LRDDR4) { - amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); - edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", - i, 1 << ((tmp >> 4) & 0x3)); - } + umc_base = get_umc_base(i); + + edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); + + amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); + edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp); + + amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); + edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp); + edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); + edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n", + i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", + (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); + edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n", + i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); + edac_dbg(1, "UMC%d x4 DIMMs present: %s\n", + i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); + edac_dbg(1, "UMC%d x16 DIMMs present: %s\n", + i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); + + if (pvt->dram_type == MEM_LRDDR4) { + amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); + edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n", + i, 1 << ((tmp >> 4) & 0x3)); + } +} + +static void __dump_misc_regs_df(struct amd64_pvt *pvt) +{ + int i; + + for_each_umc(i) { + dump_umcch_regs(pvt, i); debug_display_dimm_sizes_df(pvt, i); } @@ -1937,10 +1962,14 @@ static void prep_chip_selects(struct amd64_pvt *pvt) pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; } else if (pvt->fam >= 0x17) { int umc; - for_each_umc(umc) { - pvt->csels[umc].b_cnt = 4; - pvt->csels[umc].m_cnt = 2; + if (pvt->is_noncpu) { + pvt->csels[umc].b_cnt = 8; + pvt->csels[umc].m_cnt = 8; + } else { + pvt->csels[umc].b_cnt = 4; + pvt->csels[umc].m_cnt = 2; + } } } else { @@ -1949,6 +1978,31 @@ static void prep_chip_selects(struct amd64_pvt *pvt) } } +static void read_noncpu_umc_base_mask(struct amd64_pvt *pvt) +{ + u32 base_reg, mask_reg; + u32 *base, *mask; + int umc, cs; + + for_each_umc(umc) { + for_each_chip_select(cs, umc, pvt) { + base_reg = get_noncpu_umc_base(umc, cs) + UMCCH_BASE_ADDR; + base = &pvt->csels[umc].csbases[cs]; + + if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) + edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n", + umc, cs, *base, base_reg); + + mask_reg = get_noncpu_umc_base(umc, cs) + UMCCH_ADDR_MASK; + mask = &pvt->csels[umc].csmasks[cs]; + + if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) + edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n", + umc, cs, *mask, mask_reg); + } + } +} + static void read_umc_base_mask(struct amd64_pvt *pvt) { u32 umc_base_reg, umc_base_reg_sec; @@ -2009,8 +2063,12 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) prep_chip_selects(pvt); - if (pvt->umc) - return read_umc_base_mask(pvt); + if (pvt->umc) { + if (pvt->is_noncpu) + return read_noncpu_umc_base_mask(pvt); + else + return read_umc_base_mask(pvt); + } for_each_chip_select(cs, 0, pvt) { int reg0 = DCSB0 + (cs * 4); @@ -2056,6 +2114,10 @@ static void determine_memory_type(struct amd64_pvt *pvt) u32 dram_ctrl, dcsm; if (pvt->umc) { + if (pvt->is_noncpu) { + pvt->dram_type = MEM_HBM2; + return; + } if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) pvt->dram_type = MEM_LRDDR4; else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) @@ -2445,7 +2507,10 @@ static int f17_early_channel_count(struct amd64_pvt *pvt) /* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */ for_each_umc(i) - channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); + if (pvt->is_noncpu) + channels += pvt->csels[i].b_cnt; + else + channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); amd64_info("MCT channel count: %d\n", channels); @@ -2586,6 +2651,12 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, u32 msb, weight, num_zero_bits; int dimm, size = 0; + if (pvt->is_noncpu) { + addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; + /* The memory channels in case of GPUs are fully populated */ + goto skip_noncpu; + } + /* No Chip Selects are enabled. */ if (!cs_mode) return size; @@ -2611,6 +2682,7 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, else addr_mask_orig = pvt->csels[umc].csmasks[dimm]; + skip_noncpu: /* * The number of zero bits in the mask is equal to the number of bits * in a full mask minus the number of bits in the current mask. @@ -3356,6 +3428,16 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f17_addr_mask_to_cs_size, } }, + [ALDEBARAN_GPUS] = { + .ctl_name = "ALDEBARAN", + .f0_id = PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F0, + .f6_id = PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F6, + .max_mcs = 4, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_addr_mask_to_cs_size, + } + }, }; /* @@ -3611,6 +3693,19 @@ static int find_umc_channel(struct mce *m) return (m->ipid & GENMASK(31, 0)) >> 20; } +/* + * The HBM memory managed by the UMCCH of the noncpu node + * can be calculated based on the [15:12]bits of IPID as follows + */ +static int find_umc_channel_noncpu(struct mce *m) +{ + u8 umc, ch; + + umc = find_umc_channel(m); + ch = ((m->ipid >> 12) & 0xf); + return umc % 2 ? (ch + 4) : ch; +} + static void decode_umc_error(int node_id, struct mce *m) { u8 ecc_type = (m->status >> 45) & 0x3; @@ -3618,6 +3713,7 @@ static void decode_umc_error(int node_id, struct mce *m) struct amd64_pvt *pvt; struct err_info err; u64 sys_addr = m->addr; + u8 umc_num; mci = edac_mc_find(node_id); if (!mci) @@ -3630,7 +3726,16 @@ static void decode_umc_error(int node_id, struct mce *m) if (m->status & MCI_STATUS_DEFERRED) ecc_type = 3; - err.channel = find_umc_channel(m); + if (pvt->is_noncpu) { + err.csrow = find_umc_channel(m) / 2; + /* The UMC channel is reported as the csrow in case of the noncpu nodes */ + err.channel = find_umc_channel_noncpu(m); + umc_num = err.csrow * 8 + err.channel; + } else { + err.channel = find_umc_channel(m); + err.csrow = m->synd & 0x7; + umc_num = err.channel; + } if (!(m->status & MCI_STATUS_SYNDV)) { err.err_code = ERR_SYND; @@ -3646,9 +3751,7 @@ static void decode_umc_error(int node_id, struct mce *m) err.err_code = ERR_CHANNEL; } - err.csrow = m->synd & 0x7; - - if (umc_normaddr_to_sysaddr(&sys_addr, pvt->mc_node_id, err.channel)) { + if (umc_normaddr_to_sysaddr(&sys_addr, pvt->mc_node_id, umc_num)) { err.err_code = ERR_NORM_ADDR; goto log_error; } @@ -3775,15 +3878,20 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) /* Read registers from each UMC */ for_each_umc(i) { + if (pvt->is_noncpu) + umc_base = get_noncpu_umc_base(i, 0); + else + umc_base = get_umc_base(i); - umc_base = get_umc_base(i); umc = &pvt->umc[i]; - - amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); - amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); + + if (!pvt->is_noncpu) { + amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); + amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); + } } } @@ -3865,7 +3973,9 @@ static void read_mc_regs(struct amd64_pvt *pvt) determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); - determine_ecc_sym_sz(pvt); + /* ECC symbol size is not available on NONCPU nodes */ + if (!pvt->is_noncpu) + determine_ecc_sym_sz(pvt); } /* @@ -3953,15 +4063,21 @@ static int init_csrows_df(struct mem_ctl_info *mci) continue; empty = 0; - dimm = mci->csrows[cs]->channels[umc]->dimm; + if (pvt->is_noncpu) { + dimm = mci->csrows[umc]->channels[cs]->dimm; + dimm->edac_mode = EDAC_SECDED; + dimm->dtype = DEV_X16; + } else { + dimm->edac_mode = edac_mode; + dimm->dtype = dev_type; + dimm = mci->csrows[cs]->channels[umc]->dimm; + } edac_dbg(1, "MC node: %d, csrow: %d\n", pvt->mc_node_id, cs); dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); dimm->mtype = pvt->dram_type; - dimm->edac_mode = edac_mode; - dimm->dtype = dev_type; dimm->grain = 64; } } @@ -4226,7 +4342,9 @@ static bool ecc_enabled(struct amd64_pvt *pvt) umc_en_mask |= BIT(i); - if (umc->umc_cap_hi & UMC_ECC_ENABLED) + /* ECC is enabled by default on NONCPU nodes */ + if (pvt->is_noncpu || + (umc->umc_cap_hi & UMC_ECC_ENABLED)) ecc_en_mask |= BIT(i); } @@ -4262,6 +4380,11 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) { u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; + if (pvt->is_noncpu) { + mci->edac_ctl_cap |= EDAC_SECDED; + return; + } + for_each_umc(i) { if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); @@ -4292,7 +4415,11 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) { struct amd64_pvt *pvt = mci->pvt_info; - mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; + if (pvt->is_noncpu) + mci->mtype_cap = MEM_FLAG_HBM2; + else + mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; + mci->edac_ctl_cap = EDAC_FLAG_NONE; if (pvt->umc) { @@ -4397,11 +4524,25 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) fam_type = &family_types[F17_M70H_CPUS]; pvt->ops = &family_types[F17_M70H_CPUS].ops; fam_type->ctl_name = "F19h_M20h"; - break; + } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { + if (pvt->is_noncpu) { + int tmp = 0; + + fam_type = &family_types[ALDEBARAN_GPUS]; + pvt->ops = &family_types[ALDEBARAN_GPUS].ops; + tmp = pvt->mc_node_id - NONCPU_NODE_INDEX; + sprintf(pvt->buf, "Aldebaran#%ddie#%d", tmp / 2, tmp % 2); + fam_type->ctl_name = pvt->buf; + } else { + fam_type = &family_types[F19_CPUS]; + pvt->ops = &family_types[F19_CPUS].ops; + fam_type->ctl_name = "F19h_M30h"; + } + } else { + fam_type = &family_types[F19_CPUS]; + pvt->ops = &family_types[F19_CPUS].ops; + family_types[F19_CPUS].ctl_name = "F19h"; } - fam_type = &family_types[F19_CPUS]; - pvt->ops = &family_types[F19_CPUS].ops; - family_types[F19_CPUS].ctl_name = "F19h"; break; default: @@ -4454,6 +4595,30 @@ static void hw_info_put(struct amd64_pvt *pvt) kfree(pvt->umc); } +static void populate_layers(struct amd64_pvt *pvt, struct edac_mc_layer *layers) +{ + if (pvt->is_noncpu) { + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = fam_type->max_mcs; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = pvt->csels[0].b_cnt; + layers[1].is_virt_csrow = false; + } else { + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = pvt->csels[0].b_cnt; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + /* + * Always allocate two channels since we can have setups with + * DIMMs on only one channel. Also, this simplifies handling + * later for the price of a couple of KBs tops. + */ + layers[1].size = fam_type->max_mcs; + layers[1].is_virt_csrow = false; + } +} + static int init_one_instance(struct amd64_pvt *pvt) { struct mem_ctl_info *mci = NULL; @@ -4469,19 +4634,8 @@ static int init_one_instance(struct amd64_pvt *pvt) if (pvt->channel_count < 0) return ret; - ret = -ENOMEM; - layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; - layers[0].size = pvt->csels[0].b_cnt; - layers[0].is_virt_csrow = true; - layers[1].type = EDAC_MC_LAYER_CHANNEL; - - /* - * Always allocate two channels since we can have setups with DIMMs on - * only one channel. Also, this simplifies handling later for the price - * of a couple of KBs tops. - */ - layers[1].size = fam_type->max_mcs; - layers[1].is_virt_csrow = false; + /* Define layers for CPU and NONCPU nodes */ + populate_layers(pvt, layers); mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); if (!mci) @@ -4525,6 +4679,9 @@ static int probe_one_instance(unsigned int nid) struct ecc_settings *s; int ret; + if (!F3) + return -EINVAL; + ret = -ENOMEM; s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); if (!s) @@ -4536,6 +4693,9 @@ static int probe_one_instance(unsigned int nid) if (!pvt) goto err_settings; + if (nid >= NONCPU_NODE_INDEX) + pvt->is_noncpu = true; + pvt->mc_node_id = nid; pvt->F3 = F3; @@ -4609,6 +4769,10 @@ static void remove_one_instance(unsigned int nid) struct mem_ctl_info *mci; struct amd64_pvt *pvt; + /* Nothing to remove for the space holder entries */ + if (!F3) + return; + /* Remove from EDAC CORE tracking list */ mci = edac_mc_del_mc(&F3->dev); if (!mci) @@ -4682,7 +4846,7 @@ static int __init amd64_edac_init(void) for (i = 0; i < amd_nb_num(); i++) { err = probe_one_instance(i); - if (err) { + if (err && (err != -EINVAL)) { /* unwind properly */ while (--i >= 0) remove_one_instance(i); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 85aa820bc165..6d5f7b3afc83 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -126,6 +126,8 @@ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 +#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F0 0x14D0 +#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F6 0x14D6 /* * Function 1 - Address Map @@ -298,6 +300,7 @@ enum amd_families { F17_M60H_CPUS, F17_M70H_CPUS, F19_CPUS, + ALDEBARAN_GPUS, NUM_FAMILIES, }; @@ -389,6 +392,9 @@ struct amd64_pvt { enum mem_type dram_type; struct amd64_umc *umc; /* UMC registers */ + char buf[20]; + + u8 is_noncpu; }; enum err_codes { @@ -410,6 +416,27 @@ struct err_info { u32 offset; }; +static inline u32 get_noncpu_umc_base(u8 umc, u8 channel) +{ + /* + * On the NONCPU nodes, base address is calculated based on + * UMC channel and the HBM channel. + * + * UMC channels are selected in 6th nibble + * UMC chY[3:0]= [(chY*2 + 1) : (chY*2)]50000; + * + * HBM channels are selected in 3rd nibble + * HBM chX[3:0]= [Y ]5X[3:0]000; + * HBM chX[7:4]= [Y+1]5X[3:0]000 + */ + umc *= 2; + + if (channel / 4) + umc++; + + return 0x50000 + (umc << 20) + ((channel % 4) << 12); +} + static inline u32 get_umc_base(u8 channel) { /* chY: 0xY50000 */ From patchwork Wed Jun 30 15:28:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12352293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75E8BC11F69 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: G8LDM2OXK0MvfjDrG5Dq7HW9pYfEnYIJqjct9bhX0fwFLZ6zKtHfR6X93jcdWZu6RdlkXF7dzhZoeCaF/kReRajBGJCKUzc1vedAy+MEMPmUOSpMmvkJrkj3W49Asrup3mpiAgwYnjWJSw2uOJMmdYWhGfGephn3Smv/5rIssF16ZnRclFVjq5H1rlVLayLOcI5FytarCNUpXg5yDtvvtGsfuSH3v6vBYc0kUmcOZ8Ymh0WcEN2uZNyGmgoNewnJmiWZHn6W/jzJDWLFCXASLOQNK6ItZS/nSg9Dxlz6j9yFuT7H1mkDP3e9vP0GpOJAwH9N1J+NswiqZvVK9ZeX9XvDuQA8tDA6r4yW/UnyHzcWjijXfMADkpI7TNG1UfM8T+lQG+54BGmDGVXkqz4OC7LXBq/CXPWg2GjzPe5NJ4RSQ4C9tBNMR4MpchJDTEMbefcFSgjWmACFSVRX3Gy6yZ+d/4l0nyFv+cAwnmfVQCa53VH1cHdFuv0gUCBNJS/WCWIuR1gE/lMH6y1w0/MHNUrq5iJodk+4pJicAtAiZhEaxX+FvMVAuhoaL04ZGBkCUKp1qwmtZTsjGhgsyjv1lP6m57WfFRzhtT2tpiYyiYBFCO5D8TNMNwg58gOjM7l6RWn/vM9yYbonnssQ5I7/FMUylhJPMqm30PEO6KRpESlaklI44nl9ZEMhQq/DdUhNzvl0CMg40XHvFZV3qhJph1bKLe+5QVihGsuaqdcagzmdQseRhsDKzgD+lJnDz/DZEAHzEmRby+3TmfW1GhiSSNJIPhWg4I2nnwdz0Ngn1p8Dp6zjxPCRvL9Ql3g59vvKUFeebeXDLFMRXqe0gZk44NNfnH/BkzhreaIqzkMPaiLcL5JRr9+V8bcIQ9SS4dt89nb9sruXT3Pwd1wzrrPe0AvSHX9fXM8B7bCcewA21qD5RxDmMdF57E+QryBgCyF0/GUQMbn3O2vTf8nwP6A+RFO8jZaOeomqx1k11sIw5m13b/FwUU+sLtGUQvupvp089sNv1UPtW4uJyBi4dMKiiJkJYOFiH9hs48O+zxebrN61eRpJZpTgv3OvxKZzavEliWUmejOFY+Jiz4RqDdcNZTdIdkQwORAhGZFDTphE5ecOj3F6U8He2gVC4Y/sznrZ7G7JSLYxgIPLbhorWqD60EVs1Ior6f/aiLqeSh7Ge7F0GBylvFQ/Rjcfa8qMKINgVgSjdLHQPUbPyY5NZMevl1z6ijElkDR6qQDwSGpe7Lc1v+ZcJCPqYJwvp2HTNRONPBuLF2zZ+5wJf580Xi3VgvaAgaIJ5Zb/9wMPbdyBDiNK833c+i6wAwlWGc49OeAe X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9dc5f702-7a76-4f9c-7e10-08d93bd67bf8 X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2021 14:51:04.0032 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Xn5RK7PGV5CHk+onKIMTlL6uzV8c1YP9xiVmOegLchJwPbD9XcWHz2SDxDAxsInOJp5RAjs8LNjgbFi+EkSWig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5045 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add support for address translation on Data Fabric version 3.5. Add new data fabric ops and interleaving modes. Also, adjust how the DRAM address maps are found early in the translation for certain cases. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi Co-developed-by: Yazen Ghannam Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 213 +++++++++++++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 4 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 8fe0a5e3c8f2..a4197061ac2a 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -996,6 +996,7 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* * Glossary of acronyms used in address translation for Zen-based systems * + * CCM = Cache Coherent Master * COD = Cluster-on-Die * CS = Coherent Slave * DF = Data Fabric @@ -1064,6 +1065,7 @@ static int amd_df_indirect_read(u16 node, struct df_reg reg, u8 instance_id, u32 enum df_reg_names { /* Function 0 */ FAB_BLK_INST_CNT, + FAB_BLK_INST_INFO_0, FAB_BLK_INST_INFO_3, DRAM_HOLE_CTL, DRAM_BASE_ADDR, @@ -1074,11 +1076,16 @@ enum df_reg_names { /* Function 1 */ SYS_FAB_ID_MASK, SYS_FAB_ID_MASK_1, + SYSFABIDMASK0_DF3POINT5, + SYSFABIDMASK1_DF3POINT5, + SYSFABIDMASK2_DF3POINT5, }; static struct df_reg df_regs[] = { /* D18F0x40 (FabricBlockInstanceCount) */ [FAB_BLK_INST_CNT] = {0, 0x40}, + /* D18F0x44 (FabricBlockInstanceInformation0) */ + [FAB_BLK_INST_INFO_0] = {0, 0x44}, /* D18F0x50 (FabricBlockInstanceInformation3_CS) */ [FAB_BLK_INST_INFO_3] = {0, 0x50}, /* D18F0x104 (DramHoleControl) */ @@ -1095,6 +1102,12 @@ static struct df_reg df_regs[] = { [SYS_FAB_ID_MASK] = {1, 0x208}, /* D18F1x20C (SystemFabricIdMask1) */ [SYS_FAB_ID_MASK_1] = {1, 0x20C}, + /* D18F1x150 (SystemFabricIdMask0) */ + [SYSFABIDMASK0_DF3POINT5] = {1, 0x150}, + /* D18F1x154 (SystemFabricIdMask1) */ + [SYSFABIDMASK1_DF3POINT5] = {1, 0x154}, + /* D18F1x158 (SystemFabricIdMask2) */ + [SYSFABIDMASK2_DF3POINT5] = {1, 0x158}, }; /* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ @@ -1103,9 +1116,14 @@ enum intlv_modes { NOHASH_2CH = 0x01, NOHASH_4CH = 0x03, NOHASH_8CH = 0x05, + NOHASH_16CH = 0x07, + NOHASH_32CH = 0x08, HASH_COD4_2CH = 0x0C, HASH_COD2_4CH = 0x0D, HASH_COD1_8CH = 0x0E, + HASH_8CH = 0x1C, + HASH_16CH = 0x1D, + HASH_32CH = 0x1E, DF2_HASH_2CH = 0x21, }; @@ -1118,6 +1136,7 @@ struct addr_ctx { u32 reg_limit_addr; u32 reg_fab_id_mask0; u32 reg_fab_id_mask1; + u32 reg_fab_id_mask2; u16 cs_fabric_id; u16 die_id_mask; u16 socket_id_mask; @@ -1447,6 +1466,128 @@ struct data_fabric_ops df3_ops = { .get_component_id_mask = &get_component_id_mask_df3, }; +static int dehash_addr_df35(struct addr_ctx *ctx) +{ + u8 hashed_bit, intlv_ctl_64k, intlv_ctl_2M, intlv_ctl_1G; + u8 num_intlv_bits = ctx->intlv_num_chan; + u32 tmp, i; + + if (amd_df_indirect_read(0, df_regs[DF_GLOBAL_CTL], DF_BROADCAST, &tmp)) + return -EINVAL; + + intlv_ctl_64k = !!((tmp >> 20) & 0x1); + intlv_ctl_2M = !!((tmp >> 21) & 0x1); + intlv_ctl_1G = !!((tmp >> 22) & 0x1); + + /* + * CSSelect[0] = XOR of addr{8, 16, 21, 30}; + * CSSelect[1] = XOR of addr{9, 17, 22, 31}; + * CSSelect[2] = XOR of addr{10, 18, 23, 32}; + * CSSelect[3] = XOR of addr{11, 19, 24, 33}; - 16 and 32 channel only + * CSSelect[4] = XOR of addr{12, 20, 25, 34}; - 32 channel only + */ + for (i = 0; i < num_intlv_bits; i++) { + hashed_bit = ((ctx->ret_addr >> (8 + i)) ^ + ((ctx->ret_addr >> (16 + i)) & intlv_ctl_64k) ^ + ((ctx->ret_addr >> (21 + i)) & intlv_ctl_2M) ^ + ((ctx->ret_addr >> (30 + i)) & intlv_ctl_1G)); + + hashed_bit &= BIT(0); + if (hashed_bit != ((ctx->ret_addr >> (8 + i)) & BIT(0))) + ctx->ret_addr ^= BIT(8 + i); + } + + return 0; +} + +static int get_intlv_mode_df35(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 2) & 0x1F; + + if (ctx->intlv_mode == HASH_COD4_2CH || + ctx->intlv_mode == HASH_COD2_4CH || + ctx->intlv_mode == HASH_COD1_8CH) { + ctx->make_space_for_cs_id = &make_space_for_cs_id_cod_hash; + ctx->insert_cs_id = &insert_cs_id_cod_hash; + ctx->dehash_addr = &dehash_addr_df3; + } else { + ctx->make_space_for_cs_id = &make_space_for_cs_id_simple; + ctx->insert_cs_id = &insert_cs_id_simple; + + if (ctx->intlv_mode == HASH_8CH || + ctx->intlv_mode == HASH_16CH || + ctx->intlv_mode == HASH_32CH) + ctx->dehash_addr = &dehash_addr_df35; + } + + return 0; +} + +static void get_intlv_num_dies_df35(struct addr_ctx *ctx) +{ + ctx->intlv_num_dies = (ctx->reg_base_addr >> 7) & 0x1; +} + +static u8 get_die_id_shift_df35(struct addr_ctx *ctx) +{ + return ctx->node_id_shift; +} + +static u8 get_socket_id_shift_df35(struct addr_ctx *ctx) +{ + return (ctx->reg_fab_id_mask1 >> 8) & 0xF; +} + +static int get_masks_df35(struct addr_ctx *ctx) +{ + if (amd_df_indirect_read(0, df_regs[SYSFABIDMASK1_DF3POINT5], + DF_BROADCAST, &ctx->reg_fab_id_mask1)) + return -EINVAL; + + if (amd_df_indirect_read(0, df_regs[SYSFABIDMASK2_DF3POINT5], + DF_BROADCAST, &ctx->reg_fab_id_mask2)) + return -EINVAL; + + ctx->node_id_shift = ctx->reg_fab_id_mask1 & 0xF; + + ctx->die_id_mask = ctx->reg_fab_id_mask2 & 0xFFFF; + + ctx->socket_id_mask = (ctx->reg_fab_id_mask2 >> 16) & 0xFFFF; + + return 0; +} + +static u16 get_dst_fabric_id_df35(struct addr_ctx *ctx) +{ + return ctx->reg_limit_addr & 0xFFF; +} + +static int get_cs_fabric_id_df35(struct addr_ctx *ctx) +{ + ctx->cs_fabric_id = ctx->inst_id | (ctx->nid << ctx->node_id_shift); + + return 0; +} + +static u16 get_component_id_mask_df35(struct addr_ctx *ctx) +{ + return ctx->reg_fab_id_mask0 & 0xFFFF; +} + +struct data_fabric_ops df3point5_ops = { + .get_hi_addr_offset = &get_hi_addr_offset_df3, + .get_intlv_mode = &get_intlv_mode_df35, + .get_intlv_addr_sel = &get_intlv_addr_sel_df3, + .get_intlv_num_dies = &get_intlv_num_dies_df35, + .get_intlv_num_sockets = &get_intlv_num_sockets_df3, + .get_masks = &get_masks_df35, + .get_die_id_shift = &get_die_id_shift_df35, + .get_socket_id_shift = &get_socket_id_shift_df35, + .get_dst_fabric_id = &get_dst_fabric_id_df35, + .get_cs_fabric_id = &get_cs_fabric_id_df35, + .get_component_id_mask = &get_component_id_mask_df35, +}; + struct data_fabric_ops *df_ops; static int set_df_ops(struct addr_ctx *ctx) @@ -1458,6 +1599,16 @@ static int set_df_ops(struct addr_ctx *ctx) ctx->num_blk_instances = tmp & 0xFF; + if (amd_df_indirect_read(0, df_regs[SYSFABIDMASK0_DF3POINT5], + DF_BROADCAST, &ctx->reg_fab_id_mask0)) + return -EINVAL; + + if ((ctx->reg_fab_id_mask0 & 0xFF) != 0) { + ctx->late_hole_remove = true; + df_ops = &df3point5_ops; + return 0; + } + if (amd_df_indirect_read(0, df_regs[SYS_FAB_ID_MASK], DF_BROADCAST, &ctx->reg_fab_id_mask0)) return -EINVAL; @@ -1558,8 +1709,17 @@ static void get_intlv_num_chan(struct addr_ctx *ctx) break; case NOHASH_8CH: case HASH_COD1_8CH: + case HASH_8CH: ctx->intlv_num_chan = 3; break; + case NOHASH_16CH: + case HASH_16CH: + ctx->intlv_num_chan = 4; + break; + case NOHASH_32CH: + case HASH_32CH: + ctx->intlv_num_chan = 5; + break; default: /* Valid interleaving modes where checked earlier. */ break; @@ -1665,6 +1825,43 @@ static int addr_over_limit(struct addr_ctx *ctx) return 0; } +static int find_ccm_instance_id(struct addr_ctx *ctx) +{ + u32 temp; + + for (ctx->inst_id = 0; ctx->inst_id < ctx->num_blk_instances; ctx->inst_id++) { + if (amd_df_indirect_read(0, df_regs[FAB_BLK_INST_INFO_0], ctx->inst_id, &temp)) + return -EINVAL; + + if (temp == 0) + continue; + + if ((temp & 0xF) == 0) + return 0; + } + + return -EINVAL; +} + +#define DF_NUM_DRAM_MAPS_AVAILABLE 16 +static int find_map_reg_by_dstfabricid(struct addr_ctx *ctx) +{ + u16 node_id_mask = (ctx->reg_fab_id_mask0 >> 16) & 0xFFFF; + u16 dst_fabric_id; + + for (ctx->map_num = 0; ctx->map_num < DF_NUM_DRAM_MAPS_AVAILABLE ; ctx->map_num++) { + if (get_dram_addr_map(ctx)) + continue; + + dst_fabric_id = df_ops->get_dst_fabric_id(ctx); + + if ((dst_fabric_id & node_id_mask) == (ctx->cs_fabric_id & node_id_mask)) + return 0; + } + + return -EINVAL; +} + static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 umc) { struct addr_ctx ctx; @@ -1686,11 +1883,19 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 umc) if (df_ops->get_cs_fabric_id(&ctx)) return -EINVAL; - if (remove_dram_offset(&ctx)) - return -EINVAL; + if (ctx.nid >= NONCPU_NODE_INDEX) { + if (find_ccm_instance_id(&ctx)) + return -EINVAL; - if (get_dram_addr_map(&ctx)) - return -EINVAL; + if (find_map_reg_by_dstfabricid(&ctx)) + return -EINVAL; + } else { + if (remove_dram_offset(&ctx)) + return -EINVAL; + + if (get_dram_addr_map(&ctx)) + return -EINVAL; + } if (df_ops->get_intlv_mode(&ctx)) return -EINVAL; From patchwork Wed Jun 30 15:28:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12352295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8AAEC11F69 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1I30+ExEZ8e12IFkwkjJVAaEhajhRa0BBxyAnMtKvtNF7NHuRA9FaPrss0bRuI1FhGoD0c2QOL5m/Yq767HdFC80HxwrRp7NbWBzg0KDPOCQZTJ+MFoMk9ODkgleDAk3XR7WomOt6d5Vd7Fdaf6/xuKz1zzM0sZf4XAmv7VCl9RYeL9FhEGvK+TD57Ec87TA53+WtSc/eN3yeaKoiSkFUqPJzi0dD1fnCyrNvpFXKbiM+NXr01VLry+n6MRmRDZqtdmS2+LdutKk3yLtUeeVKcpAhHx6Z7rUg48h0gObhFp7xjZAxalqmQjiMp/xr1Dm7UTyaqoUKH5/iGPTL/y7qBAlxs77epywLXbF0teACkdmK5E6Gb6rtzQlwx3MB0u2dpppoGKdOLpJhonqSCaguJXsYc2Gw3CijFJuWtKna3XI6e8W8JRkcwVy8dQGZS6+iGXEGf6uwh3bKvpqsvDzWgxk5fPOY9bG7InRdlT4tzvoVjTifU9GyVRMAkzJ8zQqYe/bAvI6QpUz15ZXxyP8l3O0sIOOaESP2pb2VxTYUr64fHaAVCW93swworgwU5lXZtl6skJiQtTmPyfu2MuFrTXBusmQTumGOVJvKrRE1iKhFUcttwXMrE3rjTyvJCGOcYerwUgHKyPl+45LMRZHlehyqi1cS1+whiL2YFFILSzxHI8Msex4cBYAds3ZzlS93gs19VW8y5Nw2mE69PlevuvsB5R3IKalUn9Il7X0LaKWYBnCVcauYCv3J5k7S2rtRV0dWZvF1Tu+ChfYd4QcAgy7vN28tsz6PEatOWaF8QVTg+Va3QwrBkm0QuK9pvyAALilwGRaAEYfNeGgXKbU2XEQKVIyQyrniKDXYjv7tJqIF6UK5EhEpsj/MsA6ZiqMLnwtZjkQK9qD/PAU9rm8EZmd+7H1Ao6vV6s+MxbcyWbbrEFCeS3jwt0rE7RN7Qce1Ao6IY5UAVlEQdiJYgbkRLNkGsb2Js4dek9jMHkmTLNbptgJeLbr22lbcCsxaOO7noCt+pN6KBkvjncGvIlES74jYNto/NutZn+RKa81RSmkHcPO2zka/c3VJcwUImJLf2enDGtg6bBOWXVPduNPlB2blC6EuLZwkZx9uFsZLcwGGjndhYsRitz/XsxZY8aDcia4XDS9Uhqx36ZXte/hIWz389Lj/RG5bTibZdUalSsArqQ/mBOuiDf72/Rfp65TSROgwMzHgzyuIuek8bcVczcVk9pbmZojzpV8ytdmYzNRtd5ZDokNxR6YUMTINCse5sAVp9HvnnGncxHx7htuyfrcCwitqK0Fc841+wA2N1y/47C/k61hJU4nLr62+vdt X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc05cf72-8c32-44d8-e615-08d93bd67db7 X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5286.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2021 14:51:06.9652 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +A5uYGLyzTLZT7rKOpzH8CvTrQpn3fHhl1W2gbJsvJWxSNSxsOoBtFvAFsacBuijusWT1LqiMXHgS9VOFsVMPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5125 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Yazen Ghannam This patch handles the UMC to CS mapping for Aldebaran Aldebaran has 2 dies and are enumerated alternatively * die0's are enumerated as node 8, 10, 12 and 14 * die1's are enumerated as node 9, 11, 13 and 15 Signed-off-by: Yazen Ghannam Signed-off-by: Naveen Krishna Chatradhi --- drivers/edac/amd64_edac.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a4197061ac2a..3416699fa7f6 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1562,8 +1562,41 @@ static u16 get_dst_fabric_id_df35(struct addr_ctx *ctx) return ctx->reg_limit_addr & 0xFFF; } +/* UMC to CS mapping for Aldebaran die[0]s */ +u8 umc_to_cs_mapping_aldebaran_die0[] = { 28, 20, 24, 16, 12, 4, 8, 0, + 6, 30, 2, 26, 22, 14, 18, 10, + 19, 11, 15, 7, 3, 27, 31, 23, + 9, 1, 5, 29, 25, 17, 21, 13}; + +/* UMC to CS mapping for Aldebaran die[1]s */ +u8 umc_to_cs_mapping_aldebaran_die1[] = { 19, 11, 15, 7, 3, 27, 31, 23, + 9, 1, 5, 29, 25, 17, 21, 13, + 28, 20, 24, 16, 12, 4, 8, 0, + 6, 30, 2, 26, 22, 14, 18, 10}; + +int get_umc_to_cs_mapping(struct addr_ctx *ctx) +{ + if (ctx->inst_id >= sizeof(umc_to_cs_mapping_aldebaran_die0)) + return -EINVAL; + + /* + * Aldebaran has 2 dies and are enumerated alternatively + * die0's are enumerated as node 8, 10, 12 and 14 + * die1's are enumerated as node 9, 11, 13 and 15 + */ + if (ctx->nid % 2) + ctx->inst_id = umc_to_cs_mapping_aldebaran_die1[ctx->inst_id]; + else + ctx->inst_id = umc_to_cs_mapping_aldebaran_die0[ctx->inst_id]; + + return 0; +} + static int get_cs_fabric_id_df35(struct addr_ctx *ctx) { + if (ctx->nid >= NONCPU_NODE_INDEX && get_umc_to_cs_mapping(ctx)) + return -EINVAL; + ctx->cs_fabric_id = ctx->inst_id | (ctx->nid << ctx->node_id_shift); return 0;