From patchwork Mon Jul 5 14:21:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359181 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12DD6C07E99 for ; Mon, 5 Jul 2021 14:22:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC0A761946 for ; Mon, 5 Jul 2021 14:22:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231423AbhGEOYm (ORCPT ); Mon, 5 Jul 2021 10:24:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbhGEOYl (ORCPT ); Mon, 5 Jul 2021 10:24:41 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E808EC061574; Mon, 5 Jul 2021 07:22:04 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id v7so18462211pgl.2; Mon, 05 Jul 2021 07:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ezyl9znPDS4XJngAoOB66He3Jj88vDsFLgZj2nxw3FI=; b=ULQRGFs8Y4Rr98VDotpfAshNcOqA5IfduWnz9Y+6PP1Wbi5/8uPuFRiWFDc+rqLfZZ kEJxoKGePTf0RY1/AAWXy/bRt/2I0XXJ+tRCqwS9NQrqid0XZ3evdSzSPi97cv4qDa5x j/qnksP1Ok/lTeB5H2kUnoR9tsHf2RUv0tv9xMhUfnQ97VgdeDefbctPE8yMrOCgr4Wx Tju1aMe7HMhTluxqI3kB11qOEE44b77vWuEB75Pz5rWwGq+iNXEqgp/RYR6whE+PLnau +3ktCDRzTT7y8/V+YATaXr+uzQfstqKWQ9gQFAcNUHbNG9pClciOCsQvvqSUZANVsxH9 trpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ezyl9znPDS4XJngAoOB66He3Jj88vDsFLgZj2nxw3FI=; b=WRD2/lpOkozoqBeyOHjCmGIFQg1tT95NJva0bmKvkzGRFmlgNwdx3naKZcxsnaBIL2 df8D1/qQoIM8VNE18Rsm2F8IiLkvVfWiB5he2SIeurpvIw1Ri/H7wxna3QCEFUV6LonJ FU3DOZ92Zalzzo+g8t7jw6FVnolUVW6PsYm1saS9/GnKvGG3ag7z5y6va8TkURXzzYxD gc3Jbx8ysNWBdPeqREC8nAVYA1k8udbOE/VzHwrG6Xj7wlo8rSgRmoOq0Nru2p+68dOb id0elPvJrmMtmSFdI1i2foV/HmV5wucilnxLYPQOBEQPB4r4oLT7qDKELiw4r/gTvmfM i4cQ== X-Gm-Message-State: AOAM533a+stWRayCcBPFhdwGiIFoydhhgHTh1miQkZJ+9xVV1jNE1EAo 6ruO3vk9rK9E5ODq1Dv15Ho= X-Google-Smtp-Source: ABdhPJyvNyVDg6lJAgDG0H7wH1dxaYiKhWr3cuzSbo+r+sI2/8oIg0mbONiyCTsiVcQT53af1Zighw== X-Received: by 2002:aa7:9905:0:b029:301:ec7c:f73c with SMTP id z5-20020aa799050000b0290301ec7cf73cmr15294846pff.68.1625494924319; Mon, 05 Jul 2021 07:22:04 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:04 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" , Amey Narkhede Subject: [PATCH v9 1/8] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Date: Mon, 5 Jul 2021 19:51:31 +0530 Message-Id: <20210705142138.2651-2-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add has_pcie_flr bitfield in struct pci_dev to indicate support for PCIe FLR to avoid reading PCI_EXP_DEVCAP multiple times. Currently there is separate function pcie_has_flr() to probe if PCIe FLR is supported by the device which does not match the calling convention followed by reset methods which use second function argument to decide whether to probe or not. Add new function pcie_reset_flr() that follows the calling convention of reset methods. Signed-off-by: Amey Narkhede Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz --- drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +- drivers/pci/pci.c | 59 +++++++++++----------- drivers/pci/pcie/aer.c | 12 ++--- drivers/pci/probe.c | 6 ++- drivers/pci/quirks.c | 9 ++-- include/linux/pci.h | 3 +- 6 files changed, 45 insertions(+), 48 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index facc8e6bc..15d6c8452 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - /* check flr support */ - if (pcie_has_flr(pdev)) - pcie_flr(pdev); + pcie_reset_flr(pdev, 0); pci_restore_state(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 452351025..fefa6d7b3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4611,32 +4611,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -/** - * pcie_has_flr - check if a device supports function level resets - * @dev: device to check - * - * Returns true if the device advertises support for PCIe function level - * resets. - */ -bool pcie_has_flr(struct pci_dev *dev) -{ - u32 cap; - - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) - return false; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; -} -EXPORT_SYMBOL_GPL(pcie_has_flr); - /** * pcie_flr - initiate a PCIe function level reset * @dev: device to reset * - * Initiate a function level reset on @dev. The caller should ensure the - * device supports FLR before calling this function, e.g. by using the - * pcie_has_flr() helper. + * Initiate a function level reset unconditionally on @dev without + * checking any flags and DEVCAP */ int pcie_flr(struct pci_dev *dev) { @@ -4659,6 +4639,28 @@ int pcie_flr(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pcie_flr); +/** + * pcie_reset_flr - initiate a PCIe function level reset + * @dev: device to reset + * @probe: If set, only check if the device can be reset this way. + * + * Initiate a function level reset on @dev. + */ +int pcie_reset_flr(struct pci_dev *dev, int probe) +{ + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) + return -ENOTTY; + + if (!dev->has_pcie_flr) + return -ENOTTY; + + if (probe) + return 0; + + return pcie_flr(dev); +} +EXPORT_SYMBOL_GPL(pcie_reset_flr); + static int pci_af_flr(struct pci_dev *dev, int probe) { int pos; @@ -5139,11 +5141,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 0); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - if (rc != -ENOTTY) - return rc; - } + rc = pcie_reset_flr(dev, 0); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) return rc; @@ -5174,8 +5174,9 @@ int pci_probe_reset_function(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 1); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) - return 0; + rc = pcie_reset_flr(dev, 1); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 1); if (rc != -ENOTTY) return rc; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ec943cee5..98077595a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,13 +1405,11 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - pci_info(dev, "has been reset (%d)\n", rc); - } else { - pci_info(dev, "not reset (no FLR support)\n"); - rc = -ENOTTY; - } + rc = pcie_reset_flr(dev, 0); + if (!rc) + pci_info(dev, "has been reset\n"); + else + pci_info(dev, "not reset (no FLR support: %d)\n", rc); } else { rc = pci_bus_error_reset(dev); pci_info(dev, "%s Port link has been reset (%d)\n", diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3a62d09b8..a95252113 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1487,6 +1487,7 @@ void set_pcie_port_type(struct pci_dev *pdev) { int pos; u16 reg16; + u32 reg32; int type; struct pci_dev *parent; @@ -1497,8 +1498,9 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->pcie_cap = pos; pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); pdev->pcie_flags_reg = reg16; - pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); - pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; + pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, ®32); + pdev->pcie_mpss = reg32 & PCI_EXP_DEVCAP_PAYLOAD; + pdev->has_pcie_flr = reg32 & PCI_EXP_DEVCAP_FLR ? 1 : 0; parent = pci_upstream_bridge(pdev); if (!parent) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d85914afe..f977ba79a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3819,7 +3819,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) return -ENOTTY; if (probe) @@ -3888,13 +3888,10 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) */ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) { - if (!pcie_has_flr(dev)) - return -ENOTTY; + int ret = pcie_reset_flr(dev, probe); if (probe) - return 0; - - pcie_flr(dev); + return ret; msleep(250); diff --git a/include/linux/pci.h b/include/linux/pci.h index c20211e59..d432428fd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -337,6 +337,7 @@ struct pci_dev { u8 msi_cap; /* MSI capability offset */ u8 msix_cap; /* MSI-X capability offset */ u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ + u8 has_pcie_flr:1; /* PCIe FLR supported */ u8 rom_base_reg; /* Config register controlling ROM */ u8 pin; /* Interrupt pin this device uses */ u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ @@ -1225,7 +1226,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -bool pcie_has_flr(struct pci_dev *dev); +int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Mon Jul 5 14:21:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359183 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2ACC07E99 for ; Mon, 5 Jul 2021 14:22:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 31EEB6193E for ; Mon, 5 Jul 2021 14:22:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230285AbhGEOYr (ORCPT ); Mon, 5 Jul 2021 10:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbhGEOYq (ORCPT ); Mon, 5 Jul 2021 10:24:46 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C73C061574; Mon, 5 Jul 2021 07:22:10 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id 22-20020a17090a0c16b0290164a5354ad0so14928446pjs.2; Mon, 05 Jul 2021 07:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DJ2O1nNK01wBf0p/nBO9VwAZPFLJ7/FBVU/jbxpeRWo=; b=OQCR1kNGUECykJo+Wqve+WnpwlSKagZ2Nw+7pagLfhs8zjBqKWGZuiSPi8qcPw+sUK uY3SLxZb+IiqioN2y+KNaMPzIcEUMvAC4f7UcOk2IqLj/+Fp5pKCmbDB+0WSPoJfK8pC K8rHyklHUupBVqZRf1giXbvWBQ1ZbryTOsWpwRi7oiIF5rWRHMmmtw7T+dgcu6BDF3R6 WXkpQGIJbytanNpZJjXWUgW7nZNYUPOzZAWj9mBvFClD8Gi+hYoG7klg9TZBBsf6yJsE QiyAJTlVvL2XgTYHbmtZ/+nkbv9JgzOXwBeL/iTa7jdZrqIlRbIMeE7029g/CChruHW7 EBig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DJ2O1nNK01wBf0p/nBO9VwAZPFLJ7/FBVU/jbxpeRWo=; b=JfDUYDA4whDmQkNnfWH2a81cGd/phNyh8QGmOI3O4Ts4Y2SXpHfe8R5MBSTxA45uQa SIPgtRv51b4MmDPYt0SgpAMPAt97tarMdK9FE6H7LkduV9TyP7pqgGiA4/+Til87jOLS wsmX0MWm53slj4whn47qCNHlM/7vSjVBBK1Igp0ji0Qa8jX8xfFcW1jNYrj+8ZxZDAtn UeDD0OyVsX1ffU/w/qEYbnbter9yDNO7THubtr3IQveeFDlCyY3g7T25f6N3yzLZuXKC WnroY6hIWmg7JRGZkfmhPvJJTpQ6DHCa7dXnxUHjGMnYTkvdm7Ultq4lMW4nk6eM0pGp ciVg== X-Gm-Message-State: AOAM532J8/N+A2rzlOTEib867KNiRBp+mDMvgZJ/4iFCY3rl0BUKClPH AlebNhf8l2IKebR9ciswphM= X-Google-Smtp-Source: ABdhPJynxhUsFfkq+J5SV9BLg8iG7oPeXQs6oHkC7xS13CN2lMLe4Uo+hYniIXUHEN86yNn7PjrwSw== X-Received: by 2002:a17:902:7c94:b029:fc:5e8b:e645 with SMTP id y20-20020a1709027c94b02900fc5e8be645mr12678061pll.18.1625494929692; Mon, 05 Jul 2021 07:22:09 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:09 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" , Amey Narkhede Subject: [PATCH v9 2/8] PCI: Add new array for keeping track of ordering of reset methods Date: Mon, 5 Jul 2021 19:51:32 +0530 Message-Id: <20210705142138.2651-3-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new array reset_methods in struct pci_dev to keep track of reset mechanisms supported by the device and their ordering. Also refactor probing and reset functions to take advantage of calling convention of reset functions. Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Reviewed-by: Raphael Norwitz --- drivers/pci/pci.c | 92 ++++++++++++++++++++++++++------------------- drivers/pci/pci.h | 9 ++++- drivers/pci/probe.c | 5 +-- include/linux/pci.h | 7 ++++ 4 files changed, 70 insertions(+), 43 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fefa6d7b3..42440cb10 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -72,6 +72,14 @@ static void pci_dev_d3_sleep(struct pci_dev *dev) msleep(delay); } +int pci_reset_supported(struct pci_dev *dev) +{ + u8 null_reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + return memcmp(null_reset_methods, + dev->reset_methods, sizeof(null_reset_methods)); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -5104,6 +5112,15 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +const struct pci_reset_fn_method pci_reset_fn_methods[] = { + { }, + { &pci_dev_specific_reset, .name = "device_specific" }, + { &pcie_reset_flr, .name = "flr" }, + { &pci_af_flr, .name = "af_flr" }, + { &pci_pm_reset, .name = "pm" }, + { &pci_reset_bus_function, .name = "bus" }, +}; + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5126,65 +5143,62 @@ static void pci_dev_restore(struct pci_dev *dev) */ int __pci_reset_function_locked(struct pci_dev *dev) { - int rc; + int i, m, rc = -ENOTTY; might_sleep(); /* - * A reset method returns -ENOTTY if it doesn't support this device - * and we should try the next method. + * A reset method returns -ENOTTY if it doesn't support this device and + * we should try the next method. * - * If it returns 0 (success), we're finished. If it returns any - * other error, we're also finished: this indicates that further - * reset mechanisms might be broken on the device. + * If it returns 0 (success), we're finished. If it returns any other + * error, we're also finished: this indicates that further reset + * mechanisms might be broken on the device. */ - rc = pci_dev_specific_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_reset_bus_function(dev, 0); + for (i = 0; i < PCI_NUM_RESET_METHODS && (m = dev->reset_methods[i]); i++) { + rc = pci_reset_fn_methods[m].reset_fn(dev, 0); + if (!rc) + return 0; + if (rc != -ENOTTY) + return rc; + } + + return -ENOTTY; } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); /** - * pci_probe_reset_function - check whether the device can be safely reset - * @dev: PCI device to reset + * pci_init_reset_methods - check whether device can be safely reset + * and store supported reset mechanisms. + * @dev: PCI device to check for reset mechanisms * * Some devices allow an individual function to be reset without affecting * other functions in the same device. The PCI device must be responsive - * to PCI config space in order to use this function. + * to reads and writes to its PCI config space in order to use this function. * - * Returns 0 if the device function can be reset or negative if the - * device doesn't support resetting a single function. + * Stores reset mechanisms supported by device in reset_methods byte array + * which is a member of struct pci_dev. */ -int pci_probe_reset_function(struct pci_dev *dev) +void pci_init_reset_methods(struct pci_dev *dev) { - int rc; + int i, n, rc; + u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + n = 0; + + BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS); might_sleep(); - rc = pci_dev_specific_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; + for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { + rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + if (!rc) + reset_methods[n++] = i; + else if (rc != -ENOTTY) + break; + } - return pci_reset_bus_function(dev, 1); + memcpy(dev->reset_methods, reset_methods, sizeof(reset_methods)); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 37c913bbc..db1ad94e7 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -33,7 +33,8 @@ enum pci_mmap_api { int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, enum pci_mmap_api mmap_api); -int pci_probe_reset_function(struct pci_dev *dev); +int pci_reset_supported(struct pci_dev *dev); +void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); @@ -606,6 +607,12 @@ struct pci_dev_reset_methods { int (*reset)(struct pci_dev *dev, int probe); }; +struct pci_reset_fn_method { + int (*reset_fn)(struct pci_dev *pdev, int probe); + char *name; +}; + +extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_reset(struct pci_dev *dev, int probe); #else diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a95252113..a3e9a9c88 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2406,9 +2406,8 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - - if (pci_probe_reset_function(dev) == 0) - dev->reset_fn = 1; + pci_init_reset_methods(dev); + dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/include/linux/pci.h b/include/linux/pci.h index d432428fd..9f3e85f33 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,6 +49,9 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) +/* Number of reset methods used in pci_reset_fn_methods array in pci.c */ +#define PCI_NUM_RESET_METHODS 6 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -506,6 +509,10 @@ struct pci_dev { char *driver_override; /* Driver name to force a match */ unsigned long priv_flags; /* Private flags for the PCI driver */ + /* + * See pci_reset_fn_methods array in pci.c for ordering. + */ + u8 reset_methods[PCI_NUM_RESET_METHODS]; /* Reset methods ordered by priority */ }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) From patchwork Mon Jul 5 14:21:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359185 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2CA2C07E99 for ; Mon, 5 Jul 2021 14:22:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 987AC6193E for ; Mon, 5 Jul 2021 14:22:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231482AbhGEOYx (ORCPT ); Mon, 5 Jul 2021 10:24:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231469AbhGEOYx (ORCPT ); Mon, 5 Jul 2021 10:24:53 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B98AC06175F; Mon, 5 Jul 2021 07:22:16 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id w22so13146504pff.5; Mon, 05 Jul 2021 07:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jVlCn7WpT/lKwA3UFgNvaBNdCn+26OPx3iaY8fO93pM=; b=f6m7n8ZWQDIM15JSs6jrsLkRYZigFMDScieh+gKi+lyqA2DFwTgjdCQExlnUaGRptl irAc3qGk4PNLYOSS1Tfwy0FNrV89QC6JM8JF+g7WAGYF0m+FLC92faNs9RAnsHdMFOB/ /U1OLeqhL1Nfo+aITH45LiZHaJXbbRa9yOkSKeSGdtl4NZV9KNvkhJ5AlaVye1gBg9iN cj3PpoZnE4tWd6HrlATZEyrZxwRnOscG7qjeNVXjSCsK5WW/eeAwBTbJHLTm9Aze/Apo 29HIhmbklxtnJsqn+g2PC4vtm6QwJ27z8ndfLpfaNTdkKxtP990LpWRVEemxGIzeFC9v 6DnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jVlCn7WpT/lKwA3UFgNvaBNdCn+26OPx3iaY8fO93pM=; b=A3OZjfv5VKrNnBqcEHlYGQ//QR5loH81pYcCYF6smGm7R7HZFJTMT2FkGEbgO7trrD fLWHCYkZ87htoSde0lc2oQd8d/9HdXnNda3PQ7fHmhfXHAH4FSWHWYiv76wUM6c0k0fk 9eZcrtwwWBom63UTJRJBZ6qVZ/eG9WsadtlUuu3kOMc44hAMHd/saLVb2ZufmxXTS/Nw FYUG0qcePeuXok5bDgFL9C7zMuntnJ3TaftOt+jvb/rpBjZ2/4vCBnNFJrWS2Azbf2pw sJiWR8HevsM3RUG25kRWJcVBXzN+cghfU6fscFzX/Nr1Wjb8V9nix6cRafFykdvrBS2U elXw== X-Gm-Message-State: AOAM533jApfsKKRStyzYbyO2jnis50P8JUlXI6tGYfQFzh7z70NV47M0 5ezBbJjX8VpspYF5k2Wesgo= X-Google-Smtp-Source: ABdhPJywgplEqZzf2gOzi0PpDqJR3Iq9TQwPGkKok+IflsYA92YxC8hScxOCtrH2t2I/LhblwlXGCw== X-Received: by 2002:a63:5442:: with SMTP id e2mr15994546pgm.365.1625494935940; Mon, 05 Jul 2021 07:22:15 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:15 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" , Amey Narkhede Subject: [PATCH v9 3/8] PCI: Remove reset_fn field from pci_dev Date: Mon, 5 Jul 2021 19:51:33 +0530 Message-Id: <20210705142138.2651-4-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org reset_fn field is used to indicate whether the device supports any reset mechanism or not. Remove the use of reset_fn in favor of new reset_methods array which can be used to keep track of all supported reset mechanisms of a device and their ordering. The octeon driver is incorrectly using reset_fn field to detect if the device supports FLR or not. Use pcie_reset_flr() to probe whether it supports FLR or not. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/net/ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 6 +++--- drivers/pci/probe.c | 1 - drivers/pci/quirks.c | 2 +- drivers/pci/remove.c | 1 - include/linux/pci.h | 1 - 7 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 516f166ce..336d149ee 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (oct->pci_dev->reset_fn) + if (!pcie_reset_flr(oct->pci_dev, 1)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index beb8d1f4f..316f70c3e 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1367,7 +1367,7 @@ static umode_t pci_dev_reset_attr_is_visible(struct kobject *kobj, { struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); - if (!pdev->reset_fn) + if (!pci_reset_supported(pdev)) return 0; return a->mode; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 42440cb10..d5c16492c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5221,7 +5221,7 @@ int pci_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_lock(dev); @@ -5257,7 +5257,7 @@ int pci_reset_function_locked(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_save_and_disable(dev); @@ -5280,7 +5280,7 @@ int pci_try_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; if (!pci_dev_trylock(dev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a3e9a9c88..221a20415 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2407,7 +2407,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pcie_report_downtraining(dev); pci_init_reset_methods(dev); - dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f977ba79a..e86cf4a3b 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5589,7 +5589,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || pdev->subsystem_device != 0x222e || - !pdev->reset_fn) + !pci_reset_supported(pdev)) return; if (pci_enable_device_mem(pdev)) diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index dd12c2fcc..4c54c7505 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -19,7 +19,6 @@ static void pci_stop_dev(struct pci_dev *dev) pci_pme_active(dev, false); if (pci_dev_is_added(dev)) { - dev->reset_fn = 0; device_release_driver(&dev->dev); pci_proc_detach_device(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 9f3e85f33..f34563831 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -431,7 +431,6 @@ struct pci_dev { unsigned int state_saved:1; unsigned int is_physfn:1; unsigned int is_virtfn:1; - unsigned int reset_fn:1; unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ From patchwork Mon Jul 5 14:21:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359187 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B98D8C07E99 for ; Mon, 5 Jul 2021 14:22:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A572F6193E for ; Mon, 5 Jul 2021 14:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231477AbhGEOY7 (ORCPT ); Mon, 5 Jul 2021 10:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231469AbhGEOY7 (ORCPT ); Mon, 5 Jul 2021 10:24:59 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FDDAC061574; Mon, 5 Jul 2021 07:22:21 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id p17-20020a17090b0111b02901723ab8d11fso60525pjz.1; Mon, 05 Jul 2021 07:22:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+SeOboOLlz+xap97sxOppn3yBL6kAtfgBYzXOsGvd0s=; b=PCN5YPo/uXxlpYhV7km3hBSh9UI9Xkyfi83u6e/mrhpT1TvHeBdO1RVous15RJPeJP 8p4L/KW4D1z+IK6LP9DzxIYiEY/pc2YmlzU8OmIGsVp4YXgqe1ODvqk6O/YadOpe2vzo cjfIGHqTl38kqD3C3X22qMn4oZMrzg91PGxm4z5l8Jt/pel7C21Ekqqd75/CFpMX66ft Wdg/jIPee5VWnPsYd8djNOOOPbXSCzwRvx+b3egQDyX1hGXB/KeF/y5YlxaP0pEmow1S qgtloQEiBLjd4Hb3vPe2qLSUIGw3b0aCIL6SDgkrHT2IOzXIpk5AKWhHB4ezjpNHGikZ rdsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+SeOboOLlz+xap97sxOppn3yBL6kAtfgBYzXOsGvd0s=; b=qQb0kRuxlYSxOK1RHc/B1jhMk/41iiwB+dhXlw18mkR9B0jc+Hwl+oVdu5hxpo2nqP Gszk2KCb13CkpCok0V4U105UF5O1qupu+n56NXwDavujWlDkK89CIqfWZitDglKuO5Xu YLZf8PYh140227X1H6XczjmerAVVp6wku6+6vb4CHdXJ7KlklZ3ABc9h4KU3KjX82hpd uBovi42JKEfld9JRC+5/+VznpTktVIc4o2yHsnFqo+m3brhZ8VcoDeDN+iBuSohHXoEO RkevNES3WNtauiMqkK7aLYbaFbwM0sKl2brdeXPmUJH2sZTf+dbPPZqYmZP6Me5oJ1G8 hKAg== X-Gm-Message-State: AOAM530dYMCBzQQEEycPdtJhL6v18ml15/Ey83SPxvvLvKsv9kosmC0l a6urNDrw6RHJmhEn4r9Eq2Q= X-Google-Smtp-Source: ABdhPJyO5rFOq79dUCaOQUbUkXMSluWeDN2PSi5E1T3s5DgUta11uYPO3VXomZra9fxBf2jM9cvNzQ== X-Received: by 2002:a17:902:9308:b029:129:7c79:e53d with SMTP id bc8-20020a1709029308b02901297c79e53dmr7591726plb.50.1625494941205; Mon, 05 Jul 2021 07:22:21 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:20 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" , Amey Narkhede Subject: [PATCH v9 4/8] PCI/sysfs: Allow userspace to query and set device reset mechanism Date: Mon, 5 Jul 2021 19:51:34 +0530 Message-Id: <20210705142138.2651-5-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add reset_method sysfs attribute to enable user to query and set user preferred device reset methods and their ordering. Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Reviewed-by: Leon Romanovsky Reviewed-by: Raphael Norwitz --- Documentation/ABI/testing/sysfs-bus-pci | 19 +++++ drivers/pci/pci-sysfs.c | 103 ++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index ef00fada2..43f4e33c7 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -121,6 +121,25 @@ Description: child buses, and re-discover devices removed earlier from this part of the device tree. +What: /sys/bus/pci/devices/.../reset_method +Date: March 2021 +Contact: Amey Narkhede +Description: + Some devices allow an individual function to be reset + without affecting other functions in the same slot. + + For devices that have this support, a file named + reset_method will be present in sysfs. Initially reading + this file will give names of the device supported reset + methods and their ordering. After write, this file will + give names and ordering of currently enabled reset methods. + Writing the name or comma separated list of names of any of + the device supported reset methods to this file will set + the reset methods and their ordering to be used when + resetting the device. Writing empty string to this file + will disable ability to reset the device and writing + "default" will return to the original value. + What: /sys/bus/pci/devices/.../reset Date: July 2009 Contact: Michael S. Tsirkin diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 316f70c3e..8a740e211 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1334,6 +1334,108 @@ static const struct attribute_group pci_dev_rom_attr_group = { .is_bin_visible = pci_dev_rom_attr_is_visible, }; +static ssize_t reset_method_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + ssize_t len = 0; + int i, idx; + + for (i = 0; i < PCI_NUM_RESET_METHODS; i++) { + idx = pdev->reset_methods[i]; + if (!idx) + break; + + len += sysfs_emit_at(buf, len, "%s%s", len ? "," : "", + pci_reset_fn_methods[idx].name); + } + + if (len) + len += sysfs_emit_at(buf, len, "\n"); + + return len; +} + +static ssize_t reset_method_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pdev = to_pci_dev(dev); + int n = 0; + char *name, *options = NULL; + u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + if (count >= (PAGE_SIZE - 1)) + return -EINVAL; + + if (sysfs_streq(buf, "")) { + pci_warn(pdev, "All device reset methods disabled by user"); + goto set_reset_methods; + } + + if (sysfs_streq(buf, "default")) { + pci_init_reset_methods(pdev); + return count; + } + + options = kstrndup(buf, count, GFP_KERNEL); + if (!options) + return -ENOMEM; + + while ((name = strsep(&options, ",")) != NULL) { + int i; + + if (sysfs_streq(name, "")) + continue; + + name = strim(name); + + for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { + if (sysfs_streq(name, pci_reset_fn_methods[i].name) && + !pci_reset_fn_methods[i].reset_fn(pdev, 1)) { + reset_methods[n++] = i; + break; + } + } + + if (i == PCI_NUM_RESET_METHODS) { + kfree(options); + return -EINVAL; + } + } + + if (!pci_reset_fn_methods[1].reset_fn(pdev, 1) && reset_methods[0] != 1) + pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); + +set_reset_methods: + memcpy(pdev->reset_methods, reset_methods, sizeof(reset_methods)); + kfree(options); + return count; +} +static DEVICE_ATTR_RW(reset_method); + +static struct attribute *pci_dev_reset_method_attrs[] = { + &dev_attr_reset_method.attr, + NULL, +}; + +static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); + + if (!pci_reset_supported(pdev)) + return 0; + + return a->mode; +} + +static const struct attribute_group pci_dev_reset_method_attr_group = { + .attrs = pci_dev_reset_method_attrs, + .is_visible = pci_dev_reset_method_attr_is_visible, +}; + static ssize_t reset_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1491,6 +1593,7 @@ const struct attribute_group *pci_dev_groups[] = { &pci_dev_config_attr_group, &pci_dev_rom_attr_group, &pci_dev_reset_attr_group, + &pci_dev_reset_method_attr_group, &pci_dev_vpd_attr_group, #ifdef CONFIG_DMI &pci_dev_smbios_attr_group, From patchwork Mon Jul 5 14:21:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359189 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5757C07E99 for ; Mon, 5 Jul 2021 14:22:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CEE4B61954 for ; Mon, 5 Jul 2021 14:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231502AbhGEOZD (ORCPT ); Mon, 5 Jul 2021 10:25:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231469AbhGEOZD (ORCPT ); Mon, 5 Jul 2021 10:25:03 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0CE1C061574; Mon, 5 Jul 2021 07:22:26 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id 17so16574804pfz.4; Mon, 05 Jul 2021 07:22:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/PjGID5YE9bZJ8kbC8yKj/6YFVLjY36xUbGOb1a2xcI=; b=GoDCjirhWMsN6+Y2JNydQeJbbQtD0Qbn4yh1jJqCmqTp3WXjNN+I4pYMu+Xnh7tByV 1stFDKLiCLBX/D1Oy10gpP4KspcxhHMn61U7i5q/U1M5fYhEGz2ju4hJo8SOtvCubL4v dU9ZzmLwMEGIYZBJYmxcINj/9x+/rHBJjj/cMDIbuvWNIT0QeFPKFGj3GTHke9Y3ggCE djUTBOqoaokVF4ldVCHwcXzl56Ge89SizTHEk8WZJ9pmLe8CQho7X8uW3OqTd2l/6hPw ANNihTVnCwYgs7dn8lxEA2xUFR2+Z/KClhQgRzHl8BaN9PmD8u3fusJlSQoYX2aUOdIc iS7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/PjGID5YE9bZJ8kbC8yKj/6YFVLjY36xUbGOb1a2xcI=; b=qM/XJ+vny6Mv5bSDLQ4m1tWe+GvQ2Uu1engDuKrtw7BhejFJ7MTjuAmOfKSgAHkXcd 2uGDKpyix/paZwM5mXdMJJE8tPFjqJQZzD69jIARnZCy+rR1Iw+Yv4NQmUbuukAbNfgi j+5socjjNGnJCXJXECPJCQhPjI/r9vof++9nCzygvu0dbCkrMw7Bffq5sMhcuLUou6vA HU4roXMdbHL9YCCVvbrlV75riyW5iH8HOVrfAhnmoeViLPlqohX4+rYD2rrn43wrfR8a 6MArvOozfB35LL6I03NhHRuUmLdnM2yzcGUkwZh00VW1A+Q7/+iOz26JQVr2YMlwiN8Z EKQA== X-Gm-Message-State: AOAM5338eCI6kYLnYB2uRX6DYIgmusDsBbbQa478Qi6I0n3LGRx2MYmy Cdbxw7U7zBBWl4HfSZzIyH4= X-Google-Smtp-Source: ABdhPJwvmf49bAD0+eLDOE6Oj3quiVo7zXB4rdPF7ZB7Vmzknbd/i1+fD41EhaGJxVswlWRYJEpMUg== X-Received: by 2002:a63:e948:: with SMTP id q8mr16201181pgj.52.1625494946320; Mon, 05 Jul 2021 07:22:26 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:26 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" Subject: [PATCH v9 5/8] PCI: Define a function to set ACPI_COMPANION in pci_dev Date: Mon, 5 Jul 2021 19:51:35 +0530 Message-Id: <20210705142138.2651-6-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni Move the existing code logic from acpi_pci_bridge_d3() to a separate function pci_set_acpi_fwnode() to set the ACPI fwnode. No functional change with this patch. Signed-off-by: Shanker Donthineni --- drivers/pci/pci-acpi.c | 12 ++++++++---- drivers/pci/pci.h | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 36bc23e21..eaddbf701 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -934,6 +934,13 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) static struct acpi_device *acpi_pci_find_companion(struct device *dev); +void pci_set_acpi_fwnode(struct pci_dev *dev) +{ + if (!ACPI_COMPANION(&dev->dev) && !pci_dev_is_added(dev)) + ACPI_COMPANION_SET(&dev->dev, + acpi_pci_find_companion(&dev->dev)); +} + static bool acpi_pci_bridge_d3(struct pci_dev *dev) { const struct fwnode_handle *fwnode; @@ -945,11 +952,8 @@ static bool acpi_pci_bridge_d3(struct pci_dev *dev) return false; /* Assume D3 support if the bridge is power-manageable by ACPI. */ + pci_set_acpi_fwnode(dev); adev = ACPI_COMPANION(&dev->dev); - if (!adev && !pci_dev_is_added(dev)) { - adev = acpi_pci_find_companion(&dev->dev); - ACPI_COMPANION_SET(&dev->dev, adev); - } if (adev && acpi_device_power_manageable(adev)) return true; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index db1ad94e7..990b73e90 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -704,7 +704,9 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL #ifdef CONFIG_ACPI int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; +void pci_set_acpi_fwnode(struct pci_dev *dev); #else +static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} static inline int pci_acpi_program_hp_params(struct pci_dev *dev) { return -ENODEV; From patchwork Mon Jul 5 14:21:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359191 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 738CDC07E99 for ; Mon, 5 Jul 2021 14:22:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5117C61954 for ; Mon, 5 Jul 2021 14:22:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231528AbhGEOZO (ORCPT ); Mon, 5 Jul 2021 10:25:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbhGEOZJ (ORCPT ); Mon, 5 Jul 2021 10:25:09 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D41ABC061574; Mon, 5 Jul 2021 07:22:31 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id s13so7236698plg.12; Mon, 05 Jul 2021 07:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v1N3+qWlEG+Qg73HGcApeu+QIm5Y+1lSdg14qL5Ytgo=; b=I6oizvPvHL+WCwjmHmcKNfI8iLnnA8kGMIJghSJdL7NOyRvGA+HBQBIE24G1bi/9Ca xvRwl7bqE/sD0teac/t8TCVF4biSLZ1KFjqgDGbZJw10k86MNJenqJq8bTLcqZCq3OfA xCUjyFt9t/FeTIupXBgJ4LfYIb4hlmVqCk7WjZ5ZXp+C4L1En/tY2esULG9Sm4VTFwZa 3DoSdZ8hONVKrWB2C2/Dp8ZYnsYj9gybx951BzPuqSiJ+37coP3juCrDfpARlyPelNAA tf0iQ3zbhdVbtivhr7DFinJXX+PuDfLmF77PZzBqIanzVChm0d0A0gBvzKbYMkgIKMJo Gz8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1N3+qWlEG+Qg73HGcApeu+QIm5Y+1lSdg14qL5Ytgo=; b=OINWRbLiRVJFiTnjMNV4ct6nt8CmBzhtgI34fpX1npAMpqvcnf9vKfQVBJwyEFYzew b31NyNnv3d+Xa/RZIiKf4JKAVPbzz9FdLg5IptoNdYG/2iNpIVQNxWmLjayyCzb63OlL v7bN4MFuAcUF5SeR1wZO20epjN5sscNGAuZw3by7zlRrFOnObGVT+yPq732Rx3hG+uI1 QezkOOkI7YElqbawraIG2H+0Vbqy1L+KJBpXlWhxLt3MuGbGb9O/3dO+vFyM1w4PfV2l /JQQtOZdDnmKepTEtYb6zVBOMdU00pnFGwxwpkwWl9Q5ZTfu4bH8795oaslQloYXdISe yZhA== X-Gm-Message-State: AOAM530VGCCl80llBscJ+T6jzqZe7zzrtNGWsg/MxIUWtMKU73g7ur8B hPlrjF5Ss8uVcGD+kgsmmA0= X-Google-Smtp-Source: ABdhPJz3/tGECHbpfs2E9rtjoI6L8iPtlP5MuPrr/j0yag0LiG5a6nzU96OZdYMt1r097qE3mVv9EA== X-Received: by 2002:a17:90a:6d89:: with SMTP id a9mr15816933pjk.194.1625494951443; Mon, 05 Jul 2021 07:22:31 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:31 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" Subject: [PATCH v9 6/8] PCI: Setup ACPI fwnode early and at the same time with OF Date: Mon, 5 Jul 2021 19:51:36 +0530 Message-Id: <20210705142138.2651-7-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni The pci_dev objects are created through two mechanisms 1) during PCI bus scan and 2) from I/O Virtualization. The fwnode in pci_dev object is being set at different places depends on the type of firmware used, device creation mechanism, and acpi_pci_bridge_d3() WAR. The software features which have a dependency on ACPI fwnode properties and need to be handled before device_add() will not work. One use case, the software has to check the existence of _RST method to support ACPI based reset method. This patch does the two changes in order to provide fwnode consistently. - Set ACPI and OF fwnodes from pci_setup_device(). - Remove pci_set_acpi_fwnode() in acpi_pci_bridge_d3(). After this patch, ACPI/OF firmware properties are visible at the same time during the early stage of pci_dev setup. And also call sites should be able to use firmware agnostic functions device_property_xxx() for the early PCI quirks in the future. Signed-off-by: Shanker Donthineni --- drivers/pci/pci-acpi.c | 1 - drivers/pci/probe.c | 7 ++++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index eaddbf701..dae021322 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -952,7 +952,6 @@ static bool acpi_pci_bridge_d3(struct pci_dev *dev) return false; /* Assume D3 support if the bridge is power-manageable by ACPI. */ - pci_set_acpi_fwnode(dev); adev = ACPI_COMPANION(&dev->dev); if (adev && acpi_device_power_manageable(adev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 221a20415..ba0137322 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1790,6 +1790,9 @@ int pci_setup_device(struct pci_dev *dev) dev->error_state = pci_channel_io_normal; set_pcie_port_type(dev); + pci_set_of_node(dev); + pci_set_acpi_fwnode(dev); + pci_dev_assign_slot(dev); /* @@ -1925,6 +1928,7 @@ int pci_setup_device(struct pci_dev *dev) default: /* unknown header */ pci_err(dev, "unknown header type %02x, ignoring device\n", dev->hdr_type); + pci_release_of_node(dev); return -EIO; bad: @@ -2352,10 +2356,7 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) dev->vendor = l & 0xffff; dev->device = (l >> 16) & 0xffff; - pci_set_of_node(dev); - if (pci_setup_device(dev)) { - pci_release_of_node(dev); pci_bus_put(dev->bus); kfree(dev); return NULL; From patchwork Mon Jul 5 14:21:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359193 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04ACAC07E9C for ; Mon, 5 Jul 2021 14:22:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E54D361954 for ; Mon, 5 Jul 2021 14:22:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231539AbhGEOZO (ORCPT ); Mon, 5 Jul 2021 10:25:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231540AbhGEOZN (ORCPT ); Mon, 5 Jul 2021 10:25:13 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E282FC061760; Mon, 5 Jul 2021 07:22:36 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id h4so18429517pgp.5; Mon, 05 Jul 2021 07:22:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cUyFfTZzWLY1nC0kNlDEdNgOhsBcCI3jl7nSUjoy+o0=; b=oxqRWx3hnchLIDwXqQSlZqMYE0Ze5PHmuqc5ExIoQDqZyG8j5GEJzu462t8oQYtA1F sO23iz5yRYe3P0fFxjWns3HJTumyPJ73UY3eaSPWMd519rBcdCam/SQ83I72l9hPUKFE ewAgiDh2+HBASAVbwv9+NBryrlxwG7kGb2FD8EwwJuGoXBN+s+29ZVj/CL/Ay/R9p9Ei 1HCbT1D0RZzWbtRkpHj/9QCKLl98wN7cIi3eZ4v46RZhQyGs9gooyjnCUhRRXaSJbitB PFnRJCoPB7Dl1FuY50X4HX3EWio54R6UJVcWNzjQLIf7afg+NRL6FvZLSzj7mGovqgrS 7yZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cUyFfTZzWLY1nC0kNlDEdNgOhsBcCI3jl7nSUjoy+o0=; b=AZkoGnfGuqS3C327t7T7MVne0PZ41b2v6urO1ebKQwjTECKBbGEj4stB8BsX6tnXxI AZrsi/p0DTUaVhie5HeTh0/28XmqR5dhf4fgY7KRk/jN5wJblJPlHG438MgYgyYv/qyJ rXr0/b8Ulx0tuTH9IE/PwpVPGMgW2nF4MZyAg/qIjXXJ2hptGy/QttV9xxAyQwAJH9xm lWUitWPgGRqw8FvEjVd0ZF5nDG13uN2YV6VfQug1hsvcT9o0+6bz8F/Ii3VbJWu5twtR R4D4So8ADFLihcCwAYFsYhmIdqARkbL4CCE7NQyF636lsFsxiM1uoime9Hod5XjK5Zt9 /8iQ== X-Gm-Message-State: AOAM532mz2zY6o519YADLoZnyH62bYMc2BbqgtfLjj/yX9diX6qyAkt9 o0KMLaUn+GCJuas3YUYRZv8= X-Google-Smtp-Source: ABdhPJyLMc113K9irs1cGiipwliBGIG4AQ0ypBvY1CXqLMk+USAAYNpktPDvkki6FbelJLgJLpxnXA== X-Received: by 2002:a63:5912:: with SMTP id n18mr16135678pgb.108.1625494956558; Mon, 05 Jul 2021 07:22:36 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:36 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" Subject: [PATCH v9 7/8] PCI: Add support for ACPI _RST reset method Date: Mon, 5 Jul 2021 19:51:37 +0530 Message-Id: <20210705142138.2651-8-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The default priority of the ACPI reset is set to below device-specific and above hardware resets. Signed-off-by: Shanker Donthineni Suggested-by: Alex Williamson Reviewed-by: Sinan Kaya --- drivers/pci/pci-acpi.c | 23 +++++++++++++++++++++++ drivers/pci/pci.c | 1 + drivers/pci/pci.h | 6 ++++++ include/linux/pci.h | 2 +- 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index dae021322..b6de71d15 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -941,6 +941,29 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) acpi_pci_find_companion(&dev->dev)); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + if (probe) + return 0; + + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "ACPI _RST failed\n"); + return -EINVAL; + } + + return 0; +} + static bool acpi_pci_bridge_d3(struct pci_dev *dev) { const struct fwnode_handle *fwnode; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d5c16492c..1e64dbd3e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5115,6 +5115,7 @@ static void pci_dev_restore(struct pci_dev *dev) const struct pci_reset_fn_method pci_reset_fn_methods[] = { { }, { &pci_dev_specific_reset, .name = "device_specific" }, + { &pci_dev_acpi_reset, .name = "acpi" }, { &pcie_reset_flr, .name = "flr" }, { &pci_af_flr, .name = "af_flr" }, { &pci_pm_reset, .name = "pm" }, diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 990b73e90..2c12017ed 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -705,7 +705,13 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; void pci_set_acpi_fwnode(struct pci_dev *dev); +int pci_dev_acpi_reset(struct pci_dev *dev, int probe); #else +static inline int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ + return -ENOTTY; +} + static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} static inline int pci_acpi_program_hp_params(struct pci_dev *dev) { diff --git a/include/linux/pci.h b/include/linux/pci.h index f34563831..c3b0d771c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -50,7 +50,7 @@ PCI_STATUS_PARITY) /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 6 +#define PCI_NUM_RESET_METHODS 7 /* * The PCI interface treats multi-function devices as independent From patchwork Mon Jul 5 14:21:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12359195 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EBFEC07E99 for ; Mon, 5 Jul 2021 14:22:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1297A61963 for ; Mon, 5 Jul 2021 14:22:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231556AbhGEOZT (ORCPT ); Mon, 5 Jul 2021 10:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231551AbhGEOZT (ORCPT ); Mon, 5 Jul 2021 10:25:19 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B96AAC061574; Mon, 5 Jul 2021 07:22:42 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id o4so7268454plg.1; Mon, 05 Jul 2021 07:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wWttAaWSLHmjeJigDoXsaFbkl5Yq2Db87lL7nx7iZ78=; b=OjRpCIxTEx0i0T35dflZLDTecYiU0b4Ranl71uAtYtKU6CxBITdPj0XjFqAmdZgjA6 ugjX/BVak8Kl/CB8bFJiuHEHpTwHgmUQkBbztTgZ+pX9TtGeaJO25sRzIhrVqQCd8e0z CE3tFl8WOHTuzFdArdLvFDZ2HKyjwjHLaAK2tw6hOMZgyJfColovNOuhFK7M9pe9XyoB M3Q2TJBu8nabNeRgBHXddmPoxIgF2Rkf77C+VgkWj+s7ccbVHs1e/GLtMvJ2zW2iTpuJ MtbU7g0bLOBZz8AAAuJOqUVns9nTl7ytnMe9Ipntx3Gdfdzl7Au4m4oSJB36q2+9VG78 EHrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wWttAaWSLHmjeJigDoXsaFbkl5Yq2Db87lL7nx7iZ78=; b=PSrxeA/l0XH6gccPmXdAW7FYG6SaCr6emuqPuQKh7xkI+Q3pxn7/4tXKX7aPwFkBN9 R9jd2ql34VFgOr+00Mh5qk/brg0ygCGY6hiyL2VHh9bI0yxlvMIAxL6DVIZ66ZOmPixj vf449s0Z5CnSmSgz+UAjO7TEoQRh6W8fVPJaJ+eBPjetVzdOpAqi4iRgzQqe/gNNyC7w lIdMrQQU+cGevlSw173FSH9Hun6MzlNDHPFKJdALUI7cit3+JgcvFyQ78tz+X0Baaxgk HPBIHc9pW2LRoALdYOwr3Kle8wmf+aG/87wgnfbOYE5T5auWUsP27JFPb0+BB1CJy7z7 pxQw== X-Gm-Message-State: AOAM533KG3yno8CTq/TbgyhOLNKYJScauCu1mdDILe4HQo7UvVHydxRO ooOKBEznjEDxR9iN0O0ETSQ= X-Google-Smtp-Source: ABdhPJwOHStEv8LftLUDRJhNc6gNTbGmgg02NKV1/Rgj9kOz3tQGyVvgrMsm0usY6ClbXE8Il2lHgQ== X-Received: by 2002:a17:90a:5306:: with SMTP id x6mr15490845pjh.59.1625494962231; Mon, 05 Jul 2021 07:22:42 -0700 (PDT) Received: from localhost.localdomain ([2409:4042:2696:1624:5e13:abf4:6ecf:a1f1]) by smtp.googlemail.com with ESMTPSA id 92sm22615307pjv.29.2021.07.05.07.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 07:22:41 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Len Brown , "Rafael J . Wysocki" , Amey Narkhede Subject: [PATCH v9 8/8] PCI: Change the type of probe argument in reset functions Date: Mon, 5 Jul 2021 19:51:38 +0530 Message-Id: <20210705142138.2651-9-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210705142138.2651-1-ameynarkhede03@gmail.com> References: <20210705142138.2651-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new enum pci_reset_mode_t to make the context of probe argument in reset functions clear and the code easier to read. Change the type of probe argument in functions which implement reset methods from int to pci_reset_mode_t to make the intent clear. Add a new line in return statement of pci_reset_bus_function(). Suggested-by: Alex Williamson Suggested-by: Krzysztof Wilczyński Signed-off-by: Amey Narkhede --- drivers/crypto/cavium/nitrox/nitrox_main.c | 2 +- .../ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/hotplug/pciehp.h | 2 +- drivers/pci/hotplug/pciehp_hpc.c | 4 +- drivers/pci/pci-acpi.c | 10 ++- drivers/pci/pci-sysfs.c | 6 +- drivers/pci/pci.c | 85 ++++++++++++------- drivers/pci/pci.h | 12 +-- drivers/pci/pcie/aer.c | 2 +- drivers/pci/quirks.c | 37 ++++---- include/linux/pci.h | 8 +- include/linux/pci_hotplug.h | 2 +- 12 files changed, 105 insertions(+), 67 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index 15d6c8452..f97fa8e99 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,7 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - pcie_reset_flr(pdev, 0); + pcie_reset_flr(pdev, PCI_RESET_DO_RESET); pci_restore_state(pdev); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 336d149ee..6e666be69 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (!pcie_reset_flr(oct->pci_dev, 1)) + if (!pcie_reset_flr(oct->pci_dev, PCI_RESET_PROBE)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 4fd200d8b..87da03adc 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -181,7 +181,7 @@ void pciehp_release_ctrl(struct controller *ctrl); int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot); int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot); -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe); +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode); int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status); int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status); int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index fb3840e22..24b3c8787 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -834,14 +834,14 @@ void pcie_disable_interrupt(struct controller *ctrl) * momentarily, if we see that they could interfere. Also, clear any spurious * events after. */ -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode) { struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; int rc; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; down_write(&ctrl->reset_lock); diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index b6de71d15..a92ed574a 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -944,16 +944,20 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) /** * pci_dev_acpi_reset - do a function level reset using _RST method * @dev: device to reset - * @probe: check if _RST method is included in the acpi_device context. + * @probe: If PCI_RESET_PROBE, check whether _RST method is included + * in the acpi_device context. */ -int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { acpi_handle handle = ACPI_HANDLE(&dev->dev); + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 8a740e211..dcf19f6d6 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1393,7 +1393,8 @@ static ssize_t reset_method_store(struct device *dev, for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { if (sysfs_streq(name, pci_reset_fn_methods[i].name) && - !pci_reset_fn_methods[i].reset_fn(pdev, 1)) { + !pci_reset_fn_methods[i].reset_fn(pdev, + PCI_RESET_PROBE)) { reset_methods[n++] = i; break; } @@ -1405,7 +1406,8 @@ static ssize_t reset_method_store(struct device *dev, } } - if (!pci_reset_fn_methods[1].reset_fn(pdev, 1) && reset_methods[0] != 1) + if (!pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) && + reset_methods[0] != 1) pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); set_reset_methods: diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1e64dbd3e..60204cee6 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4650,30 +4650,36 @@ EXPORT_SYMBOL_GPL(pcie_flr); /** * pcie_reset_flr - initiate a PCIe function level reset * @dev: device to reset - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * Initiate a function level reset on @dev. */ -int pcie_reset_flr(struct pci_dev *dev, int probe) +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode) { + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return -ENOTTY; if (!dev->has_pcie_flr) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pcie_flr(dev); } EXPORT_SYMBOL_GPL(pcie_reset_flr); -static int pci_af_flr(struct pci_dev *dev, int probe) +static int pci_af_flr(struct pci_dev *dev, pci_reset_mode_t mode) { int pos; u8 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + pos = pci_find_capability(dev, PCI_CAP_ID_AF); if (!pos) return -ENOTTY; @@ -4685,7 +4691,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -4716,7 +4722,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) /** * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. * @dev: Device to reset. - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is * unset, it will be reinitialized internally when going from PCI_D3hot to @@ -4728,10 +4734,13 @@ static int pci_af_flr(struct pci_dev *dev, int probe) * by default (i.e. unless the @dev's d3hot_delay field has a different value). * Moreover, only devices in D0 can be reset by this function. */ -static int pci_pm_reset(struct pci_dev *dev, int probe) +static int pci_pm_reset(struct pci_dev *dev, pci_reset_mode_t mode) { u16 csr; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4739,7 +4748,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) if (csr & PCI_PM_CTRL_NO_SOFT_RESET) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (dev->current_state != PCI_D0) @@ -4988,10 +4997,13 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); -static int pci_parent_bus_reset(struct pci_dev *dev, int probe) +static int pci_parent_bus_reset(struct pci_dev *dev, pci_reset_mode_t mode) { struct pci_dev *pdev; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; @@ -5000,44 +5012,47 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe) if (pdev != dev) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pci_bridge_secondary_bus_reset(dev->bus->self); } -static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) +static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, pci_reset_mode_t mode) { int rc = -ENOTTY; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!hotplug || !try_module_get(hotplug->owner)) return rc; if (hotplug->ops->reset_slot) - rc = hotplug->ops->reset_slot(hotplug, probe); + rc = hotplug->ops->reset_slot(hotplug, mode); module_put(hotplug->owner); return rc; } -static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) +static int pci_dev_reset_slot_function(struct pci_dev *dev, pci_reset_mode_t mode) { if (dev->multifunction || dev->subordinate || !dev->slot || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; - return pci_reset_hotplug_slot(dev->slot->hotplug, probe); + return pci_reset_hotplug_slot(dev->slot->hotplug, mode); } -static int pci_reset_bus_function(struct pci_dev *dev, int probe) +static int pci_reset_bus_function(struct pci_dev *dev, pci_reset_mode_t mode) { int rc; - rc = pci_dev_reset_slot_function(dev, probe); + rc = pci_dev_reset_slot_function(dev, mode); if (rc != -ENOTTY) return rc; - return pci_parent_bus_reset(dev, probe); + return pci_parent_bus_reset(dev, mode); } static void pci_dev_lock(struct pci_dev *dev) @@ -5157,7 +5172,7 @@ int __pci_reset_function_locked(struct pci_dev *dev) * mechanisms might be broken on the device. */ for (i = 0; i < PCI_NUM_RESET_METHODS && (m = dev->reset_methods[i]); i++) { - rc = pci_reset_fn_methods[m].reset_fn(dev, 0); + rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET); if (!rc) return 0; if (rc != -ENOTTY) @@ -5192,7 +5207,7 @@ void pci_init_reset_methods(struct pci_dev *dev) might_sleep(); for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { - rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_PROBE); if (!rc) reset_methods[n++] = i; else if (rc != -ENOTTY) @@ -5509,21 +5524,24 @@ static void pci_slot_restore_locked(struct pci_slot *slot) } } -static int pci_slot_reset(struct pci_slot *slot, int probe) +static int pci_slot_reset(struct pci_slot *slot, pci_reset_mode_t mode) { int rc; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!slot || !pci_slot_resetable(slot)) return -ENOTTY; - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_lock(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, probe); + rc = pci_reset_hotplug_slot(slot->hotplug, mode); - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_unlock(slot); return rc; @@ -5537,7 +5555,7 @@ static int pci_slot_reset(struct pci_slot *slot, int probe) */ int pci_probe_reset_slot(struct pci_slot *slot) { - return pci_slot_reset(slot, 1); + return pci_slot_reset(slot, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_slot); @@ -5560,14 +5578,14 @@ static int __pci_reset_slot(struct pci_slot *slot) { int rc; - rc = pci_slot_reset(slot, 1); + rc = pci_slot_reset(slot, PCI_RESET_PROBE); if (rc) return rc; if (pci_slot_trylock(slot)) { pci_slot_save_and_disable_locked(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, 0); + rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); pci_slot_restore_locked(slot); pci_slot_unlock(slot); } else @@ -5576,14 +5594,17 @@ static int __pci_reset_slot(struct pci_slot *slot) return rc; } -static int pci_bus_reset(struct pci_bus *bus, int probe) +static int pci_bus_reset(struct pci_bus *bus, pci_reset_mode_t mode) { int ret; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!bus->self || !pci_bus_resetable(bus)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; pci_bus_lock(bus); @@ -5622,14 +5643,14 @@ int pci_bus_error_reset(struct pci_dev *bridge) goto bus_reset; list_for_each_entry(slot, &bus->slots, list) - if (pci_slot_reset(slot, 0)) + if (pci_slot_reset(slot, PCI_RESET_DO_RESET)) goto bus_reset; mutex_unlock(&pci_slot_mutex); return 0; bus_reset: mutex_unlock(&pci_slot_mutex); - return pci_bus_reset(bridge->subordinate, 0); + return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); } /** @@ -5640,7 +5661,7 @@ int pci_bus_error_reset(struct pci_dev *bridge) */ int pci_probe_reset_bus(struct pci_bus *bus) { - return pci_bus_reset(bus, 1); + return pci_bus_reset(bus, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_bus); @@ -5654,7 +5675,7 @@ static int __pci_reset_bus(struct pci_bus *bus) { int rc; - rc = pci_bus_reset(bus, 1); + rc = pci_bus_reset(bus, PCI_RESET_PROBE); if (rc) return rc; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2c12017ed..06be9e6fa 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -604,19 +604,19 @@ static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) struct pci_dev_reset_methods { u16 vendor; u16 device; - int (*reset)(struct pci_dev *dev, int probe); + int (*reset)(struct pci_dev *dev, pci_reset_mode_t mode); }; struct pci_reset_fn_method { - int (*reset_fn)(struct pci_dev *pdev, int probe); + int (*reset_fn)(struct pci_dev *pdev, pci_reset_mode_t mode); char *name; }; extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS -int pci_dev_specific_reset(struct pci_dev *dev, int probe); +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } @@ -705,9 +705,9 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; void pci_set_acpi_fwnode(struct pci_dev *dev); -int pci_dev_acpi_reset(struct pci_dev *dev, int probe); +int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 98077595a..cfa7a1775 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,7 +1405,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - rc = pcie_reset_flr(dev, 0); + rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); if (!rc) pci_info(dev, "has been reset\n"); else diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e86cf4a3b..e7f15fc02 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3669,7 +3669,7 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, * reset a single function if other methods (e.g. FLR, PM D0->D3) are * not available. */ -static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) +static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, pci_reset_mode_t mode) { /* * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf @@ -3679,7 +3679,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) * Thus we must call pcie_flr() directly without first checking if it is * supported. */ - if (!probe) + if (mode == PCI_RESET_DO_RESET) pcie_flr(dev); return 0; } @@ -3691,13 +3691,13 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) #define NSDE_PWR_STATE 0xd0100 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ -static int reset_ivb_igd(struct pci_dev *dev, int probe) +static int reset_ivb_igd(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *mmio_base; unsigned long timeout; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; mmio_base = pci_iomap(dev, 0, 0); @@ -3734,7 +3734,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe) } /* Device-specific reset method for Chelsio T4-based adapters */ -static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) +static int reset_chelsio_generic_dev(struct pci_dev *dev, pci_reset_mode_t mode) { u16 old_command; u16 msix_flags; @@ -3750,7 +3750,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * If this is the "probe" phase, return 0 indicating that we can * reset this device. */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -3812,17 +3812,17 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * Chapter 3: NVMe control registers * Chapter 7.3: Reset behavior */ -static int nvme_disable_and_flr(struct pci_dev *dev, int probe) +static int nvme_disable_and_flr(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *bar; u16 cmd; u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); @@ -3886,11 +3886,13 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) * device too soon after FLR. A 250ms delay after FLR has heuristically * proven to produce reliably working results for device assignment cases. */ -static int delay_250ms_after_flr(struct pci_dev *dev, int probe) +static int delay_250ms_after_flr(struct pci_dev *dev, pci_reset_mode_t mode) { - int ret = pcie_reset_flr(dev, probe); + int ret; + + ret = pcie_reset_flr(dev, mode); - if (probe) + if (ret || mode == PCI_RESET_PROBE) return ret; msleep(250); @@ -3906,13 +3908,13 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ -static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe) +static int reset_hinic_vf_dev(struct pci_dev *pdev, pci_reset_mode_t mode) { unsigned long timeout; void __iomem *bar; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(pdev, 0, 0); @@ -3983,16 +3985,19 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { * because when a host assigns a device to a guest VM, the host may need * to reset the device but probably doesn't have a driver for it. */ -int pci_dev_specific_reset(struct pci_dev *dev, int probe) +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { const struct pci_dev_reset_methods *i; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + for (i = pci_dev_reset_methods; i->reset; i++) { if ((i->vendor == dev->vendor || i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return i->reset(dev, mode); } return -ENOTTY; diff --git a/include/linux/pci.h b/include/linux/pci.h index c3b0d771c..0d650c873 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -52,6 +52,12 @@ /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ #define PCI_NUM_RESET_METHODS 7 +typedef enum pci_reset_mode { + PCI_RESET_DO_RESET, + PCI_RESET_PROBE, + PCI_RESET_MODE_MAX, +} pci_reset_mode_t; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -1232,7 +1238,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -int pcie_reset_flr(struct pci_dev *dev, int probe); +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index b482e42d7..9e8da46e7 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -44,7 +44,7 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*reset_slot) (struct hotplug_slot *slot, int probe); + int (*reset_slot) (struct hotplug_slot *slot, pci_reset_mode_t mode); }; /**