From patchwork Fri Jul 9 10:41:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12367129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A47CC07E9B for ; Fri, 9 Jul 2021 10:43:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9F17E613CF for ; Fri, 9 Jul 2021 10:43:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9F17E613CF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CKl7HRA/wMal9CN7ITqcfDfwD7JHnjuZswtF6hS9jSc=; b=16utQqbtWUMPHj ofOWxCxkL0RvZ6ePa3cKgF+jtfFLJDVGCQBFAOB3kLhSJatlj1x73egoNY+zX9mEiEYJO85HFCMac oB4uOvH/RaPF12axVYAwEKMn0NC4nJuF1vw6keytbudgFGuF/4r5UBG9MIyILDP9W0E2gEMmLDPQZ 0ukZZnguL77elJEM3HsQiPMVqRhsb760YKOk2E2AttCP7LeqadMorbOVs8PSYiFJMlC4yAARS7tLV B4TtfYPZBbgRo6Xp04kgioPtX0PremBl+K1LzUjkY6o0h09gtLHyMltD9dRxG5PTcYwzji7w3xRrl WxK7GN6GRPfkiZhiZdlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m1nxb-001Zgx-TL; Fri, 09 Jul 2021 10:42:20 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m1nxB-001ZYT-H6 for linux-arm-kernel@lists.infradead.org; Fri, 09 Jul 2021 10:42:00 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 15ABC613E1; Fri, 9 Jul 2021 10:41:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625827313; bh=fPefUPSOWcPfKD2PSYIT5O1A1N5dDc1L1HZoEEtQR8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uG6ZogdC+m1wNmaB9uxasVYdv1/fXFr+crHt11+yqbNtj77nsGb/pcx7Mt5wWwtWR hv9nSsFKILNpabNwfzzOcuevaFSuL5LuMgQDCr6CSgfTU500+uapLHWWh5GWgldItC gLY3xyp+7xbLIlSIy8ycKPgohgvmgSYZscLyIlGj0fj+s3camBeULvFXH+M4vhYM3N fUnrQZVLkPQqnK5mlC+6NkMmGc7eFT7LoljKm2i+MlpQM8StjL++M+8esGFtHV13Iq XqFGlPqD1Is0pzAfRhE0vNJLxOqpAk0qQx9ImDEWA0lk4WolHYhRrziD6iUQsBpqw1 uIbtjefcP0dOA== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1nx7-00B5Fo-Dd; Fri, 09 Jul 2021 12:41:49 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , =?utf-8?q?Krzysztof_Wilc?= =?utf-8?q?zy=C5=84ski?= , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 6/9] PCI: kirin: drop the PHY logic from the driver Date: Fri, 9 Jul 2021 12:41:42 +0200 Message-Id: <29ccfead1f665ed8028d4a3e7e3d28c573b632f1.1625826353.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210709_034153_681488_48AD2B99 X-CRM114-Status: GOOD ( 24.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pcie-kirin PCIe driver contains internally a PHY interface for a Kirin 960. Drop it and add support for using the new PHY driver for Kirin 960, updating DT accordingly. Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 ++- drivers/pci/controller/dwc/pcie-kirin.c | 252 +++------------------- 2 files changed, 47 insertions(+), 234 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 53890e8052a7..07a616b352f5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1001,17 +1001,33 @@ spi3: spi@ff3b3000 { status = "disabled"; }; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; - reg-names = "dbi", "apb", "phy", "config"; + reg-names = "dbi", "apb", "config"; bus-range = <0x0 0x1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + phys = <&pcie_phy>; ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>; @@ -1028,15 +1044,6 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", - "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; }; /* UFS */ diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 026fd1e42a55..a77bbecbf11f 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -21,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -28,26 +28,17 @@ #define to_kirin_pcie(x) dev_get_drvdata((x)->dev) -#define REF_CLK_FREQ 100000000 - /* PCIe ELBI registers */ #define SOC_PCIECTRL_CTRL0_ADDR 0x000 #define SOC_PCIECTRL_CTRL1_ADDR 0x004 -#define SOC_PCIEPHY_CTRL2_ADDR 0x008 -#define SOC_PCIEPHY_CTRL3_ADDR 0x00c #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) /* info located in APB */ #define PCIE_APP_LTSSM_ENABLE 0x01c -#define PCIE_APB_PHY_CTRL0 0x0 -#define PCIE_APB_PHY_CTRL1 0x4 #define PCIE_APB_PHY_STATUS0 0x400 #define PCIE_LINKUP_ENABLE (0x8020) #define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) #define PIPE_CLK_STABLE (0x1 << 19) -#define PHY_REF_PAD_BIT (0x1 << 8) -#define PHY_PWR_DOWN_BIT (0x1 << 22) -#define PHY_RST_ACK_BIT (0x1 << 16) /* info located in sysctrl */ #define SCTRL_PCIE_CMOS_OFFSET 0x60 @@ -60,36 +51,10 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) -/* peri_crg ctrl */ -#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 -#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 - -/* Time for delay */ -#define REF_2_PERST_MIN 20000 -#define REF_2_PERST_MAX 25000 -#define PERST_2_ACCESS_MIN 10000 -#define PERST_2_ACCESS_MAX 12000 -#define LINK_WAIT_MIN 900 -#define LINK_WAIT_MAX 1000 -#define PIPE_CLK_WAIT_MIN 550 -#define PIPE_CLK_WAIT_MAX 600 -#define TIME_CMOS_MIN 100 -#define TIME_CMOS_MAX 105 -#define TIME_PHY_PD_MIN 10 -#define TIME_PHY_PD_MAX 11 - struct kirin_pcie { struct dw_pcie *pci; + struct phy *phy; void __iomem *apb_base; - void __iomem *phy_base; - struct regmap *crgctrl; - struct regmap *sysctrl; - struct clk *apb_sys_clk; - struct clk *apb_phy_clk; - struct clk *phy_ref_clk; - struct clk *pcie_aclk; - struct clk *pcie_aux_clk; - int gpio_id_reset; }; /* Registers in PCIeCTRL */ @@ -104,46 +69,6 @@ static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) return readl(kirin_pcie->apb_base + reg); } -/* Registers in PCIePHY */ -static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->phy_base + reg); -} - -static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->phy_base + reg); -} - -static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - - kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); - if (IS_ERR(kirin_pcie->phy_ref_clk)) - return PTR_ERR(kirin_pcie->phy_ref_clk); - - kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux"); - if (IS_ERR(kirin_pcie->pcie_aux_clk)) - return PTR_ERR(kirin_pcie->pcie_aux_clk); - - kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); - if (IS_ERR(kirin_pcie->apb_phy_clk)) - return PTR_ERR(kirin_pcie->apb_phy_clk); - - kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); - if (IS_ERR(kirin_pcie->apb_sys_clk)) - return PTR_ERR(kirin_pcie->apb_sys_clk); - - kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk"); - if (IS_ERR(kirin_pcie->pcie_aclk)) - return PTR_ERR(kirin_pcie->pcie_aclk); - - return 0; -} - static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { @@ -152,149 +77,18 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); - kirin_pcie->phy_base = - devm_platform_ioremap_resource_byname(pdev, "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - - kirin_pcie->crgctrl = - syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); - if (IS_ERR(kirin_pcie->crgctrl)) - return PTR_ERR(kirin_pcie->crgctrl); - - kirin_pcie->sysctrl = - syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); - if (IS_ERR(kirin_pcie->sysctrl)) - return PTR_ERR(kirin_pcie->sysctrl); - return 0; } -static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie) -{ - struct device *dev = kirin_pcie->pci->dev; - u32 reg_val; - - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); - reg_val &= ~PHY_REF_PAD_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); - - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0); - reg_val &= ~PHY_PWR_DOWN_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0); - usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX); - - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); - reg_val &= ~PHY_RST_ACK_BIT; - kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); - - usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX); - reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); - if (reg_val & PIPE_CLK_STABLE) { - dev_err(dev, "PIPE clk is not stable\n"); - return -EINVAL; - } - - return 0; -} - -static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) -{ - u32 val; - - regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); - val |= PCIE_DEBOUNCE_PARAM; - val &= ~PCIE_OE_BYPASS; - regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); -} - -static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) -{ - int ret = 0; - - if (!enable) - goto close_clk; - - ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ); - if (ret) - return ret; - - ret = clk_prepare_enable(kirin_pcie->phy_ref_clk); - if (ret) - return ret; - - ret = clk_prepare_enable(kirin_pcie->apb_sys_clk); - if (ret) - goto apb_sys_fail; - - ret = clk_prepare_enable(kirin_pcie->apb_phy_clk); - if (ret) - goto apb_phy_fail; - - ret = clk_prepare_enable(kirin_pcie->pcie_aclk); - if (ret) - goto aclk_fail; - - ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk); - if (ret) - goto aux_clk_fail; - - return 0; - -close_clk: - clk_disable_unprepare(kirin_pcie->pcie_aux_clk); -aux_clk_fail: - clk_disable_unprepare(kirin_pcie->pcie_aclk); -aclk_fail: - clk_disable_unprepare(kirin_pcie->apb_phy_clk); -apb_phy_fail: - clk_disable_unprepare(kirin_pcie->apb_sys_clk); -apb_sys_fail: - clk_disable_unprepare(kirin_pcie->phy_ref_clk); - - return ret; -} - static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) { int ret; - /* Power supply for Host */ - regmap_write(kirin_pcie->sysctrl, - SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); - usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); - kirin_pcie_oe_enable(kirin_pcie); - - ret = kirin_pcie_clk_ctrl(kirin_pcie, true); + ret = phy_init(kirin_pcie->phy); if (ret) return ret; - /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ - regmap_write(kirin_pcie->sysctrl, - SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); - regmap_write(kirin_pcie->crgctrl, - CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); - regmap_write(kirin_pcie->sysctrl, - SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); - - ret = kirin_pcie_phy_init(kirin_pcie); - if (ret) - goto close_clk; - - /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) { - usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1); - if (ret) - goto close_clk; - usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); - - return 0; - } - -close_clk: - kirin_pcie_clk_ctrl(kirin_pcie, false); - return ret; + return phy_power_on(kirin_pcie->phy); } static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, @@ -444,30 +238,41 @@ static int kirin_pcie_probe(struct platform_device *pdev) pci->pp.ops = &kirin_pcie_host_ops; kirin_pcie->pci = pci; - ret = kirin_pcie_get_clk(kirin_pcie, pdev); - if (ret) - return ret; + kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); + if (IS_ERR(kirin_pcie->phy)) + return PTR_ERR(kirin_pcie->phy); ret = kirin_pcie_get_resource(kirin_pcie, pdev); if (ret) return ret; - kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) { - return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) { - dev_err(dev, "unable to get a valid gpio pin\n"); - return -ENODEV; - } - ret = kirin_pcie_power_on(kirin_pcie); if (ret) return ret; platform_set_drvdata(pdev, kirin_pcie); - return dw_pcie_host_init(&pci->pp); + ret = dw_pcie_host_init(&pci->pp); + if (ret) { + phy_power_off(kirin_pcie->phy); + goto err; + } + + return 0; +err: + phy_exit(kirin_pcie->phy); + + return ret; +} + +static int __exit kirin_pcie_remove(struct platform_device *pdev) +{ + struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); + + phy_power_off(kirin_pcie->phy); + phy_exit(kirin_pcie->phy); + + return 0; } static const struct of_device_id kirin_pcie_match[] = { @@ -477,6 +282,7 @@ static const struct of_device_id kirin_pcie_match[] = { static struct platform_driver kirin_pcie_driver = { .probe = kirin_pcie_probe, + .remove = __exit_p(kirin_pcie_remove), .driver = { .name = "kirin-pcie", .of_match_table = kirin_pcie_match, From patchwork Fri Jul 9 10:41:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12367127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4834EC07E9E for ; Fri, 9 Jul 2021 10:43:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 080B4613D1 for ; Fri, 9 Jul 2021 10:43:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 080B4613D1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=V4d75SlMnd5dOT3JyOKMAC7SqdsTT4QWMD5WzPq2pJs=; b=otO9OQAR1xRpoG 9SIqlW5iVuuxUlx73zeHDxlCNUayxY6bq4k9huhr1R1ChLPXIIzEfq3j/ziEqqaGArfMiTiUznePP 6Y+fYrHK7hKfidOWlFV1zZIHTUr9HgmNmjM/RT23ksCA4zRr6bRw4Vu82bRghUb3iYf/58e2r4fdz 6x1DVcQXlV87eD+dLIg3hLlPqeMbBRY6DwdiwlKj5djMDufM57hA7/XtI+Szgf2blWIR8ffDUHpXG 2HTSg7FcYSgjF86sELvftwh7eWE1JAENpjVjOZKtY87sP/CYG+dhoy6aiA+uRmP/DCei28TuYC+jS cu4sO0Lp27l32srTdPrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m1nxR-001Zes-9e; Fri, 09 Jul 2021 10:42:09 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m1nx9-001ZVv-Ph for linux-arm-kernel@lists.infradead.org; Fri, 09 Jul 2021 10:41:55 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5EA19613F0; Fri, 9 Jul 2021 10:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625827311; bh=m59H58S8c6uJmUxjlwS9k0tBdkqFiZIxmvII33/F3pI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SslcZji14eYszw8cDvpsfM8KITDXGg+CWncX5fUuz0NXcIxEYebukwcpftPMSPKsi OJQaVqH/hzX9FY6T/BH1nwFf65zUpB4XhdGAnHLHCry2Vd0MUpEr1/gojp/fYU0Bpp zdy+HKeWUoFzTuf8FACkfnSKhZ9AQoDsAzssUP/baWB1xYx2RmDpPb6/W4zNnhcoCl bXDraS2bm3x4+0hDcMSKO6HmUzK/Dl5Rc1h7wimkUCTqWl5zfyuDha+8M8w2GRwTHi 50EmuXR3PcvLwUpyjzjawpFPOqxkOOd1yOGnzUxJsYeMjdw+RN5ISbSVQtLQnV1LmA d4ApfW5g5CCwQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1nx7-00B5G4-LF; Fri, 09 Jul 2021 12:41:49 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v3 9/9] arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware Date: Fri, 9 Jul 2021 12:41:45 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210709_034151_937781_BCC1B9E9 X-CRM114-Status: GOOD ( 12.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manivannan Sadhasivam Add DTS bindings for the Hikey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6476149d99e3..f54dab70f01b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,72 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */