From patchwork Fri Jul 9 15:58:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Beguin X-Patchwork-Id: 12367635 X-Patchwork-Delegate: jic23@cam.ac.uk Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B615AC07E99 for ; Fri, 9 Jul 2021 15:59:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A07FB613B5 for ; Fri, 9 Jul 2021 15:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232427AbhGIQBy (ORCPT ); Fri, 9 Jul 2021 12:01:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232405AbhGIQBx (ORCPT ); Fri, 9 Jul 2021 12:01:53 -0400 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48B5DC0613E5; Fri, 9 Jul 2021 08:59:09 -0700 (PDT) Received: by mail-qk1-x72a.google.com with SMTP id t19so9750983qkg.7; Fri, 09 Jul 2021 08:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JuSZ3BR/evJA/FrHvqoUNYWit2iPKIVeOer6CmCvmrY=; b=FrMK2AynVnPyRl1+WPObShJxStizYk2TOx77+T/i0Jh+/QKwqQ90BODnMNQveiUc1E 2k/pTOsSY+4+VYTMjDWstOUb7U9gg2MUnCUPQQE7QzajMU3MKlVBln5U/HRs2OJCCwXw E2BvsJCqBkEGdDInV3vtlyX9loVkNrHlLDLiWqyAo5/Rc7epElPYv05dpZs+r7bG92vH 1G2vD9T4wRURQTDhyx9u+XNOLSo40ky8mIrvwi2+5zuRbzsHcKhfBAnv6gKu1Yzm/idS LnQYt2fR4hGnG+EOfBKOb76E77zp8D082fpSu+vX2b0en31aurFuIF+/zMgDQYCAO3OV B8pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JuSZ3BR/evJA/FrHvqoUNYWit2iPKIVeOer6CmCvmrY=; b=aD8zRzCddy4anm2YKDl8KLuGKJUyL8ie4ChD6ccG9PXoKentPmjkIHsYfSPPpOiNFb xwURL5F1sMJdvHyaOmrxCCr+gSHaZFUNZ4WqlyA48NrCO6YDT+FiK/ie50xdstrlSE36 nBy6B5GYiP3qX4KwXaotfRg4WVDR3A/J67+VMBMHnTIY5fsmVjqccY9gT5HPyZHg3W+q t3ZYnOJVI4Wre987KyEHHLd7anWhxCW/HF1ApQGiQVOhxEtgzvZSddGx2mZ6TwDjl5XN /3crqrl3D606pMKDrYHLRcqQix3Y2rOqHgBQz3z3M7SfOhQtMRU7zySEX1z1+DoIxuPs yAvQ== X-Gm-Message-State: AOAM532tWDLWuxy9X6bSZ1794RPld7mFnC/QuwatDn1cVYz0ZnFHSrzk wr/T2g1O6iq8hnvCD0l6gW4= X-Google-Smtp-Source: ABdhPJxCmEzj+H6GCxK8GxNyboNmiXe/w6pwkhRy/rmWS4nm3a6iGg4A/cI7PP/9mFwrTSsU7yH1kQ== X-Received: by 2002:a37:b983:: with SMTP id j125mr24606125qkf.482.1625846348532; Fri, 09 Jul 2021 08:59:08 -0700 (PDT) Received: from shaak.xiphos.ca (198-48-202-89.cpe.pppoe.ca. [198.48.202.89]) by smtp.gmail.com with ESMTPSA id x15sm2606071qkm.66.2021.07.09.08.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 08:59:08 -0700 (PDT) From: Liam Beguin To: liambeguin@gmail.com, lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, charles-antoine.couret@essensium.com, Nuno.Sa@analog.com Cc: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Subject: [PATCH v2 1/4] iio: adc: ad7949: define and use bitfield names Date: Fri, 9 Jul 2021 11:58:53 -0400 Message-Id: <20210709155856.1732245-2-liambeguin@gmail.com> X-Mailer: git-send-email 2.30.1.489.g328c10930387 In-Reply-To: <20210709155856.1732245-1-liambeguin@gmail.com> References: <20210709155856.1732245-1-liambeguin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Liam Beguin Replace raw configuration register values by using FIELD_PREP and defines to improve readability. Signed-off-by: Liam Beguin --- drivers/iio/adc/ad7949.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 1b4b3203e428..93aacf4f680b 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -12,12 +12,27 @@ #include #include -#define AD7949_MASK_CHANNEL_SEL GENMASK(9, 7) #define AD7949_MASK_TOTAL GENMASK(13, 0) -#define AD7949_OFFSET_CHANNEL_SEL 7 -#define AD7949_CFG_READ_BACK 0x1 #define AD7949_CFG_REG_SIZE_BITS 14 +#define AD7949_CFG_BIT_CFG BIT(13) +#define AD7949_CFG_VAL_CFG_OVERWRITE 1 +#define AD7949_CFG_VAL_CFG_KEEP 0 +#define AD7949_CFG_BIT_INCC GENMASK(12, 10) +#define AD7949_CFG_VAL_INCC_UNIPOLAR_GND 7 +#define AD7949_CFG_VAL_INCC_UNIPOLAR_COMM 6 +#define AD7949_CFG_VAL_INCC_UNIPOLAR_DIFF 4 +#define AD7949_CFG_VAL_INCC_TEMP 3 +#define AD7949_CFG_VAL_INCC_BIPOLAR 2 +#define AD7949_CFG_VAL_INCC_BIPOLAR_DIFF 0 +#define AD7949_CFG_BIT_INX GENMASK(9, 7) +#define AD7949_CFG_BIT_BW BIT(6) +#define AD7949_CFG_VAL_BW_FULL 1 +#define AD7949_CFG_VAL_BW_QUARTER 0 +#define AD7949_CFG_BIT_REF GENMASK(5, 3) +#define AD7949_CFG_BIT_SEQ GENMASK(2, 1) +#define AD7949_CFG_BIT_RBN BIT(0) + enum { ID_AD7949 = 0, ID_AD7682, @@ -109,8 +124,8 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, */ for (i = 0; i < 2; i++) { ret = ad7949_spi_write_cfg(ad7949_adc, - channel << AD7949_OFFSET_CHANNEL_SEL, - AD7949_MASK_CHANNEL_SEL); + FIELD_PREP(AD7949_CFG_BIT_INX, channel), + AD7949_CFG_BIT_INX); if (ret) return ret; if (channel == ad7949_adc->current_channel) @@ -214,10 +229,19 @@ static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) { int ret; int val; + u16 cfg; - /* Sequencer disabled, CFG readback disabled, IN0 as default channel */ ad7949_adc->current_channel = 0; - ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL); + + cfg = FIELD_PREP(AD7949_CFG_BIT_CFG, AD7949_CFG_VAL_CFG_OVERWRITE) | + FIELD_PREP(AD7949_CFG_BIT_INCC, AD7949_CFG_VAL_INCC_UNIPOLAR_GND) | + FIELD_PREP(AD7949_CFG_BIT_INX, ad7949_adc->current_channel) | + FIELD_PREP(AD7949_CFG_BIT_BW, AD7949_CFG_VAL_BW_FULL) | + FIELD_PREP(AD7949_CFG_BIT_REF, AD7949_REF_EXT_BUF) | + FIELD_PREP(AD7949_CFG_BIT_SEQ, 0x0) | + FIELD_PREP(AD7949_CFG_BIT_RBN, 1); + + ret = ad7949_spi_write_cfg(ad7949_adc, cfg, AD7949_MASK_TOTAL); /* * Do two dummy conversions to apply the first configuration setting. From patchwork Fri Jul 9 15:58:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Beguin X-Patchwork-Id: 12367637 X-Patchwork-Delegate: jic23@cam.ac.uk Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44AACC11F68 for ; Fri, 9 Jul 2021 15:59:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 31AC8613C9 for ; Fri, 9 Jul 2021 15:59:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231976AbhGIQB6 (ORCPT ); Fri, 9 Jul 2021 12:01:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232422AbhGIQBy (ORCPT ); Fri, 9 Jul 2021 12:01:54 -0400 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68894C0613DD; Fri, 9 Jul 2021 08:59:10 -0700 (PDT) Received: by mail-qk1-x72c.google.com with SMTP id s4so9725076qkm.13; Fri, 09 Jul 2021 08:59:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WVzaufTKjI7vFE0WAp9ETvQcf722VGc26MQp2yQzB7M=; b=QNblqPWByV8M/v0AKo0T6pJJ59EF6N8LN0xEUrMT7ahzm2W0M0bZtRtpC5JbyjnURT rJMPAvUJMc4lnsYVm5TranAhS3DN06zE9QBqLlkVRb65gDOj1RmwM91jLlvYeDUMmXlr UUmFje7vi+GyrOx38qu+VivsBDrLtOMqaIkNmWYZa9ZhKaCwG0xRw80mkeWs2SLYRSCl u2sZW6rmaUy2OVDoLncDYdyqoM+/p9zkmIrIhGN08d12GZSAsWgMQ/oc0UBCH2BF+ADM 5RuPd47lr4dZXA0sqV/r3v0jfWGj8WVjiVfHvKIkCbV9/EypDxcfV+0v5mMftZvabDTD zhUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WVzaufTKjI7vFE0WAp9ETvQcf722VGc26MQp2yQzB7M=; b=h19+m9fKaQyRtiDC29/ANZBwX5KJ82lnGXYseRQU7q5yk1ZchSdA4FIO4IIgO5kzfD 1yih+0Mq5y2TSOa369OekIJrzinm8txfkUaH+FGCzoQxSC6n56cAveOlfL881fRInVSD ZkyQ7V+NfGu9L/r8ZARnDCfTIKplHHl6KhTCfIZ1LiS7wJCDSiiYz025iML4WixlTpd0 PTq2jAw8LsQEsp2gVA82SgY83vI5h+Blc3USUa603gQ0R6xQcUxYwX3Ouf87+SqR3Uv4 /VD9/FPYPVYpHTEK34sqeP1D3QE60eAv0o7MAO9/umMAueJICv0cMl6CzBViLr5c1O7F /jjA== X-Gm-Message-State: AOAM532SxAmhusFfSePL3BDdtQkKZAaftyftsYVQCAe6MOAX6e6S+eyN a0G2uRE6qA6KuWqzeIz57wk= X-Google-Smtp-Source: ABdhPJxIHLKuMZ4Jq1bbpghyvw/CUGGsf7U6/boIIOdiKSwRr3hN1U1JYfWcBhtjuEBm2EJ+ABTLSA== X-Received: by 2002:a05:620a:e09:: with SMTP id y9mr37864332qkm.359.1625846349604; Fri, 09 Jul 2021 08:59:09 -0700 (PDT) Received: from shaak.xiphos.ca (198-48-202-89.cpe.pppoe.ca. [198.48.202.89]) by smtp.gmail.com with ESMTPSA id x15sm2606071qkm.66.2021.07.09.08.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 08:59:09 -0700 (PDT) From: Liam Beguin To: liambeguin@gmail.com, lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, charles-antoine.couret@essensium.com, Nuno.Sa@analog.com Cc: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Subject: [PATCH v2 2/4] iio: adc: ad7949: fix spi messages on non 14-bit controllers Date: Fri, 9 Jul 2021 11:58:54 -0400 Message-Id: <20210709155856.1732245-3-liambeguin@gmail.com> X-Mailer: git-send-email 2.30.1.489.g328c10930387 In-Reply-To: <20210709155856.1732245-1-liambeguin@gmail.com> References: <20210709155856.1732245-1-liambeguin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Liam Beguin This driver supports devices with 14-bit and 16-bit sample sizes. This is not always handled properly by spi controllers and can fail. To work around this limitation, pad samples to 16-bit and split the sample into two 8-bit messages in the event that only 8-bit messages are supported by the controller. Signed-off-by: Liam Beguin --- drivers/iio/adc/ad7949.c | 69 ++++++++++++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 93aacf4f680b..770112ac820f 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -11,6 +11,7 @@ #include #include #include +#include #define AD7949_MASK_TOTAL GENMASK(13, 0) #define AD7949_CFG_REG_SIZE_BITS 14 @@ -57,6 +58,7 @@ static const struct ad7949_adc_spec ad7949_adc_spec[] = { * @indio_dev: reference to iio structure * @spi: reference to spi structure * @resolution: resolution of the chip + * @bits_per_word: number of bits per SPI word * @cfg: copy of the configuration register * @current_channel: current channel in use * @buffer: buffer to send / receive data to / from device @@ -67,28 +69,60 @@ struct ad7949_adc_chip { struct iio_dev *indio_dev; struct spi_device *spi; u8 resolution; + u8 bits_per_word; u16 cfg; unsigned int current_channel; - u16 buffer ____cacheline_aligned; + union { + __be16 buffer; + u8 buf8[2]; + } ____cacheline_aligned; }; +static void ad7949_set_bits_per_word(struct ad7949_adc_chip *ad7949_adc) +{ + u32 adc_mask = SPI_BPW_MASK(ad7949_adc->resolution); + u32 bpw = adc_mask & ad7949_adc->spi->controller->bits_per_word_mask; + + if (bpw == adc_mask) + ad7949_adc->bits_per_word = ad7949_adc->resolution; + else if (bpw == SPI_BPW_MASK(16)) + ad7949_adc->bits_per_word = 16; + else + ad7949_adc->bits_per_word = 8; +} + static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val, u16 mask) { int ret; - int bits_per_word = ad7949_adc->resolution; - int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS; struct spi_message msg; struct spi_transfer tx[] = { { .tx_buf = &ad7949_adc->buffer, .len = 2, - .bits_per_word = bits_per_word, + .bits_per_word = ad7949_adc->bits_per_word, }, }; + ad7949_adc->buffer = 0; ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask); - ad7949_adc->buffer = ad7949_adc->cfg << shift; + + switch (ad7949_adc->bits_per_word) { + case 16: + ad7949_adc->buffer = ad7949_adc->cfg << 2; + break; + case 14: + ad7949_adc->buffer = ad7949_adc->cfg; + break; + case 8: + default: + /* Pack 14-bit value into 2 bytes, MSB first */ + ad7949_adc->buf8[0] = FIELD_GET(GENMASK(13, 6), ad7949_adc->cfg); + ad7949_adc->buf8[1] = FIELD_GET(GENMASK(5, 0), ad7949_adc->cfg); + ad7949_adc->buf8[1] = ad7949_adc->buf8[1] << 2; + break; + } + spi_message_init_with_transfers(&msg, tx, 1); ret = spi_sync(ad7949_adc->spi, &msg); @@ -105,14 +139,12 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, { int ret; int i; - int bits_per_word = ad7949_adc->resolution; - int mask = GENMASK(ad7949_adc->resolution - 1, 0); struct spi_message msg; struct spi_transfer tx[] = { { .rx_buf = &ad7949_adc->buffer, .len = 2, - .bits_per_word = bits_per_word, + .bits_per_word = ad7949_adc->bits_per_word, }, }; @@ -147,7 +179,25 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, ad7949_adc->current_channel = channel; - *val = ad7949_adc->buffer & mask; + switch (ad7949_adc->bits_per_word) { + case 16: + *val = ad7949_adc->buffer; + /* Shift-out padding bits */ + if (ad7949_adc->resolution == 14) + *val = *val >> 2; + break; + case 14: + *val = ad7949_adc->buffer & GENMASK(13, 0); + break; + case 8: + default: + /* Convert byte array to u16, MSB first */ + *val = (ad7949_adc->buf8[0] << 8) | ad7949_adc->buf8[1]; + /* Shift-out padding bits */ + if (ad7949_adc->resolution == 14) + *val = *val >> 2; + break; + } return 0; } @@ -280,6 +330,7 @@ static int ad7949_spi_probe(struct spi_device *spi) spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data]; indio_dev->num_channels = spec->num_channels; ad7949_adc->resolution = spec->resolution; + ad7949_set_bits_per_word(ad7949_adc); ad7949_adc->vref = devm_regulator_get(dev, "vref"); if (IS_ERR(ad7949_adc->vref)) { From patchwork Fri Jul 9 15:58:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Beguin X-Patchwork-Id: 12367641 X-Patchwork-Delegate: jic23@cam.ac.uk Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA10C11F67 for ; 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[198.48.202.89]) by smtp.gmail.com with ESMTPSA id x15sm2606071qkm.66.2021.07.09.08.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 08:59:10 -0700 (PDT) From: Liam Beguin To: liambeguin@gmail.com, lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, charles-antoine.couret@essensium.com, Nuno.Sa@analog.com Cc: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Subject: [PATCH v2 3/4] iio: adc: ad7949: add support for internal vref Date: Fri, 9 Jul 2021 11:58:55 -0400 Message-Id: <20210709155856.1732245-4-liambeguin@gmail.com> X-Mailer: git-send-email 2.30.1.489.g328c10930387 In-Reply-To: <20210709155856.1732245-1-liambeguin@gmail.com> References: <20210709155856.1732245-1-liambeguin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Liam Beguin Add support for selecting a custom reference voltage from the devicetree. If an external source is used, a vref regulator should be defined in the devicetree. Signed-off-by: Liam Beguin --- drivers/iio/adc/ad7949.c | 94 ++++++++++++++++++++++++++++++++++------ 1 file changed, 80 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 770112ac820f..a20fd81a0830 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -31,6 +31,7 @@ #define AD7949_CFG_VAL_BW_FULL 1 #define AD7949_CFG_VAL_BW_QUARTER 0 #define AD7949_CFG_BIT_REF GENMASK(5, 3) +#define AD7949_CFG_VAL_REF_EXTERNAL BIT(1) #define AD7949_CFG_BIT_SEQ GENMASK(2, 1) #define AD7949_CFG_BIT_RBN BIT(0) @@ -40,6 +41,33 @@ enum { ID_AD7689, }; +/** + * enum ad7949_ref - Reference selection + * + * AD7949_REF_INT_2500: Internal reference and temperature sensor enabled. + * Vref=2.5V, buffered output + * AD7949_REF_INT_4096: Internal reference and temperature sensor enabled. + * Vref=4.096V, buffered output + * AD7949_REF_EXT_TEMP: Use external reference, temperature sensor enabled. + * Internal buffer disabled + * AD7949_REF_EXT_TEMP_BUF: Use external reference, internal buffer and + * temperature sensor enabled. + * AD7949_REF_RSRV_4: Do not use + * AD7949_REF_RSRV_5: Do not use + * AD7949_REF_EXT: Use external reference, internal buffer and + * temperature sensor disabled. + * AD7949_REF_EXT_BUF: Use external reference, internal buffer enabled. + * Internal reference and temperature sensor disabled. + */ +enum ad7949_ref { + AD7949_REF_INT_2500 = 0, + AD7949_REF_INT_4096, + AD7949_REF_EXT_TEMP, + AD7949_REF_EXT_TEMP_BUF, + AD7949_REF_EXT = 6, + AD7949_REF_EXT_BUF, +}; + struct ad7949_adc_spec { u8 num_channels; u8 resolution; @@ -55,6 +83,7 @@ static const struct ad7949_adc_spec ad7949_adc_spec[] = { * struct ad7949_adc_chip - AD ADC chip * @lock: protects write sequences * @vref: regulator generating Vref + * @refsel: reference selection * @indio_dev: reference to iio structure * @spi: reference to spi structure * @resolution: resolution of the chip @@ -66,6 +95,7 @@ static const struct ad7949_adc_spec ad7949_adc_spec[] = { struct ad7949_adc_chip { struct mutex lock; struct regulator *vref; + enum ad7949_ref refsel; struct iio_dev *indio_dev; struct spi_device *spi; u8 resolution; @@ -243,12 +273,28 @@ static int ad7949_spi_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - ret = regulator_get_voltage(ad7949_adc->vref); - if (ret < 0) - return ret; + switch (ad7949_adc->refsel) { + case AD7949_REF_INT_2500: + *val = 2500; + break; + case AD7949_REF_INT_4096: + *val = 4096; + break; + case AD7949_REF_EXT_TEMP: + case AD7949_REF_EXT_TEMP_BUF: + case AD7949_REF_EXT: + case AD7949_REF_EXT_BUF: + ret = regulator_get_voltage(ad7949_adc->vref); + if (ret < 0) + return ret; + + /* convert value back to mV */ + *val = ret / 1000; + break; + } - *val = ret / 5000; - return IIO_VAL_INT; + *val2 = (1 << ad7949_adc->resolution) - 1; + return IIO_VAL_FRACTIONAL; } return -EINVAL; @@ -287,7 +333,7 @@ static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) FIELD_PREP(AD7949_CFG_BIT_INCC, AD7949_CFG_VAL_INCC_UNIPOLAR_GND) | FIELD_PREP(AD7949_CFG_BIT_INX, ad7949_adc->current_channel) | FIELD_PREP(AD7949_CFG_BIT_BW, AD7949_CFG_VAL_BW_FULL) | - FIELD_PREP(AD7949_CFG_BIT_REF, AD7949_REF_EXT_BUF) | + FIELD_PREP(AD7949_CFG_BIT_REF, ad7949_adc->refsel) | FIELD_PREP(AD7949_CFG_BIT_SEQ, 0x0) | FIELD_PREP(AD7949_CFG_BIT_RBN, 1); @@ -306,6 +352,7 @@ static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) static int ad7949_spi_probe(struct spi_device *spi) { struct device *dev = &spi->dev; + struct device_node *np = dev->of_node; const struct ad7949_adc_spec *spec; struct ad7949_adc_chip *ad7949_adc; struct iio_dev *indio_dev; @@ -332,16 +379,35 @@ static int ad7949_spi_probe(struct spi_device *spi) ad7949_adc->resolution = spec->resolution; ad7949_set_bits_per_word(ad7949_adc); - ad7949_adc->vref = devm_regulator_get(dev, "vref"); - if (IS_ERR(ad7949_adc->vref)) { - dev_err(dev, "fail to request regulator\n"); - return PTR_ERR(ad7949_adc->vref); + /* Set default devicetree parameters */ + ad7949_adc->refsel = AD7949_REF_EXT_BUF; + of_property_read_u32(np, "adi,reference-select", &ad7949_adc->refsel); + switch (ad7949_adc->refsel) { + case AD7949_REF_INT_2500: + case AD7949_REF_INT_4096: + case AD7949_REF_EXT_TEMP: + case AD7949_REF_EXT_TEMP_BUF: + case AD7949_REF_EXT: + case AD7949_REF_EXT_BUF: + break; + default: + dev_err(dev, "invalid adi,reference-select value (%d)\n", + ad7949_adc->refsel); + return -EINVAL; } - ret = regulator_enable(ad7949_adc->vref); - if (ret < 0) { - dev_err(dev, "fail to enable regulator\n"); - return ret; + if (ad7949_adc->refsel & AD7949_CFG_VAL_REF_EXTERNAL) { + ad7949_adc->vref = devm_regulator_get(dev, "vref"); + if (IS_ERR(ad7949_adc->vref)) { + dev_err(dev, "fail to request regulator\n"); + return PTR_ERR(ad7949_adc->vref); + } + + ret = regulator_enable(ad7949_adc->vref); + if (ret < 0) { + dev_err(dev, "fail to enable regulator\n"); + return ret; + } } mutex_init(&ad7949_adc->lock); From patchwork Fri Jul 9 15:58:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liam Beguin X-Patchwork-Id: 12367639 X-Patchwork-Delegate: jic23@cam.ac.uk Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86415C07E99 for ; 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[198.48.202.89]) by smtp.gmail.com with ESMTPSA id x15sm2606071qkm.66.2021.07.09.08.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 08:59:11 -0700 (PDT) From: Liam Beguin To: liambeguin@gmail.com, lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, charles-antoine.couret@essensium.com, Nuno.Sa@analog.com Cc: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Subject: [PATCH v2 4/4] dt-bindings: iio: adc: ad7949: add adi,reference-source Date: Fri, 9 Jul 2021 11:58:56 -0400 Message-Id: <20210709155856.1732245-5-liambeguin@gmail.com> X-Mailer: git-send-email 2.30.1.489.g328c10930387 In-Reply-To: <20210709155856.1732245-1-liambeguin@gmail.com> References: <20210709155856.1732245-1-liambeguin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Liam Beguin Add bindings documentation for the adi,reference-source property. This property is required to properly configure the ADC sample request based on which reference source should be used for the calculation. Signed-off-by: Liam Beguin --- .../bindings/iio/adc/adi,ad7949.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7949.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7949.yaml index 9b56bd4d5510..eae3121cad01 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7949.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7949.yaml @@ -35,6 +35,27 @@ properties: "#io-channel-cells": const: 1 + adi,reference-select: + description: | + Select the reference voltage source to use when converting samples. + Acceptable values are: + - 0: Internal reference and temperature sensor enabled. + Vref=2.5V, buffered output + - 1: Internal reference and temperature sensor enabled. + Vref=4.096V, buffered output + - 2: Use external reference, temperature sensor enabled. + Internal buffer disabled + - 3: Use external reference, internal buffer and temperature sensor + enabled. + - 6: Use external reference, internal buffer and temperature sensor + disabled. + - 7: Use external reference, internal buffer enabled. + Internal reference and temperature sensor disabled. + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 6, 7] + default: 7 + required: - compatible - reg