From patchwork Tue Jul 13 12:15:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Kiss X-Patchwork-Id: 12373833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B0D4C07E95 for ; Tue, 13 Jul 2021 12:17:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00EE161249 for ; Tue, 13 Jul 2021 12:17:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00EE161249 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=roJH/aVLdRe88gLYJvMS6SGukV9037oJ6/dftrEGRD0=; b=bd8L/Pajyx80Nc tJh90fpDxWkYUpg0AxMdsyiKWS2EEPXlGdO15mi1aESCAjxrHMuUA3VwKe/YNhyrLZ/MDzynAwdep JnzJ9dyvXrZe9vIHRZNWV3kd3PUZJ16uLcVBKPgBcCzbqINXkVlG17xX5ETPKZafiuQDJeSBnp0c+ LkrQ8NkSasHodA+6IiYymHUm6xc+lErLq61dqXkYPqbA4MSJE+Tl0Lx7NFRky6uPLWufwP9Ix4nt4 PU3p+tsGEaoNZhzd/8UuOFsCt16ZPre4geu4KSj3UZHT/y4f7vNshKgdGA+ewR5+p2uEAD4OjPGly lqqRfiXiKIF5hQz7Txew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKj-00AL1k-SV; Tue, 13 Jul 2021 12:16:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKW-00AKz0-7c for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 12:16:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84A7DD6E; Tue, 13 Jul 2021 05:16:00 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20B823F694; Tue, 13 Jul 2021 05:15:58 -0700 (PDT) From: Daniel Kiss To: coresight@lists.linaro.org Cc: denik@google.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, Daniel Kiss Subject: [PATCHv2 1/4] coresight: tmc-etr: Use handle->head from perf_output_handle directly. Date: Tue, 13 Jul 2021 14:15:29 +0200 Message-Id: <20210713121532.836244-2-daniel.kiss@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713121532.836244-1-daniel.kiss@arm.com> References: <20210713121532.836244-1-daniel.kiss@arm.com> MIME-Version: 1.0 X-ARM-No-Footer: FoSSMail X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_051604_358876_704B9088 X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Polling might call update multiple times and the cached buffer head will be out of sync without advancing it. Using the head directly from the perf_output_handle solves this problem. Signed-off-by: Daniel Kiss --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index acdb59e0e6614..589bb2d56e802 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -32,7 +32,6 @@ struct etr_flat_buf { * @etr_buf - Actual buffer used by the ETR * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode - * @head - handle->head at the beginning of the session. * @nr_pages - Number of pages in the ring buffer. * @pages - Array of Pages in the ring buffer. */ @@ -41,7 +40,6 @@ struct etr_perf_buffer { struct etr_buf *etr_buf; pid_t pid; bool snapshot; - unsigned long head; int nr_pages; void **pages; }; @@ -1436,17 +1434,18 @@ static void tmc_free_etr_buffer(void *config) * tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware * buffer to the perf ring buffer. */ -static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, +static void tmc_etr_sync_perf_buffer(struct perf_output_handle *handle, + struct etr_perf_buffer *etr_perf, unsigned long src_offset, unsigned long to_copy) { long bytes; long pg_idx, pg_offset; - unsigned long head = etr_perf->head; + unsigned long head; char **dst_pages, *src_buf; struct etr_buf *etr_buf = etr_perf->etr_buf; - head = etr_perf->head; + head = PERF_IDX2OFF(handle->head, etr_perf); pg_idx = head >> PAGE_SHIFT; pg_offset = head & (PAGE_SIZE - 1); dst_pages = (char **)etr_perf->pages; @@ -1553,7 +1552,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, /* Insert barrier packets at the beginning, if there was an overflow */ if (lost) tmc_etr_buf_insert_barrier_packet(etr_buf, offset); - tmc_etr_sync_perf_buffer(etr_perf, offset, size); + tmc_etr_sync_perf_buffer(handle, etr_perf, offset, size); /* * In snapshot mode we simply increment the head by the number of byte @@ -1605,8 +1604,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) goto unlock_out; } - etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); - /* * No HW configuration is needed if the sink is already in * use for this session. From patchwork Tue Jul 13 12:15:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Kiss X-Patchwork-Id: 12373835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 182C4C07E95 for ; Tue, 13 Jul 2021 12:18:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D961161249 for ; Tue, 13 Jul 2021 12:18:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D961161249 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iRIwtx9Vx8dFOuAWfHITsLArK001FKnAHpAK4vv2RXQ=; b=MJpwXyPzAVrDv9 smFH48ixqhlti2v+sG0inXO+0T68eO8fVVXQsjMikL6qz/mD8fE98WYrdKtqdT2dCCIVU+JCmmjLK 2swF+jDHKiFIpKlY4behA3QKAZIxzHHNpGEYNOipe9gJudMoRl0XG3UhLjMc7MJ70VGlObT9YHO1N mm5EnPJfSCnvxwebHZvYzKAfmC37SVZnKW83YsHJ1rKoINjfQJ8qYqyLBCleDo4aflFNpMudX3c4+ L0+UrwZDXRDASgvxp5h6K2znW11dNqfkKdcFOpUNqkBLBq1FjvRRxgTkFvgO2CmoY7eagtWBABgr9 pf+w8fEAhNi+mhTCrW4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKu-00AL3A-GW; Tue, 13 Jul 2021 12:16:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKW-00AKzM-VG for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 12:16:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57F911042; Tue, 13 Jul 2021 05:16:02 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C631B3F694; Tue, 13 Jul 2021 05:16:00 -0700 (PDT) From: Daniel Kiss To: coresight@lists.linaro.org Cc: denik@google.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, Daniel Kiss , Branislav Rankov Subject: [PATCHv2 2/4] coresight: tmc-etr: Track perf handler. Date: Tue, 13 Jul 2021 14:15:30 +0200 Message-Id: <20210713121532.836244-3-daniel.kiss@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713121532.836244-1-daniel.kiss@arm.com> References: <20210713121532.836244-1-daniel.kiss@arm.com> MIME-Version: 1.0 X-ARM-No-Footer: FoSSMail X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_051605_092328_FD40888E X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Keep track of the perf handler that is registred by the first tracer. This will be used by the update call from polling. Signed-off-by: Daniel Kiss Signed-off-by: Branislav Rankov --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 589bb2d56e802..55c9b5fd9f832 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1503,8 +1503,8 @@ tmc_update_etr_buffer(struct coresight_device *csdev, spin_lock_irqsave(&drvdata->spinlock, flags); - /* Don't do anything if another tracer is using this sink */ - if (atomic_read(csdev->refcnt) != 1) { + /* Serve only the tracer with the leading perf handler */ + if (drvdata->perf_handle != handle) { spin_unlock_irqrestore(&drvdata->spinlock, flags); goto out; } @@ -1619,6 +1619,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; drvdata->perf_buf = etr_perf->etr_buf; + drvdata->perf_handle = handle; atomic_inc(csdev->refcnt); } @@ -1666,6 +1667,7 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) drvdata->mode = CS_MODE_DISABLED; /* Reset perf specific data */ drvdata->perf_buf = NULL; + drvdata->perf_handle = NULL; spin_unlock_irqrestore(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index b91ec7dde7bc9..81583ffb973dc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -184,6 +184,7 @@ struct etr_buf { * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. + * @perf_handle: PERF handle for ETR. */ struct tmc_drvdata { void __iomem *base; @@ -207,6 +208,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; + struct perf_output_handle *perf_handle; }; struct etr_buf_operations { From patchwork Tue Jul 13 12:15:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Kiss X-Patchwork-Id: 12373837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44665C07E95 for ; Tue, 13 Jul 2021 12:18:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1386861249 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HL5-00AL5F-8e; Tue, 13 Jul 2021 12:16:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKZ-00AKzx-1p for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 12:16:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B7D7106F; Tue, 13 Jul 2021 05:16:04 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 98FDD3F694; Tue, 13 Jul 2021 05:16:02 -0700 (PDT) From: Daniel Kiss To: coresight@lists.linaro.org Cc: denik@google.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, Daniel Kiss , Branislav Rankov Subject: [PATCHv2 3/4] coresight: etm-perf: Export etm_event_cpu_path. Date: Tue, 13 Jul 2021 14:15:31 +0200 Message-Id: <20210713121532.836244-4-daniel.kiss@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713121532.836244-1-daniel.kiss@arm.com> References: <20210713121532.836244-1-daniel.kiss@arm.com> MIME-Version: 1.0 X-ARM-No-Footer: FoSSMail X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_051607_174480_8106E64B X-CRM114-Status: UNSURE ( 9.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Polling need to access the etm_event_cpu_path. Signed-off-by: Daniel Kiss Signed-off-by: Branislav Rankov --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-etm-perf.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 6f398377fec9e..a3f4c07f5bf8b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -117,7 +117,7 @@ etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu) return per_cpu_ptr(data->path, cpu); } -static inline struct list_head * +struct list_head * etm_event_cpu_path(struct etm_event_data *data, int cpu) { return *etm_event_cpu_path_ptr(data, cpu); diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 3e4f2ad5e193d..6d02abbad1b0f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -69,6 +69,7 @@ static inline void *etm_perf_sink_config(struct perf_output_handle *handle) return data->snk_config; return NULL; } +struct list_head *etm_event_cpu_path(struct etm_event_data *data, int cpu); #else static inline int etm_perf_symlink(struct coresight_device *csdev, bool link) { return -EINVAL; } From patchwork Tue Jul 13 12:15:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Kiss X-Patchwork-Id: 12373839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0176C07E95 for ; Tue, 13 Jul 2021 12:18:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 969E9611CB for ; Tue, 13 Jul 2021 12:18:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 969E9611CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=D5fSiHOQq1NyKAAFYGGL0pHELs65BN11VPGqKVl2ciM=; b=fyuy8NLYEKYkBF A5li+faM6SOtNSHiygd163Ba1SRbpY5Yd/MxlUP3LPZmUdk+CC7DNovsIrNmGA3N5pgStQIdumn8k PlhjRk7wnsiMs/IPj1XhssoPrTrQ4Xb4sM2wobaDR+OSwi1bwzybLSnjlXChUBuh9GW3X+3AC2ntH RjQMFmKk3gr4roWOMwqrLXHlEGXJOGscVVkJNRNCn4uIqy1sa6F5K/EzAfQzl2oQpNQUzz2zEihry 31cuyrws32SsILU34/ZDn4qDTmc4mN2MNUqQQIm2t7pzo3pIxEt75lJq3vBkDFpuTRkJ++hC2vaYU 0T4ERiSfdYCREiYKq2Pw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HLH-00AL9K-Om; Tue, 13 Jul 2021 12:16:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3HKZ-00AL0J-M6 for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 12:16:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22CDA1FB; Tue, 13 Jul 2021 05:16:06 -0700 (PDT) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6D8A23F694; Tue, 13 Jul 2021 05:16:04 -0700 (PDT) From: Daniel Kiss To: coresight@lists.linaro.org Cc: denik@google.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, suzuki.poulose@arm.com, Daniel Kiss , Branislav Rankov , Denis Nikitin Subject: [PATCHv2 4/4] coresight: Add ETR-PERF polling. Date: Tue, 13 Jul 2021 14:15:32 +0200 Message-Id: <20210713121532.836244-5-daniel.kiss@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713121532.836244-1-daniel.kiss@arm.com> References: <20210713121532.836244-1-daniel.kiss@arm.com> MIME-Version: 1.0 X-ARM-No-Footer: FoSSMail X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_051607_888883_D8FBB96B X-CRM114-Status: GOOD ( 30.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ETR might fill up the buffer sooner than an event makes perf to trigger the synchronisation especially in system wide trace. Polling runs periodically to sync the ETR buffer. Period is configurable via sysfs, disabled by default. Signed-off-by: Daniel Kiss Signed-off-by: Branislav Rankov Tested-by: Denis Nikitin --- .../testing/sysfs-bus-coresight-devices-tmc | 8 + drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + .../hwtracing/coresight/coresight-etm-perf.c | 8 + .../coresight/coresight-etr-perf-polling.c | 275 ++++++++++++++++++ .../coresight/coresight-etr-perf-polling.h | 38 +++ .../hwtracing/coresight/coresight-tmc-core.c | 4 + .../hwtracing/coresight/coresight-tmc-etr.c | 13 + 8 files changed, 359 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.c create mode 100644 drivers/hwtracing/coresight/coresight-etr-perf-polling.h diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc index 6aa527296c710..3b411e8a6f417 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc @@ -91,3 +91,11 @@ Contact: Mathieu Poirier Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS mode. Writable only for TMC-ETR configurations. The value should be aligned to the kernel pagesize. + +What: /sys/bus/coresight/devices/.tmc/polling/period +Date: July 2021 +KernelVersion: 5.14 +Contact: Daniel Kiss +Description: (RW) Time in milliseconds when the TMC-ETR is synced. + Default value is 0, means the feature is disabled. + Writable only for TMC-ETR configurations. diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 84530fd80998c..4e91fb98849f4 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -44,6 +44,18 @@ config CORESIGHT_LINK_AND_SINK_TMC To compile this driver as a module, choose M here: the module will be called coresight-tmc. + +config CORESIGHT_ETR_PERF_POLL + bool "Coresight ETR Perf Polling" + + depends on CORESIGHT_LINK_AND_SINK_TMC + help + Enable the support for software periodic synchronization of the ETR buffer. + ETR might fill up the buffer sooner than an event makes perf to trigger + the synchronization especially in system wide trace. Polling runs + periodically to sync the ETR buffer. Period is configurable via sysfs, + disabled by default. + config CORESIGHT_CATU tristate "Coresight Address Translation Unit (CATU) driver" depends on CORESIGHT_LINK_AND_SINK_TMC diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index d60816509755c..6baac328eea87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o +coresight-$(CONFIG_CORESIGHT_ETR_PERF_POLL) += coresight-etr-perf-polling.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index a3f4c07f5bf8b..3095840a567c4 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -19,6 +19,7 @@ #include #include "coresight-etm-perf.h" +#include "coresight-etr-perf-polling.h" #include "coresight-priv.h" static struct pmu etm_pmu; @@ -438,6 +439,8 @@ static void etm_event_start(struct perf_event *event, int flags) /* Tell the perf core the event is alive */ event->hw.state = 0; + etr_perf_polling_event_start(event, event_data, handle); + /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; @@ -497,6 +500,8 @@ static void etm_event_stop(struct perf_event *event, int mode) if (!sink) return; + etr_perf_polling_event_stop(event, event_data); + /* stop tracer */ source_ops(csdev)->disable(csdev, event); @@ -741,6 +746,8 @@ int __init etm_perf_init(void) etm_pmu.addr_filters_validate = etm_addr_filters_validate; etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; + etr_perf_polling_init(); + ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); if (ret == 0) etm_perf_up = true; @@ -750,5 +757,6 @@ int __init etm_perf_init(void) void __exit etm_perf_exit(void) { + etr_perf_polling_exit(); perf_pmu_unregister(&etm_pmu); } diff --git a/drivers/hwtracing/coresight/coresight-etr-perf-polling.c b/drivers/hwtracing/coresight/coresight-etr-perf-polling.c new file mode 100644 index 0000000000000..87e6bc42a62de --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etr-perf-polling.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2021 Arm Limited. All rights reserved. + * Author: Daniel Kiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-etr-perf-polling.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +struct polling_event_list { + struct perf_event *perf_event; + struct etm_event_data *etm_event_data; + struct perf_output_handle *ctx_handle; + void (*tmc_etr_reset_hw)(struct tmc_drvdata *data); + struct list_head list; +}; + +struct polling { + int cpu; + struct polling_event_list *polled_event; + struct delayed_work delayed_work; +}; + +static atomic_t period; +static spinlock_t spinlock_re; +static struct list_head registered_events; + +static DEFINE_PER_CPU(struct polling, polling); + +static ssize_t period_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int temp; + + temp = atomic_read(&period); + return sprintf(buf, "%i\n", temp); +} + +static ssize_t period_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int temp = 0; + + if (!kstrtoint(buf, 10, &temp) && (temp >= 0)) + atomic_set(&period, temp); + return count; +} + +static DEVICE_ATTR_RW(period); + +static struct attribute *coresight_tmc_polling_attrs[] = { + &dev_attr_period.attr, + NULL, +}; +const struct attribute_group coresight_tmc_polling_group = { + .attrs = coresight_tmc_polling_attrs, + .name = "polling", +}; +EXPORT_SYMBOL_GPL(coresight_tmc_polling_group); + +static inline void polling_sched_worker(struct polling *p) +{ + int tickrate = atomic_read(&period); + + if (tickrate > 0) + schedule_delayed_work_on(p->cpu, &p->delayed_work, + msecs_to_jiffies(tickrate)); +} + +static inline bool is_etr_related(struct etm_event_data *etm_event_data, int cpu) +{ + struct list_head *path; + struct coresight_device *sink; + struct tmc_drvdata *drvdata; + + path = etm_event_cpu_path(etm_event_data, cpu); + if (WARN_ON(!path)) + return false; + sink = coresight_get_sink(path); + if (WARN_ON(!sink)) + return false; + drvdata = dev_get_drvdata(sink->dev.parent); + if (drvdata->config_type != TMC_CONFIG_TYPE_ETR) + return false; + return true; +} + +/* + * Adds the event to the polled events list. + */ +void etr_perf_polling_event_start(struct perf_event *event, + struct etm_event_data *etm_event_data, + struct perf_output_handle *ctx_handle) +{ + int cpu = smp_processor_id(); + struct polling *p = per_cpu_ptr(&polling, cpu); + struct polling_event_list *element, *tmp; + + if (!is_etr_related(etm_event_data, cpu)) + return; + + spin_lock(&spinlock_re); + list_for_each_entry_safe(element, tmp, ®istered_events, list) { + if (element->ctx_handle == ctx_handle) { + element->perf_event = event; + element->etm_event_data = etm_event_data; + spin_unlock(&spinlock_re); + p->polled_event = element; + polling_sched_worker(p); + return; + } + } + spin_unlock(&spinlock_re); +} + +/* + * Removes the event from the to be polled events list. + */ +void etr_perf_polling_event_stop(struct perf_event *event, + struct etm_event_data *etm_event_data) +{ + int cpu = smp_processor_id(); + struct polling *p = per_cpu_ptr(&polling, cpu); + + if (!is_etr_related(etm_event_data, cpu)) + return; + + if (p->polled_event) { + struct polling_event_list *element = p->polled_event; + + if (element->perf_event == event) { + p->polled_event = NULL; + element->perf_event = NULL; + element->etm_event_data = NULL; + cancel_delayed_work(&p->delayed_work); + return; + } + } +} + +/* + * The polling worker is a workqueue job which is periodically + * woken up to update the perf aux buffer from the etr shrink. + */ +static void etr_perf_polling_worker(struct work_struct *work) +{ + unsigned long flags; + struct list_head *path; + struct coresight_device *sink; + int size; + int cpu = smp_processor_id(); + struct polling *p = per_cpu_ptr(&polling, cpu); + + if (!atomic_read(&period)) + return; + + if (!p->polled_event) + return; + /* + * Scheduling would do the same from the perf hooks, + * this should be done in one go. + */ + local_irq_save(flags); + + polling_sched_worker(p); + + path = etm_event_cpu_path(p->polled_event->etm_event_data, cpu); + sink = coresight_get_sink(path); + size = sink_ops(sink)->update_buffer( + sink, p->polled_event->ctx_handle, + p->polled_event->etm_event_data->snk_config); + + /* + * Restart the trace. + */ + if (p->polled_event->tmc_etr_reset_hw) + p->polled_event->tmc_etr_reset_hw(dev_get_drvdata(sink->dev.parent)); + + WARN_ON(size < 0); + if (size > 0) { + struct etm_event_data *new_event_data; + + perf_aux_output_end(p->polled_event->ctx_handle, size); + new_event_data = perf_aux_output_begin( + p->polled_event->ctx_handle, + p->polled_event->perf_event); + if (WARN_ON(new_event_data == NULL)) { + local_irq_restore(flags); + return; + } + + p->polled_event->etm_event_data = new_event_data; + WARN_ON(new_event_data->snk_config != + p->polled_event->etm_event_data->snk_config); + } + + local_irq_restore(flags); +} + +void etr_perf_polling_handle_register(struct perf_output_handle *handle, + void (*tmc_etr_reset_hw)(struct tmc_drvdata *drvdata)) +{ + struct polling_event_list *element; + + element = kmalloc(sizeof(*element), GFP_ATOMIC); + if (WARN_ON(!element)) + return; + memset(element, 0, sizeof(*element)); + element->ctx_handle = handle; + element->tmc_etr_reset_hw = tmc_etr_reset_hw; + spin_lock(&spinlock_re); + list_add(&element->list, ®istered_events); + spin_unlock(&spinlock_re); +} +EXPORT_SYMBOL_GPL(etr_perf_polling_handle_register); + +void etr_perf_polling_handle_deregister(struct perf_output_handle *handle) +{ + struct polling_event_list *element, *tmp; + + spin_lock(&spinlock_re); + list_for_each_entry_safe(element, tmp, ®istered_events, list) { + if (element->ctx_handle == handle) { + list_del(&element->list); + spin_unlock(&spinlock_re); + kfree(element); + return; + } + } + spin_unlock(&spinlock_re); +} +EXPORT_SYMBOL_GPL(etr_perf_polling_handle_deregister); + +void etr_perf_polling_init(void) +{ + int cpu; + + spin_lock_init(&spinlock_re); + INIT_LIST_HEAD(®istered_events); + atomic_set(&period, 0); + for_each_possible_cpu(cpu) { + struct polling *p = per_cpu_ptr(&polling, cpu); + + p->cpu = cpu; + p->polled_event = NULL; + INIT_DELAYED_WORK(&p->delayed_work, etr_perf_polling_worker); + } +} + +void etr_perf_polling_exit(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + struct polling *p = per_cpu_ptr(&polling, cpu); + + cancel_delayed_work_sync(&p->delayed_work); + WARN_ON(p->polled_event); + } + WARN_ON(!list_empty(®istered_events)); +} diff --git a/drivers/hwtracing/coresight/coresight-etr-perf-polling.h b/drivers/hwtracing/coresight/coresight-etr-perf-polling.h new file mode 100644 index 0000000000000..d47b4424594e6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etr-perf-polling.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2021 Arm Limited. All rights reserved. + * Author: Daniel Kiss + */ + +#ifndef _CORESIGHT_ETM_PERF_POLLING_H +#define _CORESIGHT_ETM_PERF_POLLING_H + +#include +#include +#include "coresight-etm-perf.h" +#include "coresight-tmc.h" + +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL +void etr_perf_polling_init(void); +void etr_perf_polling_exit(void); +void etr_perf_polling_handle_register(struct perf_output_handle *handle, + void (*tmc_etr_reset_hw)(struct tmc_drvdata *drvdata)); +void etr_perf_polling_handle_deregister(struct perf_output_handle *handle); +void etr_perf_polling_event_start(struct perf_event *event, + struct etm_event_data *etm_event_data, + struct perf_output_handle *ctx_handle); +void etr_perf_polling_event_stop(struct perf_event *event, + struct etm_event_data *etm_event_data); + +extern const struct attribute_group coresight_tmc_polling_group; + +#else /* !CONFIG_CORESIGHT_ETR_PERF_POLL */ +#define etr_perf_polling_init() +#define etr_perf_polling_exit() +#define etr_perf_polling_handle_register(...) +#define etr_perf_polling_handle_deregister(...) +#define etr_perf_polling_event_start(...) +#define etr_perf_polling_event_stop(...) +#endif + +#endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 74c6323d4d6ab..dbcdba162bd38 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -26,6 +26,7 @@ #include "coresight-priv.h" #include "coresight-tmc.h" +#include "coresight-etr-perf-polling.h" DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); @@ -365,6 +366,9 @@ static const struct attribute_group coresight_tmc_mgmt_group = { static const struct attribute_group *coresight_tmc_groups[] = { &coresight_tmc_group, &coresight_tmc_mgmt_group, +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL + &coresight_tmc_polling_group, +#endif NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 55c9b5fd9f832..67cd4bdcda71b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -16,6 +16,7 @@ #include #include "coresight-catu.h" #include "coresight-etm-perf.h" +#include "coresight-etr-perf-polling.h" #include "coresight-priv.h" #include "coresight-tmc.h" @@ -1137,6 +1138,16 @@ void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) drvdata->etr_buf = NULL; } +#ifdef CONFIG_CORESIGHT_ETR_PERF_POLL + +static void tmc_etr_reset_hw(struct tmc_drvdata *drvdata) +{ + __tmc_etr_disable_hw(drvdata); + __tmc_etr_enable_hw(drvdata); +} + +#endif + static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) { int ret = 0; @@ -1620,6 +1631,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) drvdata->mode = CS_MODE_PERF; drvdata->perf_buf = etr_perf->etr_buf; drvdata->perf_handle = handle; + etr_perf_polling_handle_register(handle, tmc_etr_reset_hw); atomic_inc(csdev->refcnt); } @@ -1667,6 +1679,7 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) drvdata->mode = CS_MODE_DISABLED; /* Reset perf specific data */ drvdata->perf_buf = NULL; + etr_perf_polling_handle_deregister(drvdata->perf_handle); drvdata->perf_handle = NULL; spin_unlock_irqrestore(&drvdata->spinlock, flags);