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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=mJmAFKfe0HV6pIVB6fzO73d9LrEJr3yyqntgfqOc6CI=; b=c2PO7BkZ/dATL19n9sjuIYY64azbXUfJsvR4XitDyQaxREYVUWUAVbuL4mljwbYVbQ +fu/nu8g1zmQVuJ2mlkZumgrrNFunTxpHbqqa0/i4ur/TfEb6QAzL1qShSUekWMFvX5p uGwADROGJA9nS3py34zDL2d4ueeI6HuLQcEzcaKWsuFNXcuMuzF2iVBXldjea5s9ukDT bxqUlXrOdcpr+D/QMr9MNOLK0HrVLjvKgY17pmLmFbQSSw4N5+vhuHHNWRcNRuklH6yZ J19XHQw3A/JERSIldzaLExw+7R8I5oAy53kqrgX5XPwAQMuj0rCIuBaTvOFGT7LCxt/0 Z4Ew== X-Gm-Message-State: AOAM530sc8SOZAV25Jtov/F2e8OAUeyIGY/5d+73LvN8V7itD2qMDcJf 2T0G7qKHRXbCpITUqEOuh3APhJA= X-Google-Smtp-Source: ABdhPJzx5OtFhisCMvJcH27Twpe+gvW+zeBCxP0/5PLwDGmUP0dDXGQLOx5SFVA6/BBO6ab9O4wfkdg= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:99b9:48f7:dbe6:8670]) (user=pcc job=sendgmr) by 2002:a25:1ec4:: with SMTP id e187mr9543332ybe.425.1626226594380; Tue, 13 Jul 2021 18:36:34 -0700 (PDT) Date: Tue, 13 Jul 2021 18:36:31 -0700 Message-Id: <20210714013631.3994485-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH] arm64: avoid double ISB on kernel entry From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_183636_440665_34F67EE5 X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Although an ISB is required in order to make the MTE-related system register update to GCR_EL1 effective, and the same is true for PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two ISBs on machines that support both features while we only need to issue one. To avoid the unnecessary additional ISB, remove the ISBs from the PAC and MTE-specific alternative blocks and add a couple of additional blocks that cause us to only execute one ISB if both features are supported. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/Idee7e8114d5ae5a0b171d06220a0eb4bb015a51c --- arch/arm64/kernel/entry.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 2d6dc62d929a..cdff7abd27a9 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -191,7 +191,6 @@ alternative_else_nop_endif ldr_l \tmp, gcr_kernel_excl mte_set_gcr \tmp, \tmp2 - isb 1: #endif .endm @@ -265,12 +264,24 @@ alternative_if ARM64_HAS_ADDRESS_AUTH orr x0, x0, SCTLR_ELx_ENIA msr sctlr_el1, x0 2: - isb alternative_else_nop_endif #endif mte_set_kernel_gcr x22, x23 + /* + * Any non-self-synchronizing system register updates required for + * kernel entry should be placed before this point. + */ + alternative_if ARM64_MTE + isb + b 1f + alternative_else_nop_endif + alternative_if ARM64_HAS_ADDRESS_AUTH + isb + alternative_else_nop_endif +1: + scs_load tsk, x20 .else add x21, sp, #PT_REGS_SIZE