From patchwork Thu Jul 15 11:36:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoniu Miclaus X-Patchwork-Id: 12379873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86F6EC07E96 for ; Thu, 15 Jul 2021 11:42:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 692E0613BC for ; Thu, 15 Jul 2021 11:42:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229516AbhGOLpp (ORCPT ); Thu, 15 Jul 2021 07:45:45 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:58234 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229506AbhGOLpp (ORCPT ); Thu, 15 Jul 2021 07:45:45 -0400 Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16FBajgx010870; Thu, 15 Jul 2021 07:42:51 -0400 Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com with ESMTP id 39tjcarbbp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jul 2021 07:42:51 -0400 Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 16FBgoCQ023262 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Jul 2021 07:42:50 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.5; Thu, 15 Jul 2021 07:42:49 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.858.5 via Frontend Transport; Thu, 15 Jul 2021 07:42:49 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.134]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 16FBglsO004227; Thu, 15 Jul 2021 07:42:48 -0400 From: Antoniu Miclaus To: , , , CC: Antoniu Miclaus Subject: [PATCH v5 1/2] iio: frequency: adrf6780: add support for ADRF6780 Date: Thu, 15 Jul 2021 14:36:44 +0300 Message-ID: <20210715113645.44851-1-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: lB6sRZFFQktcNPOBykOUsZDNLI4f5rUT X-Proofpoint-GUID: lB6sRZFFQktcNPOBykOUsZDNLI4f5rUT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-15_07:2021-07-14,2021-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107150084 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The ADRF6780 is a silicon germanium (SiGe) design, wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADRF6780.pdf Signed-off-by: Antoniu Miclaus Reported-by: kernel test robot --- changes in v5: - drop `depends on OF` - include `linux/mod_devicetable.h` - use FIELD_GET/FIELD_PREP inline - use dma safe buffers - use `get_unaligned_be24()` and `put_unaligned_be24()` where needed - use `if (ret)` instead of `if (ret < 0)` - remove locked version of `adrf6780_spi_update_bits` - add `adrf6780_read_voltage_raw` - use switch statements for `IIO_MOD` - other minor fixes drivers/iio/frequency/Kconfig | 12 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/adrf6780.c | 474 +++++++++++++++++++++++++++++++ 3 files changed, 487 insertions(+) create mode 100644 drivers/iio/frequency/adrf6780.c diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 240b81502512..2c9e0559e8a4 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -49,5 +49,17 @@ config ADF4371 To compile this driver as a module, choose M here: the module will be called adf4371. + +config ADRF6780 + tristate "Analog Devices ADRF6780 Microwave Upconverter" + depends on SPI + depends on COMMON_CLK + help + Say yes here to build support for Analog Devices ADRF6780 + 5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter. + + To compile this driver as a module, choose M here: the + module will be called adrf6780. + endmenu endmenu diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 518b1e50caef..ae3136c79202 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_AD9523) += ad9523.o obj-$(CONFIG_ADF4350) += adf4350.o obj-$(CONFIG_ADF4371) += adf4371.o +obj-$(CONFIG_ADRF6780) += adrf6780.o diff --git a/drivers/iio/frequency/adrf6780.c b/drivers/iio/frequency/adrf6780.c new file mode 100644 index 000000000000..7583360cb555 --- /dev/null +++ b/drivers/iio/frequency/adrf6780.c @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ADRF6780 driver + * + * Copyright 2021 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* ADRF6780 Register Map */ +#define ADRF6780_REG_CONTROL 0x00 +#define ADRF6780_REG_ALARM_READBACK 0x01 +#define ADRF6780_REG_ALARM_MASKS 0x02 +#define ADRF6780_REG_ENABLE 0x03 +#define ADRF6780_REG_LINEARIZE 0x04 +#define ADRF6780_REG_LO_PATH 0x05 +#define ADRF6780_REG_ADC_CONTROL 0x06 +#define ADRF6780_REG_ADC_OUTPUT 0x0C + +/* ADRF6780_REG_CONTROL Map */ +#define ADRF6780_PARITY_EN_MSK BIT(15) +#define ADRF6780_SOFT_RESET_MSK BIT(14) +#define ADRF6780_CHIP_ID_MSK GENMASK(11, 4) +#define ADRF6780_CHIP_ID 0xA +#define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0) + +/* ADRF6780_REG_ALARM_READBACK Map */ +#define ADRF6780_PARITY_ERROR_MSK BIT(15) +#define ADRF6780_TOO_FEW_ERRORS_MSK BIT(14) +#define ADRF6780_TOO_MANY_ERRORS_MSK BIT(13) +#define ADRF6780_ADDRESS_RANGE_ERROR_MSK BIT(12) + +/* ADRF6780_REG_ENABLE Map */ +#define ADRF6780_VGA_BUFFER_EN_MSK BIT(8) +#define ADRF6780_DETECTOR_EN_MSK BIT(7) +#define ADRF6780_LO_BUFFER_EN_MSK BIT(6) +#define ADRF6780_IF_MODE_EN_MSK BIT(5) +#define ADRF6780_IQ_MODE_EN_MSK BIT(4) +#define ADRF6780_LO_X2_EN_MSK BIT(3) +#define ADRF6780_LO_PPF_EN_MSK BIT(2) +#define ADRF6780_LO_EN_MSK BIT(1) +#define ADRF6780_UC_BIAS_EN_MSK BIT(0) + +/* ADRF6780_REG_LINEARIZE Map */ +#define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0) + +/* ADRF6780_REG_LO_PATH Map */ +#define ADRF6780_LO_SIDEBAND_MSK BIT(10) +#define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4) +#define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0) + +/* ADRF6780_REG_ADC_CONTROL Map */ +#define ADRF6780_VDET_OUTPUT_SELECT_MSK BIT(3) +#define ADRF6780_ADC_START_MSK BIT(2) +#define ADRF6780_ADC_EN_MSK BIT(1) +#define ADRF6780_ADC_CLOCK_EN_MSK BIT(0) + +/* ADRF6780_REG_ADC_OUTPUT Map */ +#define ADRF6780_ADC_STATUS_MSK BIT(8) +#define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0) + +struct adrf6780_dev { + struct spi_device *spi; + struct clk *clkin; + /* Protect against concurrent accesses to the device */ + struct mutex lock; + bool vga_buff_en; + bool lo_buff_en; + bool if_mode_en; + bool iq_mode_en; + bool lo_x2_en; + bool lo_ppf_en; + bool lo_en; + bool uc_bias_en; + bool lo_sideband; + bool vdet_out_en; + u8 data[3] ____cacheline_aligned; +}; + +static int adrf6780_spi_read(struct adrf6780_dev *dev, unsigned int reg, + unsigned int *val) +{ + int ret; + struct spi_transfer t = {0}; + + dev->data[0] = 0x80 | (reg << 1); + dev->data[1] = 0x0; + dev->data[2] = 0x0; + + t.rx_buf = &dev->data[0]; + t.tx_buf = &dev->data[0]; + t.len = 3; + + ret = spi_sync_transfer(dev->spi, &t, 1); + if (ret) + return ret; + + *val = (get_unaligned_be24(&dev->data[0]) >> 1) & GENMASK(15, 0); + + return ret; +} + +static int adrf6780_spi_write(struct adrf6780_dev *dev, + unsigned int reg, + unsigned int val) +{ + put_unaligned_be24((val << 1) | (reg << 17), &dev->data[0]); + + return spi_write(dev->spi, &dev->data[0], 3); +} + +static int adrf6780_spi_update_bits(struct adrf6780_dev *dev, unsigned int reg, + unsigned int mask, unsigned int val) +{ + int ret; + unsigned int data, temp; + + ret = adrf6780_spi_read(dev, reg, &data); + if (ret) + return ret; + + temp = (data & ~mask) | (val & mask); + + return adrf6780_spi_write(dev, reg, temp); +} + +static int adrf6780_read_voltage_raw(struct adrf6780_dev *dev, unsigned int read_val) +{ + int ret; + + mutex_lock(&dev->lock); + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_ADC_CONTROL, + ADRF6780_ADC_EN_MSK | + ADRF6780_ADC_CLOCK_EN_MSK | + ADRF6780_ADC_START_MSK, + FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) | + FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) | + FIELD_PREP(ADRF6780_ADC_START_MSK, 1)); + if (ret) + goto exit; + + usleep_range(200, 250); + + ret = adrf6780_spi_read(dev, ADRF6780_REG_ADC_OUTPUT, &read_val); + if (ret) + goto exit; + + if (!(read_val & ADRF6780_ADC_STATUS_MSK)) { + ret = -EINVAL; + goto exit; + } + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_ADC_CONTROL, + ADRF6780_ADC_START_MSK, + FIELD_PREP(ADRF6780_ADC_START_MSK, 0)); + if (ret) + goto exit; + + ret = adrf6780_spi_read(dev, ADRF6780_REG_ADC_OUTPUT, &read_val); + +exit: + mutex_unlock(&dev->lock); + return ret; +} + +static int adrf6780_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct adrf6780_dev *dev = iio_priv(indio_dev); + unsigned int data; + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + ret = adrf6780_read_voltage_raw(dev, data); + if (ret) + return ret; + + *val = data & ADRF6780_ADC_VALUE_MSK; + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data); + if (ret) + return ret; + + *val = data & ADRF6780_RDAC_LINEARIZE_MSK; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_PHASE: + ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data); + if (ret) + return ret; + + switch (chan->channel2) { + case IIO_MOD_I: + *val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK; + + return IIO_VAL_INT; + case IIO_MOD_Q: + *val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, data); + + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int adrf6780_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct adrf6780_dev *dev = iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_CHAN_INFO_SCALE: + return adrf6780_spi_write(dev, ADRF6780_REG_LINEARIZE, val); + case IIO_CHAN_INFO_PHASE: + switch (chan->channel2) { + case IIO_MOD_I: + mutex_lock(&dev->lock); + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_LO_PATH, + ADRF6780_I_PATH_PHASE_ACCURACY_MSK, + FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val)); + mutex_unlock(&dev->lock); + + return ret; + case IIO_MOD_Q: + mutex_lock(&dev->lock); + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_LO_PATH, + ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, + FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val)); + mutex_unlock(&dev->lock); + + return ret; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int adrf6780_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int write_val, + unsigned int *read_val) +{ + struct adrf6780_dev *dev = iio_priv(indio_dev); + + if (read_val) + return adrf6780_spi_read(dev, reg, read_val); + else + return adrf6780_spi_write(dev, reg, write_val); +} + +static const struct iio_info adrf6780_info = { + .read_raw = adrf6780_read_raw, + .write_raw = adrf6780_write_raw, + .debugfs_reg_access = &adrf6780_reg_access, +}; + +#define ADRF6780_CHAN(_channel) { \ + .type = IIO_VOLTAGE, \ + .output = 1, \ + .indexed = 1, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) \ +} + +#define ADRF6780_CHAN_IQ(_channel, rf_comp) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 1, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) \ +} + +static const struct iio_chan_spec adrf6780_channels[] = { + ADRF6780_CHAN(0), + ADRF6780_CHAN_IQ(0, I), + ADRF6780_CHAN_IQ(0, Q), +}; + +static int adrf6780_reset(struct adrf6780_dev *dev) +{ + int ret; + struct spi_device *spi = dev->spi; + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_CONTROL, + ADRF6780_SOFT_RESET_MSK, + FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1)); + if (ret) { + dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n"); + return ret; + } + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_CONTROL, + ADRF6780_SOFT_RESET_MSK, + FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0)); + if (ret) { + dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n"); + return ret; + } + + return 0; +} + +static int adrf6780_init(struct adrf6780_dev *dev) +{ + int ret; + unsigned int chip_id, enable_reg, enable_reg_msk; + struct spi_device *spi = dev->spi; + + /* Perform a software reset */ + ret = adrf6780_reset(dev); + if (ret) + return ret; + + ret = adrf6780_spi_read(dev, ADRF6780_REG_CONTROL, &chip_id); + if (ret) + return ret; + + chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id); + if (chip_id != ADRF6780_CHIP_ID) { + dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n"); + return -EINVAL; + } + + enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK | + ADRF6780_DETECTOR_EN_MSK | + ADRF6780_LO_BUFFER_EN_MSK | + ADRF6780_IF_MODE_EN_MSK | + ADRF6780_IQ_MODE_EN_MSK | + ADRF6780_LO_X2_EN_MSK | + ADRF6780_LO_PPF_EN_MSK | + ADRF6780_LO_EN_MSK | + ADRF6780_UC_BIAS_EN_MSK; + + enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, dev->vga_buff_en) | + FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) | + FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, dev->lo_buff_en) | + FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, dev->if_mode_en) | + FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, dev->iq_mode_en) | + FIELD_PREP(ADRF6780_LO_X2_EN_MSK, dev->lo_x2_en) | + FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, dev->lo_ppf_en) | + FIELD_PREP(ADRF6780_LO_EN_MSK, dev->lo_en) | + FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, dev->uc_bias_en); + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_ENABLE, enable_reg_msk, enable_reg); + if (ret) + return ret; + + ret = adrf6780_spi_update_bits(dev, ADRF6780_REG_LO_PATH, + ADRF6780_LO_SIDEBAND_MSK, + FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, dev->lo_sideband)); + if (ret) + return ret; + + return adrf6780_spi_update_bits(dev, ADRF6780_REG_ADC_CONTROL, + ADRF6780_VDET_OUTPUT_SELECT_MSK, + FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, dev->vdet_out_en)); +} + +static void adrf6780_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static void adrf6780_dt_parse(struct adrf6780_dev *dev) +{ + struct spi_device *spi = dev->spi; + + dev->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en"); + dev->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en"); + dev->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en"); + dev->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en"); + dev->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en"); + dev->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en"); + dev->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en"); + dev->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en"); + dev->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband"); + dev->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en"); +} + +static int adrf6780_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct adrf6780_dev *dev; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dev)); + if (!indio_dev) + return -ENOMEM; + + dev = iio_priv(indio_dev); + + indio_dev->info = &adrf6780_info; + indio_dev->name = "adrf6780"; + indio_dev->channels = adrf6780_channels; + indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels); + + dev->spi = spi; + + adrf6780_dt_parse(dev); + + dev->clkin = devm_clk_get(&spi->dev, "lo_in"); + if (IS_ERR(dev->clkin)) + return PTR_ERR(dev->clkin); + + ret = clk_prepare_enable(dev->clkin); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, adrf6780_clk_disable, dev->clkin); + if (ret < 0) + return ret; + + mutex_init(&dev->lock); + + ret = adrf6780_init(dev); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id adrf6780_id[] = { + { "adrf6780", 0 }, + {} +}; +MODULE_DEVICE_TABLE(spi, adrf6780_id); + +static const struct of_device_id adrf6780_of_match[] = { + { .compatible = "adi,adrf6780" }, + {} +}; +MODULE_DEVICE_TABLE(of, adrf6780_of_match); + +static struct spi_driver adrf6780_driver = { + .driver = { + .name = "adrf6780", + .of_match_table = adrf6780_of_match, + }, + .probe = adrf6780_probe, + .id_table = adrf6780_id, +}; +module_spi_driver(adrf6780_driver); + +MODULE_AUTHOR("Antoniu Miclaus X-Patchwork-Id: 12379875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 670A6C47E4D for ; Thu, 15 Jul 2021 11:42:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F51461260 for ; Thu, 15 Jul 2021 11:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229673AbhGOLps (ORCPT ); Thu, 15 Jul 2021 07:45:48 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:63164 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229506AbhGOLps (ORCPT ); Thu, 15 Jul 2021 07:45:48 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16FBa1u3011560; Thu, 15 Jul 2021 07:42:54 -0400 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 39smkepdeg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jul 2021 07:42:54 -0400 Received: from SCSQMBX11.ad.analog.com (SCSQMBX11.ad.analog.com [10.77.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 16FBgqEW002973 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 15 Jul 2021 07:42:53 -0400 Received: from SCSQMBX10.ad.analog.com (10.77.17.5) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.5; Thu, 15 Jul 2021 04:42:51 -0700 Received: from zeus.spd.analog.com (10.66.68.11) by scsqmbx10.ad.analog.com (10.77.17.5) with Microsoft SMTP Server id 15.2.858.5 via Frontend Transport; Thu, 15 Jul 2021 04:42:51 -0700 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.134]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 16FBglsP004227; Thu, 15 Jul 2021 07:42:49 -0400 From: Antoniu Miclaus To: , , , CC: Antoniu Miclaus , Rob Herring Subject: [PATCH v5 2/2] dt-bindings: iio: frequency: add adrf6780 doc Date: Thu, 15 Jul 2021 14:36:45 +0300 Message-ID: <20210715113645.44851-2-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210715113645.44851-1-antoniu.miclaus@analog.com> References: <20210715113645.44851-1-antoniu.miclaus@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: gsAaeQGpMtAfDPeu14GPFUZk9sv6GJjA X-Proofpoint-ORIG-GUID: gsAaeQGpMtAfDPeu14GPFUZk9sv6GJjA X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-15_07:2021-07-14,2021-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1011 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107150084 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add device tree bindings for the ADRF6780 Upconverter. Reviewed-by: Rob Herring Signed-off-by: Antoniu Miclaus --- .../bindings/iio/frequency/adi,adrf6780.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adrf6780.yaml diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adrf6780.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adrf6780.yaml new file mode 100644 index 000000000000..65cb3bee4aca --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adrf6780.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADRF6780 Microwave Upconverter + +maintainers: + - Antoniu Miclaus + +description: | + Wideband, microwave upconverter optimized for point to point microwave + radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. + + https://www.analog.com/en/products/adrf6780.html + +properties: + compatible: + enum: + - adi,adrf6780 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + + clocks: + description: + Definition of the external clock. + minItems: 1 + + clock-names: + items: + - const: lo_in + + clock-output-names: + maxItems: 1 + + adi,vga-buff-en: + description: + VGA Buffer Enable. + type: boolean + + adi,lo-buff-en: + description: + LO Buffer Enable. + type: boolean + + adi,if-mode-en: + description: + IF Mode Enable. + type: boolean + + adi,iq-mode-en: + description: + IQ Mode Enable. + type: boolean + + adi,lo-x2-en: + description: + LO x2 Enable. + type: boolean + + adi,lo-ppf-en: + description: + LO x1 Enable. + type: boolean + + adi,lo-en: + description: + LO Enable. + type: boolean + + adi,uc-bias-en: + description: + UC Bias Enable. + type: boolean + + adi,lo-sideband: + description: + Switch to the Other LO Sideband. + type: boolean + + adi,vdet-out-en: + description: + VDET Output Select Enable. + type: boolean + + '#clock-cells': + const: 0 + +dependencies: + adi,lo-x2-en: [ "adi,lo-en" ] + adi,lo-ppf-en: [ "adi,lo-en" ] + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + adrf6780@0 { + compatible = "adi,adrf6780"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adrf6780_lo>; + clock-names = "lo_in"; + }; + }; +...