From patchwork Mon Jul 19 23:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Almahallawy, Khaled" X-Patchwork-Id: 12387127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67258C07E95 for ; Mon, 19 Jul 2021 23:54:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B90D61107 for ; Mon, 19 Jul 2021 23:54:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B90D61107 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA43589C9A; Mon, 19 Jul 2021 23:54:58 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 33FA789C9A for ; Mon, 19 Jul 2021 23:54:57 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10050"; a="232927935" X-IronPort-AV: E=Sophos;i="5.84,253,1620716400"; d="scan'208";a="232927935" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2021 16:54:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,253,1620716400"; d="scan'208";a="575608798" Received: from kialmah1-desk.jf.intel.com ([10.23.15.164]) by fmsmga001.fm.intel.com with ESMTP; 19 Jul 2021 16:54:56 -0700 From: Khaled Almahallawy To: intel-gfx@lists.freedesktop.org Date: Mon, 19 Jul 2021 16:59:27 -0700 Message-Id: <20210719235927.283173-1-khaled.almahallawy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Add missing TPS4 programming bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to Specs:50484). TPS4 is CP2520 Pattern 3 (refer to DP2.0 spaces Table 3-11, DPCD 00248h LINK_QUAL_PATTERN_SELECT, and DP PHY 1.4 CTS - Appendix A - Compliance EYE Pattern(CP2520; Normative)) For TPS4, setting bits 20:19 to value != 00b, leads to a non-TPS4 pattern. This is confirmed using DP Scope running DP1.4 PHY CTS. To avoid any accidental wrong setting of bits 20:19, set it correctly for TPS4 LT pattern selection. This programming sequence is the same used by EV. Cc: Manasi Navare Cc: Ville Syrjälä CC: José Roberto de Souza Cc: Imre Deak Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 26a3aa73fcc4..54b4b28fdc74 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3412,6 +3412,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, break; case DP_TRAINING_PATTERN_4: temp |= DP_TP_CTL_LINK_TRAIN_PAT4; + temp &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + temp |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; break; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..a65998df9994 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10176,6 +10176,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)