From patchwork Fri Jul 23 07:05:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B1FC4338F for ; Fri, 23 Jul 2021 06:58:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A865960EAF for ; Fri, 23 Jul 2021 06:58:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A865960EAF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CAB46FA4B; Fri, 23 Jul 2021 06:58:36 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE0886FA49 for ; Fri, 23 Jul 2021 06:58:32 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829753" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829753" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405576" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:31 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:42 +0800 Message-Id: <20210723070548.29315-2-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Transfer "gpio_nunmber" instead of "gpio_index" while doing gpio configuration in icl_exec_gpio(). Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index c2a2cd1f84dc..cc93e045a425 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -381,7 +381,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) value = *data++ & 1; if (DISPLAY_VER(dev_priv) >= 11) - icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); + icl_exec_gpio(dev_priv, gpio_source, gpio_number, value); else if (IS_VALLEYVIEW(dev_priv)) vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); else if (IS_CHERRYVIEW(dev_priv)) From patchwork Fri Jul 23 07:05:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73964C432BE for ; Fri, 23 Jul 2021 06:58:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D75C60ED7 for ; Fri, 23 Jul 2021 06:58:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3D75C60ED7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90A506FA4D; Fri, 23 Jul 2021 06:58:36 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id B03E06FA4B for ; Fri, 23 Jul 2021 06:58:34 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829759" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829759" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405582" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:32 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:43 +0800 Message-Id: <20210723070548.29315-3-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DSI driver should have its own implementation to toggle gpio pins based on GPIO info coming from VBT sequences. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 10 +++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index cc93e045a425..dd03e5629ba6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -43,6 +43,7 @@ #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_sideband.h" +#include "intel_de.h" #define MIPI_TRANSFER_MODE_SHIFT 0 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 @@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv, u8 gpio_source, u8 gpio_index, bool value) { - drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); + u32 val; + + switch (gpio_index) { + case ICL_GPIO_L_VDDEN_1: + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1)); + if (value) + val |= PWR_STATE_TARGET; + else + val &= ~PWR_STATE_TARGET; + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val); + break; + case ICL_GPIO_L_BKLTEN_1: + val = intel_de_read(dev_priv, ICP_PP_CONTROL(1)); + if (value) + val |= BACKLIGHT_ENABLE; + else + val &= ~BACKLIGHT_ENABLE; + intel_de_write(dev_priv, ICP_PP_CONTROL(1), val); + break; + case ICL_GPIO_DDPA_CTRLCLK_1: + val = intel_de_read(dev_priv, GPIO(1)); + if (value) + val |= GPIO_CLOCK_VAL_OUT; + else + val &= ~GPIO_CLOCK_VAL_OUT; + val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK; + intel_de_write(dev_priv, GPIO(1), val); + break; + case ICL_GPIO_DDPA_CTRLDATA_1: + val = intel_de_read(dev_priv, GPIO(1)); + if (value) + val |= GPIO_DATA_VAL_OUT; + else + val &= ~GPIO_DATA_VAL_OUT; + val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK; + intel_de_write(dev_priv, GPIO(1), val); + break; + default: + /* TODO: Add support for remaining GPIOs */ + DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index); + break; + } } static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 943fe485c662..b725234e0e9c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5143,6 +5143,16 @@ enum { #define _PP_STATUS 0x61200 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) #define PP_ON REG_BIT(31) + +#define _PP_CONTROL_1 0xc7204 +#define _PP_CONTROL_2 0xc7304 +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \ + _PP_CONTROL_2) +#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) +#define VDD_OVERRIDE_FORCE REG_BIT(3) +#define BACKLIGHT_ENABLE REG_BIT(2) +#define PWR_DOWN_ON_RESET REG_BIT(1) +#define PWR_STATE_TARGET REG_BIT(0) /* * Indicates that all dependencies of the panel are on: * From patchwork Fri Jul 23 07:05:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09B40C432BE for ; Fri, 23 Jul 2021 06:58:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C96AF60ED7 for ; Fri, 23 Jul 2021 06:58:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C96AF60ED7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E39246EADC; Fri, 23 Jul 2021 06:58:40 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85B766FA4C for ; Fri, 23 Jul 2021 06:58:36 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829764" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829764" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405590" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:34 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:44 +0800 Message-Id: <20210723070548.29315-4-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Driver should wait for free header or payload buffer in FIFO. It would be good to wait a while for HW to release credit before give it up to write to HW. Without sending initailize command sets completely. It would caused MIPI display can't light up properly. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/icl_dsi.c | 40 ++++++++++++-------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 43ec7fcd3f5d..1780830d9909 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -54,20 +54,28 @@ static int payload_credits_available(struct drm_i915_private *dev_priv, >> FREE_PLOAD_CREDIT_SHIFT; } -static void wait_for_header_credits(struct drm_i915_private *dev_priv, - enum transcoder dsi_trans) +static bool wait_for_header_credits(struct drm_i915_private *dev_priv, + enum transcoder dsi_trans, int hdr_credit) { if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= - MAX_HEADER_CREDIT, 100)) + hdr_credit, 100)) { drm_err(&dev_priv->drm, "DSI header credits not released\n"); + return false; + } + + return true; } -static void wait_for_payload_credits(struct drm_i915_private *dev_priv, - enum transcoder dsi_trans) +static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, + enum transcoder dsi_trans, int payld_credit) { if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= - MAX_PLOAD_CREDIT, 100)) + payld_credit, 100)) { drm_err(&dev_priv->drm, "DSI payload credits not released\n"); + return false; + } + + return true; } static enum transcoder dsi_port_to_transcoder(enum port port) @@ -90,8 +98,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) /* wait for header/payload credits to be released */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - wait_for_header_credits(dev_priv, dsi_trans); - wait_for_payload_credits(dev_priv, dsi_trans); + wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); + wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); } /* send nop DCS command */ @@ -108,7 +116,7 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) /* wait for header credits to be released */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - wait_for_header_credits(dev_priv, dsi_trans); + wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); } /* wait for LP TX in progress bit to be cleared */ @@ -126,18 +134,13 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, struct intel_dsi *intel_dsi = host->intel_dsi; struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); - int free_credits; int i, j; for (i = 0; i < len; i += 4) { u32 tmp = 0; - free_credits = payload_credits_available(dev_priv, dsi_trans); - if (free_credits < 1) { - drm_err(&dev_priv->drm, - "Payload credit not available\n"); + if (!wait_for_payload_credits(dev_priv, dsi_trans, 1)) return false; - } for (j = 0; j < min_t(u32, len - i, 4); j++) tmp |= *data++ << 8 * j; @@ -155,15 +158,10 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); u32 tmp; - int free_credits; /* check if header credit available */ - free_credits = header_credits_available(dev_priv, dsi_trans); - if (free_credits < 1) { - drm_err(&dev_priv->drm, - "send pkt header failed, not enough hdr credits\n"); + if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) return -1; - } tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); From patchwork Fri Jul 23 07:05:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D1AC432BE for ; Fri, 23 Jul 2021 06:58:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FE9B60EAF for ; Fri, 23 Jul 2021 06:58:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8FE9B60EAF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27CA96FA4E; Fri, 23 Jul 2021 06:58:45 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F5F06FA4C for ; Fri, 23 Jul 2021 06:58:38 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829770" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829770" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405594" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:36 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:45 +0800 Message-Id: <20210723070548.29315-5-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to chapter "Sending Commands to the Panel" in bspec #29738 and #49188. If driver try to send DCS long pakcet, we have to program TX payload register at first. And configure TX header HW register later. DSC long packet would not be sent properly if we don't follow this sequence. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 1780830d9909..60413bbf565f 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1807,11 +1807,6 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, if (msg->flags & MIPI_DSI_MSG_USE_LPM) enable_lpdt = true; - /* send packet header */ - ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); - if (ret < 0) - return ret; - /* only long packet contains payload */ if (mipi_dsi_packet_format_is_long(msg->type)) { ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); @@ -1819,6 +1814,11 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, return ret; } + /* send packet header */ + ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); + if (ret < 0) + return ret; + //TODO: add payload receive code if needed ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; From patchwork Fri Jul 23 07:05:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8144BC4338F for ; Fri, 23 Jul 2021 06:58:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A42D60ED7 for ; Fri, 23 Jul 2021 06:58:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4A42D60ED7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 469B06F8C5; Fri, 23 Jul 2021 06:58:41 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC0706FA4C for ; Fri, 23 Jul 2021 06:58:39 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829772" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829772" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405603" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:38 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:46 +0800 Message-Id: <20210723070548.29315-6-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and max slice count == 1, max supported pixel clock should be 100% of CD clock. Then do min_cdclk and pixel clock comparison to get proper min cdclk. v2: - Check for dsc enable and slice count ==1 then allow to double confirm min cdclk value. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C Reviewed-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 71067a62264d..3e09f6370d27 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); + /* + * VDSC engine can process only 1 pixel per Cd clock. + * In case VDSC is used and max slice count == 1, + * max supported pixel clock should be 100% of CD clock. + * Then do min_cdclk and pixel clock comparison to get cdclk. + */ + if (crtc_state->dsc.compression_enable && + crtc_state->dsc.slice_count == 1) + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + /* * HACK. Currently for TGL platforms we calculate * min_cdclk initially based on pixel_rate divided From patchwork Fri Jul 23 07:05:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 851DEC4320E for ; Fri, 23 Jul 2021 06:58:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5827360EAF for ; Fri, 23 Jul 2021 06:58:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5827360EAF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 047376FA50; Fri, 23 Jul 2021 06:58:49 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id A932A6F94B for ; Fri, 23 Jul 2021 06:58:41 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829775" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829775" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405611" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:39 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:47 +0800 Message-Id: <20210723070548.29315-7-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" So far, DCS backlight driver hardcode (0xFF) for max brightness level. MIPI DCS spec allow max 0xFFFF for set_display_brightness (51h) command. And VBT brightness precision bits can support 8 ~ 16 bits. We should set correct precision bits in VBT that meet panel's request. Driver can refer to this setting then configure max brightness level in DCS backlight driver properly. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/intel_bios.c | 3 +++ .../gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 12 +++++++++--- drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 5b6922e28ef2..a43cbf35a01d 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -483,6 +483,9 @@ parse_lfp_backlight(struct drm_i915_private *i915, level = 255; } i915->vbt.backlight.min_brightness = min_level; + + i915->vbt.backlight.max_brightness_level = + (1 << backlight_data->brightness_precision_bits[panel_type]) - 1; } else { level = backlight_data->level[panel_type]; i915->vbt.backlight.min_brightness = entry->min_brightness; diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c index 584c14c4cbd0..cd85520d36e2 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c @@ -41,7 +41,7 @@ #define POWER_SAVE_HIGH (3 << 0) #define POWER_SAVE_OUTDOOR_MODE (4 << 0) -#define PANEL_PWM_MAX_VALUE 0xFF +#define PANEL_PWM_MAX_VALUE 0xFFFF static u32 dcs_get_backlight(struct intel_connector *connector, enum pipe unused) { @@ -147,10 +147,16 @@ static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state, static int dcs_setup_backlight(struct intel_connector *connector, enum pipe unused) { + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); struct intel_panel *panel = &connector->panel; - panel->backlight.max = PANEL_PWM_MAX_VALUE; - panel->backlight.level = PANEL_PWM_MAX_VALUE; + panel->backlight.max = dev_priv->vbt.backlight.max_brightness_level \ + ? dev_priv->vbt.backlight.max_brightness_level \ + : PANEL_PWM_MAX_VALUE; + panel->backlight.level = dev_priv->vbt.backlight.max_brightness_level \ + ? dev_priv->vbt.backlight.max_brightness_level \ + : PANEL_PWM_MAX_VALUE; return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f99b6c0dd068..210eef301ba6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -712,6 +712,7 @@ struct intel_vbt_data { struct { u16 pwm_freq_hz; + u16 max_brightness_level; bool present; bool active_low_pwm; u8 min_brightness; /* min_brightness/255 of max */ From patchwork Fri Jul 23 07:05:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12395367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26DF5C4338F for ; Fri, 23 Jul 2021 06:58:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EBF3D60EAF for ; Fri, 23 Jul 2021 06:58:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EBF3D60EAF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 889976F94B; Fri, 23 Jul 2021 06:58:44 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 562C26F94B for ; Fri, 23 Jul 2021 06:58:43 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10053"; a="211829779" X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="211829779" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 23:58:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,263,1620716400"; d="scan'208";a="502405623" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jul 2021 23:58:41 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Jul 2021 15:05:48 +0800 Message-Id: <20210723070548.29315-8-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com> References: <20210723070548.29315-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Driver has to swap the endian before send brightness level value to tcon. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C Reported-by: kernel test robot --- drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c index cd85520d36e2..47c1cd704915 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c @@ -66,10 +66,9 @@ static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 { struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder)); struct mipi_dsi_device *dsi_device; - u8 data = level; + u16 data = cpu_to_be16(level); enum port port; - /* FIXME: Need to take care of 16 bit brightness level */ for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) { dsi_device = intel_dsi->dsi_hosts[port]->device; mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,