From patchwork Sat Jul 24 19:04:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Branchereau X-Patchwork-Id: 12397743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ABB4C4338F for ; Sat, 24 Jul 2021 19:05:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D30660EB0 for ; Sat, 24 Jul 2021 19:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229606AbhGXSY6 (ORCPT ); Sat, 24 Jul 2021 14:24:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229530AbhGXSY6 (ORCPT ); Sat, 24 Jul 2021 14:24:58 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6BB5C061757; Sat, 24 Jul 2021 12:05:28 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id z7so5927123wrn.11; Sat, 24 Jul 2021 12:05:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFqPeTJizFnfUZM7Q40k9J0nA9MRhn5b8J6dQsSbkSU=; b=g5nY822zTiAYbbkQ4YvFuTxrqBbrNXQb0J6QLorJ6+V4lidZ71xypTmFB5e/wdlDmv Z+S+OLK1FmyQGep01xTB9/9vn1uhuGI15sgbW8RtkRAmwMqqd/9Nr6kTLFB/sVD89NBN GHmttZTJEYENNoHHQu//YH1hsPWfQwXbsz3xoVJY/20eomOzxcPzl0AaNFTgiKwY552B Ea6wuEb/61dxpYp1AbFlCR8kKoW7UyP/W++yhJL/uNRP6DJknEGKGRZ3sjI8qthxEr7z Ecw1XE4wmkW2iui+tO7c2Ngx6ArEqnijunxPClK1wF44rkXMuOdPnLF3JX3jG2D5SjrE IxbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFqPeTJizFnfUZM7Q40k9J0nA9MRhn5b8J6dQsSbkSU=; b=R+1PviGawqTnxE/gmNIJ4cQ5PLSYy+zPRkHlHTJrv5vnnfBm/q6P1uiUU6gZzR7I5C geoupOK+U7rgoAZ/0eDWD4lzKjsiLNdxWhuTLKeO6iEdWYYjpbAT46TzfpZPWYRTEEYJ mvW5Sq9LXebzF4HeXTsDtYOYgQBsevNJB4Ub3zYgJ42TYaVjTDD7setmmt/4zp8xydxi o43PV6HQtxz+78aL0z4bBF9JqBFArJ093H4ABtCXDUYQ+JnixQTGYrLbjNWISXjT5gJH WRl6+oBLapXx4qi27JuBhUvUJGYsqo/4AsfowFr/UbWSU6COrzDGoPPqhEZoDX9DwKiB 0NNQ== X-Gm-Message-State: AOAM530q+9UHp3WaLC8frgU6DYJYAO6U5Oy3fxDXyMKYdt20aw2wOpol xOBxtbAWFY4qbbLbqc7NpaQ= X-Google-Smtp-Source: ABdhPJyER3AGOSAzaJBWOSY3FIvCmfsIuvtui436ER79FTl14zfHObSDGR1r7fovxH8clCA5FgzmBg== X-Received: by 2002:a5d:4a4c:: with SMTP id v12mr10875840wrs.256.1627153527415; Sat, 24 Jul 2021 12:05:27 -0700 (PDT) Received: from monk.home (astrasbourg-157-1-7-84.w90-40.abo.wanadoo.fr. [90.40.218.84]) by smtp.gmail.com with ESMTPSA id j15sm1117798wms.20.2021.07.24.12.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 12:05:27 -0700 (PDT) From: Christophe Branchereau Cc: jic23@kernel.org, lars@metafoo.de, linux-mips@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, contact@artur-rojek.eu, paul@crapouillou.net, Christophe Branchereau Subject: [PATCH v3 1/5] iio/adc: ingenic: rename has_aux2 to has_aux_md Date: Sat, 24 Jul 2021 21:04:45 +0200 Message-Id: <20210724190449.221894-2-cbranchereau@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210724190449.221894-1-cbranchereau@gmail.com> References: <20210724190449.221894-1-cbranchereau@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The jz4760(b) socs have 3 aux channels. The purpose of has_aux2 is to set the MD bits used to select the AUX channel to be sampled, not to describe the hardware. Rename it to a more appropriate name. Signed-off-by: Christophe Branchereau Reviewed-by: Paul Cercueil --- drivers/iio/adc/ingenic-adc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ingenic-adc.c index 34c03a264f74..40f2d8c2cf72 100644 --- a/drivers/iio/adc/ingenic-adc.c +++ b/drivers/iio/adc/ingenic-adc.c @@ -92,7 +92,7 @@ struct ingenic_adc_soc_data { const int *battery_scale_avail; size_t battery_scale_avail_size; unsigned int battery_vref_mode: 1; - unsigned int has_aux2: 1; + unsigned int has_aux_md: 1; const struct iio_chan_spec *channels; unsigned int num_channels; int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc); @@ -506,7 +506,7 @@ static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { .battery_scale_avail = jz4725b_adc_battery_scale_avail, .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail), .battery_vref_mode = true, - .has_aux2 = false, + .has_aux_md = false, .channels = jz4740_channels, .num_channels = ARRAY_SIZE(jz4740_channels), .init_clk_div = jz4725b_adc_init_clk_div, @@ -520,7 +520,7 @@ static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { .battery_scale_avail = jz4740_adc_battery_scale_avail, .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail), .battery_vref_mode = true, - .has_aux2 = false, + .has_aux_md = false, .channels = jz4740_channels, .num_channels = ARRAY_SIZE(jz4740_channels), .init_clk_div = NULL, /* no ADCLK register on JZ4740 */ @@ -534,7 +534,7 @@ static const struct ingenic_adc_soc_data jz4770_adc_soc_data = { .battery_scale_avail = jz4770_adc_battery_scale_avail, .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail), .battery_vref_mode = false, - .has_aux2 = true, + .has_aux_md = true, .channels = jz4770_channels, .num_channels = ARRAY_SIZE(jz4770_channels), .init_clk_div = jz4770_adc_init_clk_div, @@ -581,7 +581,7 @@ static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev, /* We cannot sample AUX/AUX2 in parallel. */ mutex_lock(&adc->aux_lock); - if (adc->soc_data->has_aux2 && engine == 0) { + if (adc->soc_data->has_aux_md && engine == 0) { bit = BIT(chan->channel == INGENIC_ADC_AUX2); ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit); } From patchwork Sat Jul 24 19:04:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Branchereau X-Patchwork-Id: 12397747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0AAEC4338F for ; Sat, 24 Jul 2021 19:05:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8225C60E09 for ; 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[90.40.218.84]) by smtp.gmail.com with ESMTPSA id j15sm1117798wms.20.2021.07.24.12.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 12:05:27 -0700 (PDT) From: Christophe Branchereau Cc: jic23@kernel.org, lars@metafoo.de, linux-mips@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, contact@artur-rojek.eu, paul@crapouillou.net, Christophe Branchereau Subject: [PATCH v3 2/5] dt-bindings: iio/adc: add an INGENIC_ADC_AUX0 entry Date: Sat, 24 Jul 2021 21:04:46 +0200 Message-Id: <20210724190449.221894-3-cbranchereau@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210724190449.221894-1-cbranchereau@gmail.com> References: <20210724190449.221894-1-cbranchereau@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The JZ4760(B) socs have 3 AUX inputs, add an entry to prepare including the one named AUX in the sadc driver. Leaving the rest untouched as it's ABI. Signed-off-by: Christophe Branchereau Reviewed-by: Paul Cercueil --- include/dt-bindings/iio/adc/ingenic,adc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/iio/adc/ingenic,adc.h b/include/dt-bindings/iio/adc/ingenic,adc.h index 4627a00e369e..a6ccc031635b 100644 --- a/include/dt-bindings/iio/adc/ingenic,adc.h +++ b/include/dt-bindings/iio/adc/ingenic,adc.h @@ -13,5 +13,6 @@ #define INGENIC_ADC_TOUCH_YN 6 #define INGENIC_ADC_TOUCH_XD 7 #define INGENIC_ADC_TOUCH_YD 8 +#define INGENIC_ADC_AUX0 9 #endif From patchwork Sat Jul 24 19:04:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Branchereau X-Patchwork-Id: 12397749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B19F8C4320E for ; Sat, 24 Jul 2021 19:05:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C29760E98 for ; Sat, 24 Jul 2021 19:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbhGXSZC (ORCPT ); Sat, 24 Jul 2021 14:25:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229745AbhGXSZA (ORCPT ); Sat, 24 Jul 2021 14:25:00 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9FB3C061757; Sat, 24 Jul 2021 12:05:30 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id n11so2753099wmd.2; Sat, 24 Jul 2021 12:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r4l4X9Ml9axxQp0KFzsTd5BH2EID20QmHeunm7jfaaI=; b=EFbKtpEYqM0JbnaWCyMfLkzsjfqn+6n7VqWYEVhYWZ/1W5/DVxhg3o2JDUl8Zv4B5U +RYeF229YNGBTT6REqUCSa0+KeFGYlPVdJaMXozsXgVFl5CyyEt1mCVVh+vto+9VTf8t QJa4+/Sv4R7SgCaI0Xzll8rlQHeBndnCiG/akrLu60rEe89PGtmbwjGACuseUPAh+Ryf tsbYE+6UaBvxD5WmGriGe7inXieEf34KE57VRSj26MAez9w4n7VRQhwQgQPTXopYnTPl 6lB+SGXJEmwvjahEOgl4kpvn+GmvcaNd2NkJxo+Y7fqACiaqvfWCmP7vWItp7Td7KYxa WDOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r4l4X9Ml9axxQp0KFzsTd5BH2EID20QmHeunm7jfaaI=; b=I0nGJqd6Z+DiSj14vuvRElXSIBECu2Xe2Rqdv5XhSs8cXgkSQ1fydDfxGle64TUuv5 QowUqgTBOPsn9tTdc7ldqsP2Zp8EZYooL8ITkXbC82P5T0qiZ6MUSKjhLA9zcJmt2OXG 3cErj/1nWdyxLlU9XLZb07BWBwCo4eocwebzVV4Nc83myBnLvILYSybBE446WgYYja/W qtq1YY/rTVmgeoBA0tjwo0Jvs5Sm1U0cvhBf7MportC/7MsgYrMjPo+1BCnsabKUuUcl NbPr/iJ3BQB+GIRV0tBCmXGy9pSBFjUN8Thazuon85SlFJ439Qp4Ns8D04QoXJqdKhzF tSzQ== X-Gm-Message-State: AOAM530R5NJClGI78x2Fev9InlSZMEY0n9+vEpIXMeHVufZu1zu85KSc DUVNgBny8L96dOZTsB55vb0= X-Google-Smtp-Source: ABdhPJyf2ox5QLWxNIExZYLr3mmgGNJUkVFz4luV6S7JpaNeRe7Kp9Gm/Ag1xINQHYWW1pl0n2wKXg== X-Received: by 2002:a1c:26c4:: with SMTP id m187mr325127wmm.71.1627153529062; Sat, 24 Jul 2021 12:05:29 -0700 (PDT) Received: from monk.home (astrasbourg-157-1-7-84.w90-40.abo.wanadoo.fr. [90.40.218.84]) by smtp.gmail.com with ESMTPSA id j15sm1117798wms.20.2021.07.24.12.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 12:05:28 -0700 (PDT) From: Christophe Branchereau Cc: jic23@kernel.org, lars@metafoo.de, linux-mips@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, contact@artur-rojek.eu, paul@crapouillou.net, Christophe Branchereau Subject: [PATCH v3 3/5] iio/adc: ingenic: add JZ4760 support to the sadc driver Date: Sat, 24 Jul 2021 21:04:47 +0200 Message-Id: <20210724190449.221894-4-cbranchereau@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210724190449.221894-1-cbranchereau@gmail.com> References: <20210724190449.221894-1-cbranchereau@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The jz4760 sadc is very similar to the jz4770 one, but has a VREF of 2.5V and 3 aux channels. modify ingenic_adc_read_chan_info_raw() needs a change to account for it. Signed-off-by: Christophe Branchereau Reviewed-by: Paul Cercueil --- drivers/iio/adc/ingenic-adc.c | 82 +++++++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ingenic-adc.c index 40f2d8c2cf72..6b9af0530590 100644 --- a/drivers/iio/adc/ingenic-adc.c +++ b/drivers/iio/adc/ingenic-adc.c @@ -71,6 +71,7 @@ #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10 #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986) #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12 +#define JZ4760_ADC_BATTERY_VREF 2500 #define JZ4770_ADC_BATTERY_VREF 1200 #define JZ4770_ADC_BATTERY_VREF_BITS 12 @@ -295,6 +296,10 @@ static const int jz4740_adc_battery_scale_avail[] = { JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS, }; +static const int jz4760_adc_battery_scale_avail[] = { + JZ4760_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS, +}; + static const int jz4770_adc_battery_raw_avail[] = { 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1, }; @@ -400,6 +405,47 @@ static const struct iio_chan_spec jz4740_channels[] = { }, }; +static const struct iio_chan_spec jz4760_channels[] = { + { + .extend_name = "aux", + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .indexed = 1, + .channel = INGENIC_ADC_AUX0, + .scan_index = -1, + }, + { + .extend_name = "aux1", + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .indexed = 1, + .channel = INGENIC_ADC_AUX, + .scan_index = -1, + }, + { + .extend_name = "aux2", + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .indexed = 1, + .channel = INGENIC_ADC_AUX2, + .scan_index = -1, + }, + { + .extend_name = "battery", + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .indexed = 1, + .channel = INGENIC_ADC_BATTERY, + .scan_index = -1, + }, +}; + static const struct iio_chan_spec jz4770_channels[] = { { .type = IIO_VOLTAGE, @@ -526,6 +572,20 @@ static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { .init_clk_div = NULL, /* no ADCLK register on JZ4740 */ }; +static const struct ingenic_adc_soc_data jz4760_adc_soc_data = { + .battery_high_vref = JZ4760_ADC_BATTERY_VREF, + .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS, + .battery_raw_avail = jz4770_adc_battery_raw_avail, + .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail), + .battery_scale_avail = jz4760_adc_battery_scale_avail, + .battery_scale_avail_size = ARRAY_SIZE(jz4760_adc_battery_scale_avail), + .battery_vref_mode = false, + .has_aux_md = true, + .channels = jz4760_channels, + .num_channels = ARRAY_SIZE(jz4760_channels), + .init_clk_div = jz4770_adc_init_clk_div, +}; + static const struct ingenic_adc_soc_data jz4770_adc_soc_data = { .battery_high_vref = JZ4770_ADC_BATTERY_VREF, .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS, @@ -569,7 +629,7 @@ static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *chan, int *val) { - int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY); + int cmd, ret, engine = (chan->channel == INGENIC_ADC_BATTERY); struct ingenic_adc *adc = iio_priv(iio_dev); ret = clk_enable(adc->clk); @@ -579,11 +639,22 @@ static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev, return ret; } - /* We cannot sample AUX/AUX2 in parallel. */ + /* We cannot sample the aux channels in parallel. */ mutex_lock(&adc->aux_lock); if (adc->soc_data->has_aux_md && engine == 0) { - bit = BIT(chan->channel == INGENIC_ADC_AUX2); - ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit); + switch (chan->channel) { + case INGENIC_ADC_AUX0: + cmd = 0; + break; + case INGENIC_ADC_AUX: + cmd = 1; + break; + case INGENIC_ADC_AUX2: + cmd = 2; + break; + } + + ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, cmd); } ret = ingenic_adc_capture(adc, engine); @@ -591,6 +662,7 @@ static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev, goto out; switch (chan->channel) { + case INGENIC_ADC_AUX0: case INGENIC_ADC_AUX: case INGENIC_ADC_AUX2: *val = readw(adc->base + JZ_ADC_REG_ADSDAT); @@ -621,6 +693,7 @@ static int ingenic_adc_read_raw(struct iio_dev *iio_dev, return ingenic_adc_read_chan_info_raw(iio_dev, chan, val); case IIO_CHAN_INFO_SCALE: switch (chan->channel) { + case INGENIC_ADC_AUX0: case INGENIC_ADC_AUX: case INGENIC_ADC_AUX2: *val = JZ_ADC_AUX_VREF; @@ -832,6 +905,7 @@ static int ingenic_adc_probe(struct platform_device *pdev) static const struct of_device_id ingenic_adc_of_match[] = { { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, }, { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, }, + { .compatible = "ingenic,jz4760-adc", .data = &jz4760_adc_soc_data, }, { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, }, { }, }; From patchwork Sat Jul 24 19:04:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Branchereau X-Patchwork-Id: 12397753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7000AC4320A for ; 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[90.40.218.84]) by smtp.gmail.com with ESMTPSA id j15sm1117798wms.20.2021.07.24.12.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 12:05:29 -0700 (PDT) From: Christophe Branchereau Cc: jic23@kernel.org, lars@metafoo.de, linux-mips@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, contact@artur-rojek.eu, paul@crapouillou.net, Christophe Branchereau Subject: [PATCH v3 4/5] iio/adc: ingenic: add JZ4760B support to the sadc driver Date: Sat, 24 Jul 2021 21:04:48 +0200 Message-Id: <20210724190449.221894-5-cbranchereau@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210724190449.221894-1-cbranchereau@gmail.com> References: <20210724190449.221894-1-cbranchereau@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The JZ4760B variant differs slightly from the JZ4760: it has a bit called VBAT_SEL in the CFG register. In order to correctly sample the battery voltage on existing handhelds using this SOC, the bit must be cleared. We leave the possibility to set the bit, by using the "ingenic,use-internal-divider" in the devicetree. Signed-off-by: Christophe Branchereau --- drivers/iio/adc/ingenic-adc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ingenic-adc.c index 6b9af0530590..eaa8ab36183c 100644 --- a/drivers/iio/adc/ingenic-adc.c +++ b/drivers/iio/adc/ingenic-adc.c @@ -37,6 +37,7 @@ #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10) #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16) #define JZ_ADC_REG_CFG_CMD_SEL BIT(22) +#define JZ_ADC_REG_CFG_VBAT_SEL BIT(30) #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10)) #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16 @@ -879,6 +880,14 @@ static int ingenic_adc_probe(struct platform_device *pdev) /* Put hardware in a known passive state. */ writeb(0x00, adc->base + JZ_ADC_REG_ENABLE); writeb(0xff, adc->base + JZ_ADC_REG_CTRL); + + /* JZ4760B specific */ + if (device_property_present(dev, "ingenic,use-internal-divider")) + ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL, + JZ_ADC_REG_CFG_VBAT_SEL); + else + ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL, 0); + usleep_range(2000, 3000); /* Must wait at least 2ms. */ clk_disable(adc->clk); From patchwork Sat Jul 24 19:04:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Branchereau X-Patchwork-Id: 12397751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FD74C432BE for ; Sat, 24 Jul 2021 19:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2AED260EBA for ; Sat, 24 Jul 2021 19:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230196AbhGXSZP (ORCPT ); Sat, 24 Jul 2021 14:25:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229873AbhGXSZC (ORCPT ); Sat, 24 Jul 2021 14:25:02 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E18CC06175F; Sat, 24 Jul 2021 12:05:32 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id m20-20020a05600c4f54b029024e75a15716so2691486wmq.2; Sat, 24 Jul 2021 12:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L6mgIBbDERHrkCfdLTeeBkkROy6MNNlPhpbr+IZWCG0=; b=kWO5kTX6qOZhjysoEpAtRpAwW9NLPsN7Xm1DOg6ApYo1yJDVOOy7mGzGWSWqoHnDUG sCGCHK/Qg31NBII+CppsVqz4W5fu9g09DbhK1EDAffkOrsdXWbNYfGvgRuiUmdcApaKu YbiIMUqHx+VriAIpvsFY3LOh95ERz1kc9tPPoJYviYdwcVNDhjm6G7XC859pdQws+Ugs 82TTq6TJzcIwwlVuZdr4G/HUAdFzczbMQJvjtXi9NzMtWSlQnrO5sd/zXYvLMwJ7xNaE dwqJM75lrgsbstFK9xIU7n4Aa1BxH5XE++LME/4zYR0fZHm0sgezUc1nERcZ0DVt0CH9 xvsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L6mgIBbDERHrkCfdLTeeBkkROy6MNNlPhpbr+IZWCG0=; b=Sz6Pg6qEMD7dQykBoE2Fl3Hs4AIYLEV1eoePEEhapOB0zClh2B8fR/XCc41ODDxO+2 d+ro8wgAGzepfxn1X3Gw+yFMFk6ZQPmAV65B5bFLZcWNwhOKELSESqoD+Xx3axBmuqu7 SgB5ipHGxmRr6AMEUwpAoH7SU2YUUN3+twhE5auLwCbcVzwzkfdikWCVIcvoAtNzyLB/ Z1ooSS3tKpENaT230tlTHo0UH5u/F3jnr7iH1yMm445e82OBOzhfeJ/ugHEQE7qNVQgb XitVSDpoq8iK/W/RYGXcWR+qxQ+E/ebcH8rCGEMPg8IuHgD1s73TYXZDbAhdJJRCaaF3 kYSA== X-Gm-Message-State: AOAM530tyaM77WKtEcR0EydGegnpT9tBuIQSZQUZAHBxe4HEhask3pjM +uqoPpx4sQzZjyOIjhKHDuX7BUUCPAEnjIlF X-Google-Smtp-Source: ABdhPJwiri0wRQuVWzxKRd7O64i3yhmC0ux1B5nJV+Lp05qiUNKbpFW6GZHthZto9WkNOLlr0aFMtg== X-Received: by 2002:a1c:f613:: with SMTP id w19mr20214045wmc.136.1627153530699; Sat, 24 Jul 2021 12:05:30 -0700 (PDT) Received: from monk.home (astrasbourg-157-1-7-84.w90-40.abo.wanadoo.fr. [90.40.218.84]) by smtp.gmail.com with ESMTPSA id j15sm1117798wms.20.2021.07.24.12.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 12:05:30 -0700 (PDT) From: Christophe Branchereau Cc: jic23@kernel.org, lars@metafoo.de, linux-mips@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux@roeck-us.net, contact@artur-rojek.eu, paul@crapouillou.net, Christophe Branchereau Subject: [PATCH v3 5/5] dt-bindings: iio/adc: ingenic: add the JZ4760(B) socs to the sadc Documentation Date: Sat, 24 Jul 2021 21:04:49 +0200 Message-Id: <20210724190449.221894-6-cbranchereau@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210724190449.221894-1-cbranchereau@gmail.com> References: <20210724190449.221894-1-cbranchereau@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add both the jz4760 and jz4760b, plus a property to use the internal divider on the b variant and document it. Signed-off-by: Christophe Branchereau Reviewed-by: Paul Cercueil --- .../bindings/iio/adc/ingenic,adc.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml index 433a3fb55a2e..3eb7aa8822c3 100644 --- a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml @@ -23,6 +23,8 @@ properties: enum: - ingenic,jz4725b-adc - ingenic,jz4740-adc + - ingenic,jz4760-adc + - ingenic,jz4760b-adc - ingenic,jz4770-adc '#io-channel-cells': @@ -43,6 +45,23 @@ properties: interrupts: maxItems: 1 + ingenic,use-internal-divider: + description: + If present, battery voltage is read from the VBAT_IR pin, which has an + internal 1/4 divider. If absent, it is read through the VBAT_ER pin, + which does not have such a divider. + type: boolean + +if: + not: + properties: + compatible: + contains: + const: ingenic,jz4760b-adc +then: + properties: + ingenic,use-internal-divider: false + required: - compatible - '#io-channel-cells'