From patchwork Mon Jul 26 08:32:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 12398875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-22.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B193CC4338F for ; Mon, 26 Jul 2021 08:39:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 73BF36024A for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m7w2d-00ADmk-JF; Mon, 26 Jul 2021 08:32:51 +0000 Received: from lb3-smtp-cloud9.xs4all.net ([194.109.24.30]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m7w2R-00ADhs-B2 for linux-arm-kernel@lists.infradead.org; Mon, 26 Jul 2021 08:32:41 +0000 Received: from copland.sibelius.xs4all.nl ([83.163.83.176]) by smtp-cloud9.xs4all.net with ESMTP id 7w2DmOzH54Jsb7w2QmW9Nr; Mon, 26 Jul 2021 10:32:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1627288358; bh=GWt5LuWPf3oek+gIp/5dyhcc4QQE8RQI7HAJudeIgsw=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=LOumNdCm5LdudnnCecwSz33JKKX1SuZ6ewF7zSDOR7+TzT/8PXSr+wCZlInAYgNwi mE7owpgG17hPX3tnU7n6Exkn+LAHtGnQBOVyTMfwGNfCgcCTuezsgOridF3LDE+9R/ Kp/8AyUoBUFWmZ5gVTgqCr//tS+GM4CZCIlHb10aw8U9+XEWLCVGe9r+OWUzGcghr2 FKleytXkh8OoBWs2+WYoylICTQwFncFquLX7ENMMA5DhJHwk55tYFHmwEeD2LbIvnH L4FIdfK+/35jYiBNpbWHnY7GnJ2PoeU8lgASLjBy1fCZxNACnjsigZG7v2ciT77ZeZ RBIcoCp91fdqA== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, Mark Kettenis , Hector Martin , Bjorn Helgaas , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: pci: Add DT bindings for apple,pcie Date: Mon, 26 Jul 2021 10:32:00 +0200 Message-Id: <20210726083204.93196-2-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210726083204.93196-1-mark.kettenis@xs4all.nl> References: <20210726083204.93196-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfP11OTtA1mcDlQcRvuB1CqGUBdkCQoJMby5ObOd4hsvrK9swzvorSiJRQLGZQiTkvCIUDx8iIj1Flzkh9+sPsNN6Hm48I2rjidwq3IcGbXWRv9OG7ePg kEqnUYJXlc471PE8nipHXO/rQ7CBAwPhDaJrWG8sLd2kTT1XMBvZ5b0MFIALxoGsAU7YUoF1lIBd99CTwNSufq++OXrWz9Y0xQ4KDPNUHCwDS5U3ljzb4o3M Fy+7dYmawgXiOkZwWO3wYnhgXlZtbhE6iZ0mCFxlBVE221gBQe+2IeP/GyfqKLUEHUHe0ysdxg1w/OO/Kf6+EGN5MuRWupEyTlvA5iXPQBJOJomiyALraQUm /+2DCYN1yLuuj4sbr/ZDBnObBoGnPzY/Sl5oaehoY+Iaew6xirLJAlplHcbvfz8Zjn9ctfAK9vxj2u2Vw9qepTunPgaHFdxSkjIN/YO65//lqbH8fOgEu1G5 wGw/E4oGLJr1rmpGh7t8IXFk6xZNP5iBdaGCj5iIsey8AaFr2vSrrVM4/RQ4UbBvNQ4r6Hqo4kCPR7ZsPS5gsEkwLHBtZ4KpgJ8/hQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210726_013239_582482_62BB084F X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Kettenis The Apple PCIe host controller is a PCIe host controller with multiple root ports present in Apple ARM SoC platforms, including various iPhone and iPad devices and the "Apple Silicon" Macs. Signed-off-by: Mark Kettenis --- .../devicetree/bindings/pci/apple,pcie.yaml | 166 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml new file mode 100644 index 000000000000..bfcbdee79c64 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple PCIe host controller + +maintainers: + - Mark Kettenis + +description: | + The Apple PCIe host controller is a PCIe host controller with + multiple root ports present in Apple ARM SoC platforms, including + various iPhone and iPad devices and the "Apple Silicon" Macs. + The controller incorporates Synopsys DesigWare PCIe logic to + implements its root ports. But the ATU found on most DesignWare + PCIe host bridges is absent. + All root ports share a single ECAM space, but separate GPIOs are + used to take the PCI devices on those ports out of reset. Therefore + the standard "reset-gpio" and "max-link-speed" properties appear on + the child nodes that represent the PCI bridges that correspond to + the individual root ports. + MSIs are handled by the PCIe controller and translated into regular + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be + distributed over the root ports as the OS sees fit by programming + the PCIe controller's port registers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + items: + - const: apple,t8103-pcie + - const: apple,pcie + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 + items: + - const: config + - const: rc + - const: port0 + - const: port1 + - const: port2 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: + Interrupt specifiers, one for each root port. + minItems: 1 + maxItems: 3 + + msi-controller: true + msi-parent: true + + msi-ranges: + description: + A list of pairs , where "intid" is the first + interrupt number that can be used as an MSI, and "span" the size + of that range. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + minItems: 2 + maxItems: 2 + + iommu-map: true + iommu-map-mask: true + +required: + - compatible + - reg + - reg-names + - bus-range + - interrupts + - msi-controller + - msi-parent + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x4000>, + <0x6 0x81000000 0x0 0x8000>, + <0x6 0x82000000 0x0 0x8000>, + <0x6 0x83000000 0x0 0x8000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <704 32>; + + iommu-map = <0x100 &dart0 1 1>, + <0x200 &dart1 1 1>, + <0x300 &dart2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + clocks = <&pcie_core_clk>, <&pcie_aux_clk>, <&pcie_ref_clk>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 19135a9d778e..f4aa40d3166e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1694,6 +1694,7 @@ C: irc://chat.freenode.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c From patchwork Mon Jul 26 08:32:01 2021 Content-Type: text/plain; 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Mon, 26 Jul 2021 08:33:08 +0000 Received: from lb2-smtp-cloud9.xs4all.net ([194.109.24.26]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m7w2Z-00ADlR-7O for linux-arm-kernel@lists.infradead.org; Mon, 26 Jul 2021 08:32:48 +0000 Received: from copland.sibelius.xs4all.nl ([83.163.83.176]) by smtp-cloud9.xs4all.net with ESMTP id 7w2DmOzH54Jsb7w2WmW9Om; Mon, 26 Jul 2021 10:32:44 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1627288364; bh=PKbQ1TmUx1VxAzGEjtXpNW/Qb53gi7gmApBAe4okEsI=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=g3+Imej37aAQx9NE+ANp2i/Y1eNwT3P9EcgAYxRnZb8nDPnUe9vMhzUtMoIN6Kr+i rPEmlime5AEk1KYXWYzhtRTMbonjSixyosJA7NGglJ/6NTQdel1KDDts4cNYzFmPZb LZW1zlpxh4/2u9AugpXFn/XTHteZwwH1Fl4wNii5pJnpp50y1KwdOoiUAOV6hudzRh fFG9/3s6Tez/oHcySaLY21ma/tQsTuXEv11+KQ5fhGST0QzdzHM2Tx1mVdNDi617fG MwI4a/wmVIsCyaIftnxwbFl2673ofg2pySspq/pWJOBGFNpR2twJEukUlMpI0/sGX6 UGWXx+JYIz3qQ== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, Mark Kettenis , Hector Martin , Bjorn Helgaas , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] arm64: apple: Add PCIe node Date: Mon, 26 Jul 2021 10:32:01 +0200 Message-Id: <20210726083204.93196-3-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210726083204.93196-1-mark.kettenis@xs4all.nl> References: <20210726083204.93196-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfNgmQNzELbD+zU3VM/bNjyFjHaUQPd84PWVoDiNStFaEhlF1Z0Ouoq97lo+jRhfg0zzWNzfCbCozTMRLkRE55hGOxB5YxqwGJU6LwEOaLRzD3SkRLatU A8r2W4Yw5lPbLSINkh/DpOTEWjOwBJ1laUXWqsWs/hBOPR9agv2j2IsQEtiTc1Ux1N95Mi0mgV53EGQYKZv3lrHFs8XIieYWT7gVvCZJGnpyysulvfSmPXoi iGkMhPMYz9OJvO0nrXXaiqwfOGafGgo8Negn9ggqlrXg5aAYjil58+zvYJ/671NlOpwa/JI8IBtkbuwF7VGjK+i5/X8UwslsT9Ru/HGtoRWkyc6fwzrL1Uyj iXDRfdZgjZqWOV0CMCOHjL0fKdSXRyWjEAmhzZcvEW91e1tyHiZb8No/NQhhhFYLXqtqK1ghvTQ7Ml6R3IaunE3kiU4Qlr2mp/vBA09aSdXGsqyA+04YVBfO gjUQoB7wJy/Ru2XodQYXxk5VeIAZMUsPmD3AbzbUsIDMH6WSQI4yiM6ZcoSUfaUpJciKg+vXZkrMVlaDcZXWrKQfOHc5QOeelrdp+w== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210726_013247_462891_6B73A5BA X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Kettenis Add node corresponding to the apcie,t8103 node in the Apple device tree for the Mac mini (M1, 2020). Clock references and DART (IOMMU) references are left out at the moment and will be added once the appropriate bindings have been settled upon. Signed-off-by: Mark Kettenis --- arch/arm64/boot/dts/apple/t8103.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 503a76fc30e6..cd3ebb940e86 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -214,5 +214,68 @@ pinctrl_smc: pinctrl@23e820000 { , ; }; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x4000>, + <0x6 0x81000000 0x0 0x8000>, + <0x6 0x82000000 0x0 0x8000>, + <0x6 0x83000000 0x0 0x8000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <704 32>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; };