From patchwork Thu Dec 6 01:09:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 10715163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4C421731 for ; Thu, 6 Dec 2018 01:09:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D326329821 for ; Thu, 6 Dec 2018 01:09:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C50322DBA1; Thu, 6 Dec 2018 01:09:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC85629821 for ; Thu, 6 Dec 2018 01:09:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728870AbeLFBJf (ORCPT ); Wed, 5 Dec 2018 20:09:35 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:27018 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728810AbeLFBJe (ORCPT ); Wed, 5 Dec 2018 20:09:34 -0500 X-UUID: da60c881892c489a9df785b81b605916-20181206 X-UUID: da60c881892c489a9df785b81b605916-20181206 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 587175850; Thu, 06 Dec 2018 09:09:20 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 6 Dec 2018 09:09:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 6 Dec 2018 09:09:17 +0800 From: Jianjun Wang To: , , , , , CC: , , , , , , , Jianjun Wang Subject: [PATCH 1/2] dt-bindings: PCI: Add support for MT7629 Date: Thu, 6 Dec 2018 09:09:12 +0800 Message-ID: <1544058553-10936-2-git-send-email-jianjun.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544058553-10936-1-git-send-email-jianjun.wang@mediatek.com> References: <1544058553-10936-1-git-send-email-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MT7629 is an arm platform Soc which has the same PCIe IP with MT7622. Signed-off-by: Jianjun Wang Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 20227a875ac8..3790c6cc108f 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -6,6 +6,7 @@ Required properties: "mediatek,mt2712-pcie" "mediatek,mt7622-pcie" "mediatek,mt7623-pcie" + "mediatek,mt7629-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the PCIe subsys and root ports. - reg-names: Names of the above areas to use during resource lookup. From patchwork Thu Dec 6 01:09:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 10715169 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D4181731 for ; Thu, 6 Dec 2018 01:09:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D48729821 for ; Thu, 6 Dec 2018 01:09:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 514EB2DB6C; Thu, 6 Dec 2018 01:09:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7004F29821 for ; Thu, 6 Dec 2018 01:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728763AbeLFBJ3 (ORCPT ); Wed, 5 Dec 2018 20:09:29 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:40651 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728758AbeLFBJ3 (ORCPT ); Wed, 5 Dec 2018 20:09:29 -0500 X-UUID: f925863b2cee4e619ee0f4992650c4a3-20181206 X-UUID: f925863b2cee4e619ee0f4992650c4a3-20181206 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2003207512; Thu, 06 Dec 2018 09:09:21 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 6 Dec 2018 09:09:20 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 6 Dec 2018 09:09:19 +0800 From: Jianjun Wang To: , , , , , CC: , , , , , , , Jianjun Wang Subject: [PATCH 2/2] PCI: mediatek: Add controller support for MT7629 Date: Thu, 6 Dec 2018 09:09:13 +0800 Message-ID: <1544058553-10936-3-git-send-email-jianjun.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544058553-10936-1-git-send-email-jianjun.wang@mediatek.com> References: <1544058553-10936-1-git-send-email-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A023BCEA8D70FAFF7E6DD84C093D03E3E7BD40AA7C98361D308535D6AD2714F52000:8 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MT7629 is an arm platform SoC which has the same PCIe IP with MT7622. The read value of BAR0 is 0xffff_ffff, it's size will be calculated as 4GB in arm64 but bogus alignment values at arm32, the pcie device and devices behind this bridge will not be enabled. Fix it's BAR0 resource size to guarantee the pcie devices will be enabled correctly. The HW default value of its device id is invalid, fix it's device id to match the hardware implementation. Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek.c | 26 ++++++++++++++++++++++++++ include/linux/pci_ids.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index d20cf461ba00..f8937cc3c87c 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -73,6 +73,7 @@ #define PCIE_MSI_VECTOR 0x0c0 #define PCIE_CONF_VEND_ID 0x100 +#define PCIE_CONF_DEVICE_ID 0x102 #define PCIE_CONF_CLASS_ID 0x106 #define PCIE_INT_MASK 0x420 @@ -135,12 +136,14 @@ struct mtk_pcie_port; /** * struct mtk_pcie_soc - differentiate between host generations * @need_fix_class_id: whether this host's class ID needed to be fixed or not + * @need_fix_device_id: whether this host's device ID needed to be fixed or not * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions */ struct mtk_pcie_soc { bool need_fix_class_id; + bool need_fix_device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); @@ -692,6 +695,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) writew(val, port->base + PCIE_CONF_CLASS_ID); } + if (soc->need_fix_device_id) { + val = PCI_DEVICE_ID_MEDIATEK_7629; + writew(val, port->base + PCIE_CONF_DEVICE_ID); + } + /* 100ms timeout value should be enough for Gen1/2 training */ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, !!(val & PCIE_PORT_LINKUP_V2), 20, @@ -1238,11 +1246,29 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { .setup_irq = mtk_pcie_setup_irq, }; +static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { + .need_fix_class_id = true, + .need_fix_device_id = true, + .ops = &mtk_pcie_ops_v2, + .startup = mtk_pcie_startup_port_v2, + .setup_irq = mtk_pcie_setup_irq, +}; + +static void mtk_fixup_bar_size(struct pci_dev *dev) +{ + struct resource *dev_res = &dev->resource[0]; + /* 32bit resource length will calculate size to 0, set it smaller */ + dev_res->end = 0xfffffffe; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MEDIATEK, PCI_DEVICE_ID_MEDIATEK_7629, + mtk_fixup_bar_size); + static const struct of_device_id mtk_pcie_ids[] = { { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, + { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, {}, }; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 69f0abe1ba1a..77b278bac3a8 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2126,6 +2126,7 @@ #define PCI_VENDOR_ID_MYRICOM 0x14c1 #define PCI_VENDOR_ID_MEDIATEK 0x14c3 +#define PCI_DEVICE_ID_MEDIATEK_7629 0x7629 #define PCI_VENDOR_ID_TITAN 0x14D2 #define PCI_DEVICE_ID_TITAN_010L 0x8001