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Thu, 6 Dec 2018 01:11:09 -0800 Received: from mircea-Latitude-E6540.analog.com (10.50.1.101) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 6 Dec 2018 04:11:08 -0500 From: Mircea Caprioru To: CC: , , , , , , , , Mircea Caprioru Subject: [PATCH 1/2] staging: iio: adc: ad7192: Add clock for external clock reference Date: Thu, 6 Dec 2018 11:10:51 +0200 Message-ID: <20181206091052.7644-1-mircea.caprioru@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39860400002)(396003)(136003)(346002)(376002)(2980300002)(199004)(189003)(478600001)(6916009)(8936002)(305945005)(1076002)(50226002)(7636002)(5660300001)(426003)(336012)(8676002)(356004)(6666004)(106002)(107886003)(72206003)(53416004)(2616005)(36756003)(476003)(126002)(16586007)(54906003)(486006)(4326008)(7696005)(186003)(86362001)(246002)(51416003)(14444005)(316002)(2906002)(44832011)(47776003)(48376002)(50466002)(77096007)(2351001)(26005)(106466001);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR03MB3132;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;A:1;MX:1; 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This modifications is in accordance with clock framework dt bindings documentation. Signed-off-by: Mircea Caprioru --- drivers/staging/iio/adc/ad7192.c | 74 +++++++++++++++++++++----------- drivers/staging/iio/adc/ad7192.h | 2 - 2 files changed, 50 insertions(+), 26 deletions(-) diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index acdbc07fd259..8a4e6ede42b3 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -6,6 +6,7 @@ * Licensed under the GPL-2. */ +#include #include #include #include @@ -156,8 +157,9 @@ struct ad7192_state { struct regulator *avdd; struct regulator *dvdd; + struct clk *mclk; u16 int_vref_mv; - u32 mclk; + u32 fclk; u32 f_order; u32 mode; u32 conf; @@ -165,6 +167,7 @@ struct ad7192_state { u8 gpocon; u8 devid; struct mutex lock; /* protect sensor state */ + u8 clock_sel; struct ad_sigma_delta sd; }; @@ -250,28 +253,8 @@ static int ad7192_setup(struct ad7192_state *st, dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", id); - switch (pdata->clock_source_sel) { - case AD7192_CLK_INT: - case AD7192_CLK_INT_CO: - st->mclk = AD7192_INT_FREQ_MHZ; - break; - case AD7192_CLK_EXT_MCLK1_2: - case AD7192_CLK_EXT_MCLK2: - if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) { - st->mclk = pdata->ext_clk_hz; - break; - } - dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n", - pdata->ext_clk_hz); - ret = -EINVAL; - goto out; - default: - ret = -EINVAL; - goto out; - } - st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | - AD7192_MODE_CLKSRC(pdata->clock_source_sel) | + AD7192_MODE_CLKSRC(st->clock_sel) | AD7192_MODE_RATE(480); st->conf = AD7192_CONF_GAIN(0); @@ -499,7 +482,7 @@ static int ad7192_read_raw(struct iio_dev *indio_dev, *val -= 273 * ad7192_get_temp_scale(unipolar); return IIO_VAL_INT; case IIO_CHAN_INFO_SAMP_FREQ: - *val = st->mclk / + *val = st->fclk / (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); return IIO_VAL_INT; } @@ -546,7 +529,7 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, break; } - div = st->mclk / (val * st->f_order * 1024); + div = st->fclk / (val * st->f_order * 1024); if (div < 1 || div > 1023) { ret = -EINVAL; break; @@ -625,6 +608,42 @@ static const struct iio_chan_spec ad7193_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(14), }; +static int ad7192_clock_select(struct spi_device *spi, struct ad7192_state *st) +{ + int ret; + + st->clock_sel = AD7192_CLK_EXT_MCLK2; + st->mclk = devm_clk_get(&spi->dev, "clk"); + if (IS_ERR(st->mclk)) { + if (PTR_ERR(st->mclk) != -ENOENT) + return PTR_ERR(st->mclk); + + /* try xtal option */ + st->mclk = devm_clk_get(&spi->dev, "xtal"); + st->clock_sel = AD7192_CLK_EXT_MCLK1_2; + if (IS_ERR(st->mclk)) { + if (PTR_ERR(st->mclk) != -ENOENT) + return PTR_ERR(st->mclk); + + /* use internal clock */ + st->clock_sel = AD7192_CLK_INT; + st->fclk = AD7192_INT_FREQ_MHZ; + } + } + if (st->clock_sel == AD7192_CLK_EXT_MCLK2 || + st->clock_sel == AD7192_CLK_EXT_MCLK1_2) { + ret = clk_prepare_enable(st->mclk); + if (ret < 0) + return ret; + + st->fclk = clk_get_rate(st->mclk); + if (!ad7192_valid_external_frequency(st->fclk)) + return -EINVAL; + } + + return 0; +} + static int ad7192_probe(struct spi_device *spi) { const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev); @@ -672,6 +691,10 @@ static int ad7192_probe(struct spi_device *spi) goto error_disable_avdd; } + ret = ad7192_clock_select(spi, st); + if (ret < 0) + goto error_clk_disable_unprepare; + voltage_uv = regulator_get_voltage(st->avdd); if (pdata->vref_mv) @@ -720,6 +743,8 @@ static int ad7192_probe(struct spi_device *spi) error_remove_trigger: ad_sd_cleanup_buffer_and_trigger(indio_dev); +error_clk_disable_unprepare: + clk_disable_unprepare(st->mclk); error_disable_dvdd: regulator_disable(st->dvdd); error_disable_avdd: @@ -735,6 +760,7 @@ static int ad7192_remove(struct spi_device *spi) iio_device_unregister(indio_dev); ad_sd_cleanup_buffer_and_trigger(indio_dev); + clk_disable_unprepare(st->mclk); regulator_disable(st->dvdd); regulator_disable(st->avdd); diff --git a/drivers/staging/iio/adc/ad7192.h b/drivers/staging/iio/adc/ad7192.h index 7433a43c2611..3be3ee269ed5 100644 --- a/drivers/staging/iio/adc/ad7192.h +++ b/drivers/staging/iio/adc/ad7192.h @@ -33,8 +33,6 @@ struct ad7192_platform_data { u16 vref_mv; - u8 clock_source_sel; - u32 ext_clk_hz; bool refin2_en; bool rej60_en; bool sinc3_en; From patchwork Thu Dec 6 09:10:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mircea Caprioru X-Patchwork-Id: 10715463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7782414E2 for ; Thu, 6 Dec 2018 09:11:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61B3F2DB31 for ; Thu, 6 Dec 2018 09:11:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 52E8B2E61F; Thu, 6 Dec 2018 09:11:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE01E2DB31 for ; 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This patch adds a dt binding for enabling this property. Signed-off-by: Mircea Caprioru --- drivers/staging/iio/adc/ad7192.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index 8a4e6ede42b3..a11c8a82bb7c 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -611,6 +611,10 @@ static const struct iio_chan_spec ad7193_channels[] = { static int ad7192_clock_select(struct spi_device *spi, struct ad7192_state *st) { int ret; + bool clock_out_en; + + clock_out_en = of_property_read_bool(spi->dev.of_node, + "adi,int-clock-output-enable"); st->clock_sel = AD7192_CLK_EXT_MCLK2; st->mclk = devm_clk_get(&spi->dev, "clk"); @@ -626,7 +630,10 @@ static int ad7192_clock_select(struct spi_device *spi, struct ad7192_state *st) return PTR_ERR(st->mclk); /* use internal clock */ - st->clock_sel = AD7192_CLK_INT; + if (!clock_out_en) + st->clock_sel = AD7192_CLK_INT; + else + st->clock_sel = AD7192_CLK_INT_CO; st->fclk = AD7192_INT_FREQ_MHZ; } }