From patchwork Wed Aug 4 01:23:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 12417713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49CBC4320A for ; Wed, 4 Aug 2021 01:05:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9655160EE9 for ; Wed, 4 Aug 2021 01:05:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9655160EE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE01789F24; Wed, 4 Aug 2021 01:05:49 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9778189F24; Wed, 4 Aug 2021 01:05:14 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="274873913" X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="274873913" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:13 -0700 X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="670732229" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:12 -0700 From: Matthew Brost To: Cc: Date: Tue, 3 Aug 2021 18:23:01 -0700 Message-Id: <20210804012303.158392-2-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210804012303.158392-1-matthew.brost@intel.com> References: <20210804012303.158392-1-matthew.brost@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/3] i915/gem_exec_schedule: Make gem_exec_schedule understand static priority mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The i915 currently has 2k visible priority levels which are currently unique. This is changing to statically map these 2k levels into 3 buckets: low: < 0 mid: 0 high: > 0 Update gem_exec_schedule to understand this. This entails updating promotion test to use 3 levels that will map into different buckets and also add bit of delay after releasing a cork beforing completing the spinners. Also skip any tests that rely on having more than 3 priority levels. v2: Add a delay between starting releasing spinner and cork in promotion, add local define for static mapping engine info Signed-off-by: Matthew Brost --- lib/i915/gem_scheduler.c | 14 ++++++++ lib/i915/gem_scheduler.h | 1 + lib/i915/i915_drm_local.h | 10 ++++++ tests/i915/gem_exec_schedule.c | 62 +++++++++++++++++++++------------- 4 files changed, 63 insertions(+), 24 deletions(-) diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c index cdddf42ad..d006b8676 100644 --- a/lib/i915/gem_scheduler.c +++ b/lib/i915/gem_scheduler.c @@ -28,6 +28,7 @@ #include "igt_core.h" #include "ioctl_wrappers.h" +#include "i915/i915_drm_local.h" #include "i915/gem_scheduler.h" #include "i915/gem_submission.h" @@ -90,6 +91,19 @@ bool gem_scheduler_has_ctx_priority(int fd) I915_SCHEDULER_CAP_PRIORITY; } +/** + * gem_scheduler_has_static_priority: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query whether the driver supports priority assigned + * from user space are statically mapping into 3 buckets. + */ +bool gem_scheduler_has_static_priority(int fd) +{ + return gem_scheduler_capability(fd) & + I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP; +} + /** * gem_scheduler_has_preemption: * @fd: open i915 drm file descriptor diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h index d43e84bd2..b00804f70 100644 --- a/lib/i915/gem_scheduler.h +++ b/lib/i915/gem_scheduler.h @@ -29,6 +29,7 @@ unsigned gem_scheduler_capability(int fd); bool gem_scheduler_enabled(int fd); bool gem_scheduler_has_ctx_priority(int fd); +bool gem_scheduler_has_static_priority(int fd); bool gem_scheduler_has_preemption(int fd); bool gem_scheduler_has_semaphores(int fd); bool gem_scheduler_has_engine_busy_stats(int fd); diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h index dd646aedf..a1527ff21 100644 --- a/lib/i915/i915_drm_local.h +++ b/lib/i915/i915_drm_local.h @@ -20,6 +20,16 @@ extern "C" { * clean these up when kernel uapi headers are sync'd. */ +/* + * Indicates the 2k user priority levels are statically mapped into 3 buckets as + * follows: + * + * -1k to -1 Low priority + * 0 Normal priority + * 1 to 1k Highest priority + */ +#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) + #if defined(__cplusplus) } #endif diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index e5fb45982..bb9fb6c14 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -199,7 +199,8 @@ create_highest_priority(int fd, const intel_ctx_cfg_t *cfg) static void unplug_show_queue(int fd, struct igt_cork *c, const intel_ctx_cfg_t *cfg, - unsigned int engine) + unsigned int engine, + unsigned usec_delay) { igt_spin_t *spin[MAX_ELSP_QLEN]; int max = MAX_ELSP_QLEN; @@ -216,6 +217,7 @@ static void unplug_show_queue(int fd, struct igt_cork *c, igt_cork_unplug(c); /* batches will now be queued on the engine */ igt_debugfs_dump(fd, "i915_engine_info"); + usleep(usec_delay); for (int n = 0; n < max; n++) igt_spin_free(fd, spin[n]); @@ -237,7 +239,7 @@ static void fifo(int fd, const intel_ctx_t *ctx, unsigned ring) store_dword_fenced(fd, ctx, ring, scratch, 0, 1, fence, 0); store_dword_fenced(fd, ctx, ring, scratch, 0, 2, fence, 0); - unplug_show_queue(fd, &cork, &ctx->cfg, ring); + unplug_show_queue(fd, &cork, &ctx->cfg, ring, 0); close(fence); result = __sync_read_u32(fd, scratch, 0); @@ -298,7 +300,7 @@ static void implicit_rw(int i915, const intel_ctx_t *ctx, unsigned int ring, ring, scratch, 0, ring, fence, I915_GEM_DOMAIN_RENDER); - unplug_show_queue(i915, &cork, &ctx->cfg, ring); + unplug_show_queue(i915, &cork, &ctx->cfg, ring, 0); close(fence); result = __sync_read_u32(i915, scratch, 0); @@ -355,7 +357,7 @@ static void independent(int fd, const intel_ctx_t *ctx, unsigned int engine, /* Same priority, but different timeline (as different engine) */ batch = __store_dword(fd, ctx, engine, scratch, 0, engine, 0, fence, 0); - unplug_show_queue(fd, &cork, &ctx->cfg, engine); + unplug_show_queue(fd, &cork, &ctx->cfg, engine, 0); close(fence); gem_sync(fd, batch); @@ -1326,7 +1328,7 @@ static void reorder(int fd, const intel_ctx_cfg_t *cfg, store_dword_fenced(fd, ctx[LO], ring, scratch, 0, ctx[LO]->id, fence, 0); store_dword_fenced(fd, ctx[HI], ring, scratch, 0, ctx[HI]->id, fence, 0); - unplug_show_queue(fd, &cork, cfg, ring); + unplug_show_queue(fd, &cork, cfg, ring, 0); close(fence); result = __sync_read_u32(fd, scratch, 0); @@ -1353,10 +1355,10 @@ static void promotion(int fd, const intel_ctx_cfg_t *cfg, unsigned ring) gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO); ctx[HI] = intel_ctx_create(fd, cfg); - gem_context_set_priority(fd, ctx[HI]->id, 0); + gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO); ctx[NOISE] = intel_ctx_create(fd, cfg); - gem_context_set_priority(fd, ctx[NOISE]->id, MIN_PRIO/2); + gem_context_set_priority(fd, ctx[NOISE]->id, 0); result = gem_create(fd, 4096); dep = gem_create(fd, 4096); @@ -1377,7 +1379,7 @@ static void promotion(int fd, const intel_ctx_cfg_t *cfg, unsigned ring) store_dword(fd, ctx[HI], ring, result, 0, ctx[HI]->id, 0); - unplug_show_queue(fd, &cork, cfg, ring); + unplug_show_queue(fd, &cork, cfg, ring, 250000); close(fence); dep_read = __sync_read_u32(fd, dep, 0); @@ -1893,7 +1895,7 @@ static void deep(int fd, const intel_ctx_cfg_t *cfg, igt_info("Second deptree: %d requests [%.3fs]\n", n * XS, 1e-9*igt_nsec_elapsed(&tv)); - unplug_show_queue(fd, &cork, cfg, ring); + unplug_show_queue(fd, &cork, cfg, ring, 0); gem_close(fd, plug); igt_require(expected); /* too slow */ @@ -1962,7 +1964,7 @@ static void wide(int fd, const intel_ctx_cfg_t *cfg, unsigned ring) igt_info("Submitted %d requests over %d contexts in %.1fms\n", count, MAX_CONTEXTS, igt_nsec_elapsed(&tv) * 1e-6); - unplug_show_queue(fd, &cork, cfg, ring); + unplug_show_queue(fd, &cork, cfg, ring, 0); close(fence); __sync_read_u32_count(fd, result, result_read, sizeof(result_read)); @@ -2067,7 +2069,7 @@ static void reorder_wide(int fd, const intel_ctx_cfg_t *cfg, unsigned ring) intel_ctx_destroy(fd, tmp_ctx); } - unplug_show_queue(fd, &cork, cfg, ring); + unplug_show_queue(fd, &cork, cfg, ring, 0); close(fence); __sync_read_u32_count(fd, result, result_read, sizeof(result_read)); @@ -2963,19 +2965,25 @@ igt_main test_each_engine_store("preempt-other-chain", fd, ctx, e) preempt_other(fd, &ctx->cfg, e->flags, CHAIN); - test_each_engine_store("preempt-queue", fd, ctx, e) - preempt_queue(fd, &ctx->cfg, e->flags, 0); + test_each_engine_store("preempt-engines", fd, ctx, e) + preempt_engines(fd, e, 0); - test_each_engine_store("preempt-queue-chain", fd, ctx, e) - preempt_queue(fd, &ctx->cfg, e->flags, CHAIN); - test_each_engine_store("preempt-queue-contexts", fd, ctx, e) - preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS); + igt_subtest_group { + igt_fixture { + igt_require(!gem_scheduler_has_static_priority(fd)); + } - test_each_engine_store("preempt-queue-contexts-chain", fd, ctx, e) - preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS | CHAIN); + test_each_engine_store("preempt-queue", fd, ctx, e) + preempt_queue(fd, &ctx->cfg, e->flags, 0); - test_each_engine_store("preempt-engines", fd, ctx, e) - preempt_engines(fd, e, 0); + test_each_engine_store("preempt-queue-chain", fd, ctx, e) + preempt_queue(fd, &ctx->cfg, e->flags, CHAIN); + test_each_engine_store("preempt-queue-contexts", fd, ctx, e) + preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS); + + test_each_engine_store("preempt-queue-contexts-chain", fd, ctx, e) + preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS | CHAIN); + } igt_subtest_group { igt_hang_t hang; @@ -3017,11 +3025,17 @@ igt_main test_each_engine_store("wide", fd, ctx, e) wide(fd, &ctx->cfg, e->flags); - test_each_engine_store("reorder-wide", fd, ctx, e) - reorder_wide(fd, &ctx->cfg, e->flags); - test_each_engine_store("smoketest", fd, ctx, e) smoketest(fd, &ctx->cfg, e->flags, 5); + + igt_subtest_group { + igt_fixture { + igt_require(!gem_scheduler_has_static_priority(fd)); + } + + test_each_engine_store("reorder-wide", fd, ctx, e) + reorder_wide(fd, &ctx->cfg, e->flags); + } } igt_subtest_group { From patchwork Wed Aug 4 01:23:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 12417717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9BEAC4338F for ; Wed, 4 Aug 2021 01:06:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9485760EE9 for ; Wed, 4 Aug 2021 01:06:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9485760EE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58767891DD; Wed, 4 Aug 2021 01:06:42 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C9B6C6E9A0; Wed, 4 Aug 2021 01:05:19 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="274873915" X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="274873915" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:14 -0700 X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="670732231" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:12 -0700 From: Matthew Brost To: Cc: Date: Tue, 3 Aug 2021 18:23:02 -0700 Message-Id: <20210804012303.158392-3-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210804012303.158392-1-matthew.brost@intel.com> References: <20210804012303.158392-1-matthew.brost@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 2/3] i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The i915 currently has 2k visible priority levels which are currently unique. This is changing to statically map these 2k levels into 3 buckets: low: < 0 mid: 0 high: > 0 Update gem_ctx_shared to understand this. This entails updating promotion test to use 3 levels that will map into different buckets and also add bit of delay after releasing a cork beforing completing the spinners. v2: Add a delay between starting releasing spinner and cork in promotion Signed-off-by: Matthew Brost --- tests/i915/gem_ctx_shared.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 4441e6eb7..b3a156ca4 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -571,7 +571,8 @@ create_highest_priority(int i915, const intel_ctx_cfg_t *cfg) } static void unplug_show_queue(int i915, struct igt_cork *c, - const intel_ctx_cfg_t *cfg, unsigned int engine) + const intel_ctx_cfg_t *cfg, unsigned int engine, + unsigned int usec_delay) { igt_spin_t *spin[MAX_ELSP_QLEN]; @@ -583,6 +584,7 @@ static void unplug_show_queue(int i915, struct igt_cork *c, igt_cork_unplug(c); /* batches will now be queued on the engine */ igt_debugfs_dump(i915, "i915_engine_info"); + usleep(usec_delay); for (int n = 0; n < ARRAY_SIZE(spin); n++) igt_spin_free(i915, spin[n]); @@ -734,7 +736,7 @@ static void reorder(int i915, const intel_ctx_cfg_t *cfg, store_dword(i915, ctx[LO], ring, scratch, 0, ctx[LO]->id, plug, 0); store_dword(i915, ctx[HI], ring, scratch, 0, ctx[HI]->id, plug, 0); - unplug_show_queue(i915, &cork, &q_cfg, ring); + unplug_show_queue(i915, &cork, &q_cfg, ring, 0); gem_close(i915, plug); ptr = gem_mmap__device_coherent(i915, scratch, 0, 4096, PROT_READ); @@ -771,10 +773,10 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO); ctx[HI] = intel_ctx_create(i915, &q_cfg); - gem_context_set_priority(i915, ctx[HI]->id, 0); + gem_context_set_priority(i915, ctx[HI]->id, MAX_PRIO); ctx[NOISE] = intel_ctx_create(i915, &q_cfg); - gem_context_set_priority(i915, ctx[NOISE]->id, MIN_PRIO/2); + gem_context_set_priority(i915, ctx[NOISE]->id, 0); result = gem_create(i915, 4096); dep = gem_create(i915, 4096); @@ -795,7 +797,7 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) store_dword(i915, ctx[HI], ring, result, 0, ctx[HI]->id, 0, 0); - unplug_show_queue(i915, &cork, &q_cfg, ring); + unplug_show_queue(i915, &cork, &q_cfg, ring, 250000); gem_close(i915, plug); ptr = gem_mmap__device_coherent(i915, dep, 0, 4096, PROT_READ); From patchwork Wed Aug 4 01:23:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 12417715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59466C4338F for ; Wed, 4 Aug 2021 01:06:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1DB5760EE9 for ; Wed, 4 Aug 2021 01:06:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1DB5760EE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A90056E9A0; Wed, 4 Aug 2021 01:06:12 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2846A6E9A1; Wed, 4 Aug 2021 01:05:21 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10065"; a="274873916" X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="274873916" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:14 -0700 X-IronPort-AV: E=Sophos;i="5.84,293,1620716400"; d="scan'208";a="670732232" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2021 18:05:12 -0700 From: Matthew Brost To: Cc: Date: Tue, 3 Aug 2021 18:23:03 -0700 Message-Id: <20210804012303.158392-4-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210804012303.158392-1-matthew.brost@intel.com> References: <20210804012303.158392-1-matthew.brost@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_capture: Update to support GuC based resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Signed-off-by: John Harrison" When GuC submission is enabled, GuC itself manages hang detection and recovery. Therefore, any test that relies on being able to trigger an engine reset in the driver will fail. Full GT resets can still be triggered by the driver, however in that situation detecting the specific context that caused a hang is not possible as the driver has no information about what is actually running on the hardware at any given time. So update the test to cause a reset via a the hangcheck mechanism by submitting a hanging batch and waiting. That way it is guaranteed to be testing the correct reset code paths for the current platform, whether that is GuC enabled or not. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- lib/igt_gt.c | 44 +++++++++++++++++++---------- lib/igt_gt.h | 1 + tests/i915/gem_exec_capture.c | 52 +++++++++++++++++++++++++++++------ 3 files changed, 74 insertions(+), 23 deletions(-) diff --git a/lib/igt_gt.c b/lib/igt_gt.c index c049477db..ec548d501 100644 --- a/lib/igt_gt.c +++ b/lib/igt_gt.c @@ -56,23 +56,28 @@ * engines. */ +static int reset_query_once = -1; + static bool has_gpu_reset(int fd) { - static int once = -1; - if (once < 0) { - struct drm_i915_getparam gp; - int val = 0; - - memset(&gp, 0, sizeof(gp)); - gp.param = 35; /* HAS_GPU_RESET */ - gp.value = &val; - - if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp)) - once = intel_gen(intel_get_drm_devid(fd)) >= 5; - else - once = val > 0; + if (reset_query_once < 0) { + reset_query_once = gem_gpu_reset_type(fd); + + /* Very old kernels did not support the query */ + if (reset_query_once == -1) + reset_query_once = + (intel_gen(intel_get_drm_devid(fd)) >= 5) ? 1 : 0; } - return once; + + return reset_query_once > 0; +} + +static bool has_engine_reset(int fd) +{ + if (reset_query_once < 0) + has_gpu_reset(fd); + + return reset_query_once > 1; } static void eat_error_state(int dev) @@ -176,7 +181,11 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned flags) igt_skip("hang injection disabled by user [IGT_HANG=0]\n"); gem_context_require_bannable(fd); - allow_reset = 1; + if (flags & HANG_WANT_ENGINE_RESET) + allow_reset = 2; + else + allow_reset = 1; + if ((flags & HANG_ALLOW_CAPTURE) == 0) { param.param = I915_CONTEXT_PARAM_NO_ERROR_CAPTURE; param.value = 1; @@ -187,11 +196,16 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned flags) __gem_context_set_param(fd, ¶m); allow_reset = INT_MAX; /* any reset method */ } + igt_require(igt_params_set(fd, "reset", "%d", allow_reset)); + reset_query_once = -1; /* Re-query after changing param */ if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false)) igt_require(has_gpu_reset(fd)); + if (flags & HANG_WANT_ENGINE_RESET) + igt_require(has_engine_reset(fd)); + ban = context_get_ban(fd, ctx); if ((flags & HANG_ALLOW_BAN) == 0) context_set_ban(fd, ctx, 0); diff --git a/lib/igt_gt.h b/lib/igt_gt.h index d87fae2d3..d806c4b80 100644 --- a/lib/igt_gt.h +++ b/lib/igt_gt.h @@ -48,6 +48,7 @@ void igt_disallow_hang(int fd, igt_hang_t arg); igt_hang_t igt_hang_ctx(int fd, uint32_t ctx, int ring, unsigned flags); #define HANG_ALLOW_BAN 1 #define HANG_ALLOW_CAPTURE 2 +#define HANG_WANT_ENGINE_RESET 4 igt_hang_t igt_hang_ring(int fd, int ring); void igt_post_hang_ring(int fd, igt_hang_t arg); diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c index f59cb09da..6ae4208ce 100644 --- a/tests/i915/gem_exec_capture.c +++ b/tests/i915/gem_exec_capture.c @@ -23,6 +23,7 @@ #include #include +#include #include "i915/gem.h" #include "i915/gem_create.h" @@ -31,8 +32,16 @@ #include "igt_rand.h" #include "igt_sysfs.h" +#define MAX_RESET_TIME 120 + IGT_TEST_DESCRIPTION("Check that we capture the user specified objects on a hang"); +static void configure_engine(int fd, const char *name) +{ + gem_engine_property_printf(fd, name, "preempt_timeout_ms", "%d", 250); + gem_engine_property_printf(fd, name, "heartbeat_interval_ms", "%d", 500); +} + static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj) { char *error, *str; @@ -61,8 +70,13 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj) igt_assert(found); } +static bool fence_busy(int fence) +{ + return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0; +} + static void __capture1(int fd, int dir, const intel_ctx_t *ctx, - unsigned ring, uint32_t target) + unsigned ring, uint32_t target, const char *name) { const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); struct drm_i915_gem_exec_object2 obj[4]; @@ -74,6 +88,10 @@ static void __capture1(int fd, int dir, const intel_ctx_t *ctx, struct drm_i915_gem_execbuffer2 execbuf; uint32_t *batch, *seqno; int i; + int fence_out; + struct timeval before, after, delta; + + configure_engine(fd, name); memset(obj, 0, sizeof(obj)); obj[SCRATCH].handle = gem_create(fd, 4096); @@ -149,18 +167,34 @@ static void __capture1(int fd, int dir, const intel_ctx_t *ctx, execbuf.flags = ring; if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; + execbuf.flags |= I915_EXEC_FENCE_OUT; + execbuf.rsvd2 = ~0UL; execbuf.rsvd1 = ctx->id; igt_assert(!READ_ONCE(*seqno)); - gem_execbuf(fd, &execbuf); + gem_execbuf_wr(fd, &execbuf); + + fence_out = execbuf.rsvd2 >> 32; + igt_assert(fence_out >= 0); /* Wait for the request to start */ while (READ_ONCE(*seqno) != 0xc0ffee) igt_assert(gem_bo_busy(fd, obj[SCRATCH].handle)); munmap(seqno, 4096); + /* Wait for a reset to occur */ + gettimeofday(&before, NULL); + while (fence_busy(fence_out)) { + gettimeofday(&after, NULL); + timersub(&after, &before, &delta); + igt_assert(delta.tv_sec < MAX_RESET_TIME); + sched_yield(); + } + gettimeofday(&after, NULL); + timersub(&after, &before, &delta); + igt_info("Target died after %ld.%06lds\n", delta.tv_sec, delta.tv_usec); + /* Check that only the buffer we marked is reported in the error */ - igt_force_gpu_reset(fd); check_error_state(dir, &obj[CAPTURE]); gem_sync(fd, obj[BATCH].handle); @@ -170,12 +204,13 @@ static void __capture1(int fd, int dir, const intel_ctx_t *ctx, gem_close(fd, obj[SCRATCH].handle); } -static void capture(int fd, int dir, const intel_ctx_t *ctx, unsigned ring) +static void capture(int fd, int dir, const intel_ctx_t *ctx, + const struct intel_execution_engine2 *e) { uint32_t handle; handle = gem_create(fd, 4096); - __capture1(fd, dir, ctx, ring, handle); + __capture1(fd, dir, ctx, e->flags, handle, e->name); gem_close(fd, handle); } @@ -577,7 +612,7 @@ static void userptr(int fd, int dir) igt_assert(posix_memalign(&ptr, 4096, 4096) == 0); igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0); - __capture1(fd, dir, intel_ctx_0(fd), 0, handle); + __capture1(fd, dir, intel_ctx_0(fd), 0, handle, "bcs0"); gem_close(fd, handle); free(ptr); @@ -626,7 +661,8 @@ igt_main gem_require_mmap_wc(fd); igt_require(has_capture(fd)); ctx = intel_ctx_create_all_physical(fd); - igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE); + igt_allow_hang(fd, 0, HANG_ALLOW_CAPTURE | + HANG_WANT_ENGINE_RESET); dir = igt_sysfs_open(fd); igt_require(igt_sysfs_set(dir, "error", "Begone!")); @@ -634,7 +670,7 @@ igt_main } test_each_engine("capture", fd, ctx, e) - capture(fd, dir, ctx, e->flags); + capture(fd, dir, ctx, e); igt_subtest_f("many-4K-zero") { igt_require(gem_can_store_dword(fd, 0));