From patchwork Fri Aug 6 18:18:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12423757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DF1DC4338F for ; Fri, 6 Aug 2021 18:20:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF68561184 for ; Fri, 6 Aug 2021 18:20:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EF68561184 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Mime-Version: Message-Id:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=1MEgeyo4N/GOT5lPlnCXfNhReRNIb4/WUu+Bdq4lPiY=; b=LYM jG9Cnq7z+9j1331q37qg8LC1LPK1qvVkeutY2/gsDEpkbo8DUvIXudS7o+XYzkySMecE4oaL+GAtw LK0Y2rxKW9y3+CNJwLJ8Y67eIdcbAL65WTF06KzfGeW/+7bXSpksHtpchqr5OsOSiFFVe430kT+Oc 0ahNUVWrm1EAQ1aXCDf9ng3v31KCMJ/w5cNSdsm+q+YdswUvxMWTDmZCm5Hq0tGDQIYktCCqP2Krn Cj6zjvTkthZqqbnadBwVi7oa5sreW5+S+wjoyHobU70fhE4EI2M7pja4XbTEwWvAW1UNS2RNHUKfN lwCWs5NEu1hx9Dzk0RiEr3mVoiSMv7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mC4R6-00D7IQ-6l; Fri, 06 Aug 2021 18:19:12 +0000 Received: from mail-io1-xd49.google.com ([2607:f8b0:4864:20::d49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mC4R1-00D7H2-Do for linux-arm-kernel@lists.infradead.org; Fri, 06 Aug 2021 18:19:08 +0000 Received: by mail-io1-xd49.google.com with SMTP id k20-20020a6b6f140000b029053817be16cdso6401783ioc.3 for ; Fri, 06 Aug 2021 11:19:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:message-id:mime-version:subject:from:to:cc; bh=4pt7QhWVdBAZAccNLJ7Co0Ahi/sO10ASBjVGlHUl104=; b=TjlQFXYBQNkXFps/LJl9th2cCqZwh9wckjZhg8+93+RDK9kLNxPtlAWMkFw2jSQA19 QFCfZVmc0tZvKuATbvgkPOmRYvh4iYAnZgttZq3EwPdlO1+XVnyDfpZXIGjinuCn6+bp ceaLKPKw4cLSFABsChUYGBjEqoePv5lkOc12KtgQEQUQMK8mXo3wvIYmbKu5P8QCyIgF u/LjcDMsxvrGsJx8kyZ1Mt+rk3vAOZdWzRYOPHFOVealOwHLAHN0w1nae3rvbuWFkZH5 GRbwu2ATnK7V089cVHG/nayW445reL3jHhNPM9LRs94xFmwUA20G/kUg6BhQdlAYAMEu /Kzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=4pt7QhWVdBAZAccNLJ7Co0Ahi/sO10ASBjVGlHUl104=; b=A5sOJkYu62c/a3YUeC/3+CdJiKQug8Z4ACurkBNiWVY0Vea4pIUlAiwLtCxVrISnTs forqXAzU6wQAwvWuJ5dQ3JLtwig5vBchYwXx97NaQZucBwkzEXXPMlIUlOuDZaXl1qUZ M4gh0IfUQGcmVjnu2Lcsg7UJwxDvkN9q+jHnwMZAE14gtxOxSmWFoUF5VD1Jq+BpyyrT r9UhQtwdzhW5144CeOAIy9vRd6tvwrkgf3gCiNJgTy7jfjVXvm73sZa0WlzxaTN4usva QyK0dzSdniWSKH39I9nHpMo8tWbPdDQeTTNmprhMZduIkziJuIqUWbS4SNkCtssheOAJ 9b5g== X-Gm-Message-State: AOAM530tUu+fXG+PoQj+DPetQju2HWdn8EdlYh8iwRcZscYiDhs0EAR/ ubHghNOvAm9VRF1V+EQtB/Oibgj8C3uTGJ02fWmqYC9yHowG/1uRvCeliLujSH0q41Jg5kb47tu pMY+F5ACmOdHp7IMSuZuFGGsRANUinVPWg/t2IWdbvP97vZzGeK0tPJir0QhPdi3D5HOp99eLXj W6bUXO X-Google-Smtp-Source: ABdhPJy9OszBxX0krnUQ0z3p9cmQEBtU97V6NU0I2norm2BVKVMMk50x+78rJsrwF6IIcSFTjWxg4Qud3mE= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a5d:8b51:: with SMTP id c17mr73477iot.119.1628273943313; Fri, 06 Aug 2021 11:19:03 -0700 (PDT) Date: Fri, 6 Aug 2021 18:18:55 +0000 Message-Id: <20210806181855.2841629-1-oupton@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.605.g8dce9f2422-goog Subject: [PATCH] clocksource/arm_arch_timer: Fix masking for high freq counters From: Oliver Upton To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Mark Rutland , Marc Zyngier , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210806_111907_554307_3AB86702 X-CRM114-Status: GOOD ( 20.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unfortunately, the architecture provides no means to determine the bit width of the system counter. However, we do know the following from the specification: - the system counter is at least 56 bits wide - Roll-over time of not less than 40 years To date, the arch timer driver has depended on the first property, assuming any system counter to be 56 bits wide and masking off the rest. However, combining a narrow clocksource mask with a high frequency counter could result in prematurely wrapping the system counter by a significant margin. For example, a 56 bit wide, 1GHz system counter would wrap in a mere 2.28 years! This is a problem for two reasons: v8.6+ implementations are required to provide a 64 bit, 1GHz system counter. Furthermore, before v8.6, implementers may select a counter frequency of their choosing. Fix the issue by deriving a valid clock mask based on the second property from above. Set the floor at 56 bits, since we know no system counter is narrower than that. Suggested-by: Marc Zyngier Signed-off-by: Oliver Upton --- This patch was tested with QEMU, tweaked to provide a 1GHz system counter frequency, as I could not easily figure out how to tweak the base FVP to provide a 1GHz counter. Parent commit: 0c32706dac1b ("arm64: stacktrace: avoid tracing arch_stack_walk()") drivers/clocksource/arm_arch_timer.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index be6d741d404c..8c41626a4c8a 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -52,6 +52,12 @@ #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c +/* + * The minimum amount of time a generic timer is guaranteed to not roll over + * (40 years) + */ +#define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600) + static unsigned arch_timers_present __initdata; static void __iomem *arch_counter_base __ro_after_init; @@ -1004,9 +1010,24 @@ struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) return &arch_timer_kvm_info; } +/* + * Makes an educated guess at a valid counter width based on the Generic Timer + * specification. Of note: + * 1) the Generic Timer is at least 56 bits wide + * 2) a roll-over time of not less than 40 years + */ +static int __init arch_counter_get_width(void) +{ + u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_get_cntfrq(); + + /* guarantee the returned width is within the valid range */ + return max(56, min(64, ilog2(min_cycles))); +} + static void __init arch_counter_register(unsigned type) { u64 start_count; + int width; /* Register the CP15 based counter if we have one */ if (type & ARCH_TIMER_TYPE_CP15) { @@ -1031,6 +1052,10 @@ static void __init arch_counter_register(unsigned type) arch_timer_read_counter = arch_counter_get_cntvct_mem; } + width = arch_counter_get_width(); + clocksource_counter.mask = CLOCKSOURCE_MASK(width); + cyclecounter.mask = CLOCKSOURCE_MASK(width); + if (!arch_counter_suspend_stop) clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; start_count = arch_timer_read_counter(); @@ -1040,8 +1065,7 @@ static void __init arch_counter_register(unsigned type) timecounter_init(&arch_timer_kvm_info.timecounter, &cyclecounter, start_count); - /* 56 bits minimum, so we assume worst case rollover */ - sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); + sched_clock_register(arch_timer_read_counter, width, arch_timer_rate); } static void arch_timer_stop(struct clock_event_device *clk)