From patchwork Mon Aug 9 19:15:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6373AC4338F for ; Mon, 9 Aug 2021 19:16:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D09260C3E for ; Mon, 9 Aug 2021 19:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236006AbhHITQa (ORCPT ); Mon, 9 Aug 2021 15:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235993AbhHITQ3 (ORCPT ); Mon, 9 Aug 2021 15:16:29 -0400 Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB08FC061799 for ; Mon, 9 Aug 2021 12:16:08 -0700 (PDT) Received: by mail-qt1-x836.google.com with SMTP id c6so9147588qtv.5 for ; Mon, 09 Aug 2021 12:16:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jCUn04Uy/5nEhUoONzVloyladnaZ3tCplSZNJCiC434=; b=PfKTTaJAJJZ2D4KXZhWvd4vKnqpucY/bQjwfimMNiABMITFlT+4h2MrxLamSOR/qc/ XDNtHmk8vjjCnsQAjr5vXmkdTw14nNEXrXQJE6qBlw+3AYcqtny3VZ7+AiCcXrYsdlBM WYBpCWRPMH7GBHCNGSfnJA6sISm25CnRFCniQSaMAOJWTyhin3/R1z2MR6Mb5HpADQZN rkKg2AnFkSTS/OKte9OOmdGAhdQy76cxs7QK5FygYcO1JmB3FzHis4bc0BuM7NQp9R9C MJKz5fRsZcX/6FeYk5f6YVL0gx7pDt5QyOEHIoOohs64dyfxaurKVDU4ZwPZvDDnHKYc 60ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jCUn04Uy/5nEhUoONzVloyladnaZ3tCplSZNJCiC434=; b=kLqt/RQ5dA/Ckq7e0w8BUEW7Y1fQ2H4wnHA4F3rGG7P+v3eEfJsRXNHmQ5w0qC/q9r GxQ3m6CaYsIucPxYTwNDGr7Xawq5ukImtWV1e94fn0NZkx+3Xa57NpICxFNxLVxwEXgw Fi7kLLweikfeALGyNp8QICbP2dzUCDtjHBwrtIAdHzclKAmA3bj4F9GvFVlCxrNsqSW1 wvwbvtVwoaTuaZWz0U2VFE93wJDsWSLeRvM9ipCpctgWVB+KEzg/0prWvuSVZc9mFyeB 2MmTGxEDl+N0fyE4cRHTZAOfHsBspUyYJF/dqv8ugJWp9i+iE9Qa9epxC+5S8qzUIqTB M2Lg== X-Gm-Message-State: AOAM5318JG3ktBzlwN4o75CwvjuH59hSoDA+kqw2wY373is1/AF4ILrf U7/rdEaqxDg0zgIcWu0vUmRAZQ== X-Google-Smtp-Source: ABdhPJyYrBFlubKsm4LysukWo59AZFPq48z6MW4nQhQbxtg2K05KEGkyV1+pvNJ8XuZ07uIOGB2brA== X-Received: by 2002:aed:279e:: with SMTP id a30mr21429912qtd.300.1628536567899; Mon, 09 Aug 2021 12:16:07 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:07 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 1/6] firmware: qcom_scm: Introduce SCM calls to access LMh Date: Mon, 9 Aug 2021 15:15:59 -0400 Message-Id: <20210809191605.3742979-2-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce SCM calls to access/configure limits management hardware(LMH). Reviewed-by: Bjorn Andersson Signed-off-by: Thara Gopinath --- v2->v3: Added freeing of payload_buf after the scm call in qcom_scm_lmh_dcvsh as per Matthias review comments. v1->v2: Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review comments. drivers/firmware/qcom_scm.c | 58 +++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 4 +++ include/linux/qcom_scm.h | 14 +++++++++ 3 files changed, 76 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 47ea2bd42b10..8a503753fe2a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1147,6 +1147,64 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) } EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); +bool qcom_scm_lmh_dcvsh_available(void) +{ + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); + +int qcom_scm_lmh_profile_change(u32 profile_id) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), + .args[0] = profile_id, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_lmh_profile_change); + +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version) +{ + dma_addr_t payload_phys; + u32 *payload_buf; + int ret, payload_size = 5 * sizeof(u32); + + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_LMH, + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_VAL, QCOM_SCM_VAL), + .args[1] = payload_size, + .args[2] = limit_node, + .args[3] = node_id, + .args[4] = version, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); + if (!payload_buf) + return -ENOMEM; + + payload_buf[0] = payload_fn; + payload_buf[1] = 0; + payload_buf[2] = payload_reg; + payload_buf[3] = 1; + payload_buf[4] = payload_val; + + desc.args[0] = payload_phys; + + ret = qcom_scm_call(__scm->dev, &desc, NULL); + + dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys); + return ret; +} +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 632fe3142462..d92156ceb3ac 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -114,6 +114,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 +#define QCOM_SCM_SVC_LMH 0x13 +#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01 +#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 + #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 0165824c5128..c0475d1c9885 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -109,6 +109,12 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version); +extern int qcom_scm_lmh_profile_change(u32 profile_id); +extern bool qcom_scm_lmh_dcvsh_available(void); + #else #include @@ -170,5 +176,13 @@ static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } + +static inline int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version) + { return -ENODEV; } + +static inline int qcom_scm_lmh_profile_change(u32 profile_id) { return -ENODEV; } + +static inline bool qcom_scm_lmh_dcvsh_available(void) { return -ENODEV; } #endif #endif From patchwork Mon Aug 9 19:16:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EB24C4320A for ; Mon, 9 Aug 2021 19:16:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73E9B60EB2 for ; Mon, 9 Aug 2021 19:16:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236000AbhHITQg (ORCPT ); Mon, 9 Aug 2021 15:16:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236001AbhHITQa (ORCPT ); Mon, 9 Aug 2021 15:16:30 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D256EC061799 for ; Mon, 9 Aug 2021 12:16:09 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id e1so7235597qvs.13 for ; Mon, 09 Aug 2021 12:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XB6E4bFMZZgMSfFJQadW9M1Rp4P9hRjq9j714rm3z2g=; b=i0lY7SQm7MEjSadwicd+iFMuhQsBwKGb3zVN7U23umNRt+M71L6wggjtAJCmv/edu7 mDf5+bzLzIjLgA461yjvrvcDjcFjMioJXr3OtypRCMy57wBHmVeoiawhKSlGwWqmBoZl apWjQCNSh7moFztX84BuTyY2R0WstA/NWdjEeABaaWy77+Flvt9MEBEkBM7hm+Dg8AhG aZcBX9TmNTWCpbemMuI3mHoAWevBztmxg6mHrWt20V8o3s5DVnNhNG20Mc0dg0zjWn43 SrttSY0GvSDrqD2cdUhNc4cEYUvwU+vbQR7lcVIZAfTt7BvwYmLHHj/+Lq8WfiqbVTIQ ZAEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XB6E4bFMZZgMSfFJQadW9M1Rp4P9hRjq9j714rm3z2g=; b=DLA07NRHYyh6sBR34RW9gOG7tqHUf6uSMSyFTJmFFMTJGKOEhDdUSWooMK8eksTpic UNHkM7UvwvKQo+X59CN8PA+z33qggo0XvJf5kfXiI7jmWzPHgc3PxFpao9jaUitZ6Aql VvIp94XAEE/gpPUkVl4Q49d1FXpt/axFKCkIG+xTHdJxDOpA9vXHU43i+PgiITivcTfM h4N9Lx/VKWWglVi5BkQAlxrJTSF3dbJ8JM1Z7DA1ipFrJzx3X1GvZ+hhHEZRBFdaliiO igO+0J+DXvFtOh7FmLZPG2VmYDnZQfnXrTuEKyF2ZfpGLik/hoVl+yxkgP4DKw7nvaAj RK9Q== X-Gm-Message-State: AOAM5329idqSEDuWAxjP2jiurUwFqQXv7RBKtCw8OYbNGF0UwmScTfFV GhHfSDJHYiYpP9p79ZybGhajNQ== X-Google-Smtp-Source: ABdhPJy7MvyGZ/vmbXzrVr43QPntZrrb0JqJT9pzd+czsaU5vhBsIiHSaahUymXyCWg4HTPxwowi+A== X-Received: by 2002:a05:6214:923:: with SMTP id dk3mr7192444qvb.38.1628536568908; Mon, 09 Aug 2021 12:16:08 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:08 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 2/6] thermal: qcom: Add support for LMh driver Date: Mon, 9 Aug 2021 15:16:00 -0400 Message-Id: <20210809191605.3742979-3-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Driver enabling various pieces of Limits Management Hardware(LMh) for cpu cluster0 and cpu cluster1 namely kick starting monitoring of temperature, current, battery current violations, enabling reliability algorithm and setting up various temperature limits. The following has been explained in the cover letter. I am including this here so that this remains in the commit message as well. LMh is a hardware infrastructure on some Qualcomm SoCs that can enforce temperature and current limits as programmed by software for certain IPs like CPU. On many newer LMh is configured by firmware/TZ and no programming is needed from the kernel side. But on certain SoCs like sdm845 the firmware does not do a complete programming of the h/w. On such soc's kernel software has to explicitly set up the temperature limits and turn on various monitoring and enforcing algorithms on the hardware. Tested-by: Steev Klimaszewski # Lenovo Yoga C630 Signed-off-by: Thara Gopinath --- v4->v5: - Minor change related to renaming of dt binding property qcom,lmh-cpu to cpus as per Rob Herring's review comments. v3->v4: - Minor code re-arrangement and removal of redundant code as per Bjorn's review comments - Added suppress_bind_attrs to driver as per Bjorn's review comments. - Changes to support changes in LMh dt node properties naming and types. v2->v3: - Rearranged enabling of various LMh subfunction and removed returning on error in enabling any one subfunction as the different pieces can operate and thus be enabled independently. - Other minor cosmetic fixes. v1->v2: - Cosmetic and spelling fixes from review comments from Randy Dunlap - Added irq_disable to lmh_irq_ops and removed disabling of irq from lmh_handle_irq. Now cpufreq explicitly disables irq prior to handling it as per Bjorn's suggestion. - Rebased to new version of qcom_scm_lmh_dcvsh as changed in patch 1. - Removed generic dt compatible string and introduced platform specific one as per Bjorn's suggestion. - Take arm, low and high temp thresholds for LMh from dt properties instead of #defines in the driver as per Daniel's suggestion. - Other minor fixes. drivers/thermal/qcom/Kconfig | 10 ++ drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/lmh.c | 232 ++++++++++++++++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/thermal/qcom/lmh.c diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index 8d5ac2df26dc..7d942f71e532 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -31,3 +31,13 @@ config QCOM_SPMI_TEMP_ALARM trip points. The temperature reported by the thermal sensor reflects the real time die temperature if an ADC is present or an estimate of the temperature based upon the over temperature stage value. + +config QCOM_LMH + tristate "Qualcomm Limits Management Hardware" + depends on ARCH_QCOM + help + This enables initialization of Qualcomm limits management + hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on + input from temperature and current sensors. On many newer Qualcomm SoCs + LMh is configured in the firmware and this feature need not be enabled. + However, on certain SoCs like sdm845 LMh has to be configured from kernel. diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 252ea7d9da0b..0fa2512042e7 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -5,3 +5,4 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o +obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c new file mode 100644 index 000000000000..eafa7526eb8b --- /dev/null +++ b/drivers/thermal/qcom/lmh.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * Copyright (C) 2021, Linaro Limited. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define LMH_NODE_DCVS 0x44435653 +#define LMH_CLUSTER0_NODE_ID 0x6370302D +#define LMH_CLUSTER1_NODE_ID 0x6370312D + +#define LMH_SUB_FN_THERMAL 0x54484D4C +#define LMH_SUB_FN_CRNT 0x43524E54 +#define LMH_SUB_FN_REL 0x52454C00 +#define LMH_SUB_FN_BCL 0x42434C00 + +#define LMH_ALGO_MODE_ENABLE 0x454E424C +#define LMH_TH_HI_THRESHOLD 0x48494748 +#define LMH_TH_LOW_THRESHOLD 0x4C4F5700 +#define LMH_TH_ARM_THRESHOLD 0x41524D00 + +#define LMH_REG_DCVS_INTR_CLR 0x8 + +struct lmh_hw_data { + void __iomem *base; + struct irq_domain *domain; + int irq; +}; + +static irqreturn_t lmh_handle_irq(int hw_irq, void *data) +{ + struct lmh_hw_data *lmh_data = data; + int irq = irq_find_mapping(lmh_data->domain, 0); + + /* Call the cpufreq driver to handle the interrupt */ + if (irq) + generic_handle_irq(irq); + + return 0; +} + +static void lmh_enable_interrupt(struct irq_data *d) +{ + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d); + + /* Clear the existing interrupt */ + writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR); + enable_irq(lmh_data->irq); +} + +static void lmh_disable_interrupt(struct irq_data *d) +{ + struct lmh_hw_data *lmh_data = irq_data_get_irq_chip_data(d); + + disable_irq_nosync(lmh_data->irq); +} + +static struct irq_chip lmh_irq_chip = { + .name = "lmh", + .irq_enable = lmh_enable_interrupt, + .irq_disable = lmh_disable_interrupt +}; + +static int lmh_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + struct lmh_hw_data *lmh_data = d->host_data; + + irq_set_chip_and_handler(irq, &lmh_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, lmh_data); + + return 0; +} + +static const struct irq_domain_ops lmh_irq_ops = { + .map = lmh_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int lmh_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *cpu_node; + struct lmh_hw_data *lmh_data; + int temp_low, temp_high, temp_arm, cpu_id, ret; + u32 node_id; + + lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL); + if (!lmh_data) + return -ENOMEM; + + lmh_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(lmh_data->base)) + return PTR_ERR(lmh_data->base); + + cpu_node = of_parse_phandle(np, "cpus", 0); + if (!cpu_node) + return -EINVAL; + cpu_id = of_cpu_node_to_id(cpu_node); + of_node_put(cpu_node); + + ret = of_property_read_u32(np, "qcom,lmh-temp-high-millicelsius", &temp_high); + if (ret) { + dev_err(dev, "missing qcom,lmh-temp-high-millicelsius property\n"); + return ret; + } + + ret = of_property_read_u32(np, "qcom,lmh-temp-low-millicelsius", &temp_low); + if (ret) { + dev_err(dev, "missing qcom,lmh-temp-low-millicelsius property\n"); + return ret; + } + + ret = of_property_read_u32(np, "qcom,lmh-temp-arm-millicelsius", &temp_arm); + if (ret) { + dev_err(dev, "missing qcom,lmh-temp-arm-millicelsius property\n"); + return ret; + } + + /* + * Only sdm845 has lmh hardware currently enabled from hlos. If this is needed + * for other platforms, revisit this to check if the should be part + * of a dt match table. + */ + if (cpu_id == 0) { + node_id = LMH_CLUSTER0_NODE_ID; + } else if (cpu_id == 4) { + node_id = LMH_CLUSTER1_NODE_ID; + } else { + dev_err(dev, "Wrong CPU id associated with LMh node\n"); + return -EINVAL; + } + + if (!qcom_scm_lmh_dcvsh_available()) + return -EINVAL; + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) + dev_err(dev, "Error %d enabling current subfunction\n", ret); + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) + dev_err(dev, "Error %d enabling reliability subfunction\n", ret); + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) + dev_err(dev, "Error %d enabling BCL subfunction\n", ret); + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error %d enabling thermal subfunction\n", ret); + return ret; + } + + ret = qcom_scm_lmh_profile_change(0x1); + if (ret) { + dev_err(dev, "Error %d changing profile\n", ret); + return ret; + } + + /* Set default thermal trips */ + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret); + return ret; + } + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal HI threshold%d\n", ret); + return ret; + } + + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low, + LMH_NODE_DCVS, node_id, 0); + if (ret) { + dev_err(dev, "Error setting thermal ARM threshold%d\n", ret); + return ret; + } + + lmh_data->irq = platform_get_irq(pdev, 0); + lmh_data->domain = irq_domain_add_linear(np, 1, &lmh_irq_ops, lmh_data); + if (!lmh_data->domain) { + dev_err(dev, "Error adding irq_domain\n"); + return -EINVAL; + } + + /* Disable the irq and let cpufreq enable it when ready to handle the interrupt */ + irq_set_status_flags(lmh_data->irq, IRQ_NOAUTOEN); + ret = devm_request_irq(dev, lmh_data->irq, lmh_handle_irq, + IRQF_ONESHOT | IRQF_NO_SUSPEND, + "lmh-irq", lmh_data); + if (ret) { + dev_err(dev, "Error %d registering irq %x\n", ret, lmh_data->irq); + irq_domain_remove(lmh_data->domain); + return ret; + } + + return 0; +} + +static const struct of_device_id lmh_table[] = { + { .compatible = "qcom,sdm845-lmh", }, + {} +}; +MODULE_DEVICE_TABLE(of, lmh_table); + +static struct platform_driver lmh_driver = { + .probe = lmh_probe, + .driver = { + .name = "qcom-lmh", + .of_match_table = lmh_table, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(lmh_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QCOM LMh driver"); From patchwork Mon Aug 9 19:16:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65DB7C432BE for ; Mon, 9 Aug 2021 19:16:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4ADD960C3E for ; Mon, 9 Aug 2021 19:16:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236056AbhHITQh (ORCPT ); Mon, 9 Aug 2021 15:16:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236018AbhHITQb (ORCPT ); Mon, 9 Aug 2021 15:16:31 -0400 Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A92B0C06179A for ; Mon, 9 Aug 2021 12:16:10 -0700 (PDT) Received: by mail-qt1-x82a.google.com with SMTP id d9so13394730qty.12 for ; Mon, 09 Aug 2021 12:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M441F/dCOu3tlQKnKAKIoZxwlYnqvhrWCGp9221xVHk=; b=B/c2BFtwUODWQxiL/AGJUFkAamP4RWl2XoUfsvJn9QDR9a399/ZTBwmRKwMwje5Xr6 PKGs4maeDCpAcC6+KCqU2bncXRDT2O3Dr3FJYWR58DTp0kNTmeKCPPZfp8aFP43Kng6X N5a08unUtwE7qyyngKRg+vKHpS5Lc6RTfE2EiMMkEg5AEC40NFyuQCB7/cWuCng0T/bl wiN2SRRwwCQO9NIb/O9A2GPNt+zQN8b4TvhzyxBKcHJn+6XEAB6CdJuUgQfrTiLAi7TN /8JMZE2KVFkCpp+jqHpFS+Jd3JtEKduhcZAJ395eCk6A+KWZz5RP7k7oBXwTOujCqDNr r2sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M441F/dCOu3tlQKnKAKIoZxwlYnqvhrWCGp9221xVHk=; b=QRfdatVS22xLYAoEFduh7eKcFJM/pq8mz3bZBD7qXQ9TtboPW/fDJe/XtG9B0gajqu 0tcixFo4asuXK6CJv4XHOcnJda8y1A73GjPAbI+g0wNO9KkpKEBtUYGsKq3uGIjZFaVI u365nxHP5Sf7Oi2CLYsEaJygl+uwboFoL2+VAp1mtF6VkzKgKvP0PkAS6xT+dqG8IjVA pbpppjSRkzfp/+AlgJBCUDkVCh2pjQNsH/rmn+8RGd7kN/WcIbMvzt6WuI+aQww7GmZg M3Qj2psyebCt+hTYI+DyOEsyoIhSVMd3H+SfmpLQX27b0jh3NOb8xvMIcqT3t1Lk6emW gBZg== X-Gm-Message-State: AOAM530pSVaWdl4l1Hu61m3NUVyYUwBgVoS/rs5vSV8ZDUAOEISlgv1+ JoQUrA4ClOAs62v9y/ssY5Xy3Q== X-Google-Smtp-Source: ABdhPJxdXbXbKOX8+r/7UOK3yqpDMVli5Cpfq8grtLR+wJi5MnzfKHYVWrdAY5AN996Jg+XHn33gNA== X-Received: by 2002:ac8:5b89:: with SMTP id a9mr7406884qta.282.1628536569797; Mon, 09 Aug 2021 12:16:09 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:09 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 3/6] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Date: Mon, 9 Aug 2021 15:16:01 -0400 Message-Id: <20210809191605.3742979-4-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt support to notify the kernel of h/w initiated frequency throttling by LMh. Convey this to scheduler via thermal presssure interface. Signed-off-by: Thara Gopinath --- v4->v5: - Changed throttle_lock from a spinlock to mutex to take potential race between LMh de-init sequence and reenabling of interrupts/polling after a thermal throttle event. - Other cosmetic fixes as pointed out by Viresh. v3->v4: - Dropped devm_ versions of request_irq and free_irq as per comments on mailing list. - Introduced locking to prevent race between LMh de-init sequence and re-enabling of interrupts/polling after a thermal throttle event. - Moved the LMh de-init sequence to qcom_cpufreq_hw_lmh_exit as per Viresh's review comments - Code rearrangement as per Bjorn's review comments. - Moved the interrupt handling to threaded interrupt handling since Steev reported some scheduling while atomic bug on the mailing list. v2->v3: - Cosmetic fixes from review comments on the list. - Moved all LMh initializations to qcom_cpufreq_hw_lmh_init. - Added freeing of LMh interrupt and cancelling the polling worker to qcom_cpufreq_hw_cpu_exit as per Viresh's suggestion. - LMh interrupts are now tied to cpu dev and not cpufreq dev. This will be useful for further generation of SoCs where the same interrupt signals multiple cpu clusters. v1->v2: - Introduced qcom_cpufreq_hw_lmh_init to consolidate LMh related initializations as per Viresh's review comment. - Moved the piece of code restarting polling/re-enabling LMh interrupt to qcom_lmh_dcvs_notify therby simplifying isr and timer callback as per Viresh's suggestion. - Droped cpus from qcom_cpufreq_data and instead using cpus from cpufreq_policy in qcom_lmh_dcvs_notify as per Viresh's review comment. - Dropped dt property qcom,support-lmh as per Bjorn's suggestion. - Other minor/cosmetic fixes drivers/cpufreq/qcom-cpufreq-hw.c | 147 ++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index f86859bf76f1..d9f6da99af3a 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -7,12 +7,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) @@ -22,10 +24,13 @@ #define CLK_HW_DIV 2 #define LUT_TURBO_IND 1 +#define HZ_PER_KHZ 1000 + struct qcom_cpufreq_soc_data { u32 reg_enable; u32 reg_freq_lut; u32 reg_volt_lut; + u32 reg_current_vote; u32 reg_perf_state; u8 lut_row_size; }; @@ -34,6 +39,16 @@ struct qcom_cpufreq_data { void __iomem *base; struct resource *res; const struct qcom_cpufreq_soc_data *soc_data; + + /* + * Mutex to synchronize between de-init sequence and re-starting LMh + * polling/interrupts + */ + struct mutex throttle_lock; + int throttle_irq; + bool cancel_throttle; + struct delayed_work throttle_work; + struct cpufreq_policy *policy; }; static unsigned long cpu_hw_rate, xo_rate; @@ -251,10 +266,92 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } +static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) +{ + unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote); + + return (val & 0x3FF) * 19200; +} + +static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) +{ + unsigned long max_capacity, capacity, freq_hz, throttled_freq; + struct cpufreq_policy *policy = data->policy; + int cpu = cpumask_first(policy->cpus); + struct device *dev = get_cpu_device(cpu); + struct dev_pm_opp *opp; + unsigned int freq; + + /* + * Get the h/w throttled frequency, normalize it using the + * registered opp table and use it to calculate thermal pressure. + */ + freq = qcom_lmh_get_throttle_freq(data); + freq_hz = freq * HZ_PER_KHZ; + + opp = dev_pm_opp_find_freq_floor(dev, &freq_hz); + if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) + opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz); + + throttled_freq = freq_hz / HZ_PER_KHZ; + + /* Update thermal pressure */ + + max_capacity = arch_scale_cpu_capacity(cpu); + capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq); + + /* Don't pass boost capacity to scheduler */ + if (capacity > max_capacity) + capacity = max_capacity; + + arch_set_thermal_pressure(policy->cpus, max_capacity - capacity); + + /* + * In the unlikely case policy is unregistered do not enable + * polling or h/w interrupt + */ + mutex_lock(&data->throttle_lock); + if (data->cancel_throttle) + goto out; + + /* + * If h/w throttled frequency is higher than what cpufreq has requested + * for, then stop polling and switch back to interrupt mechanism. + */ + if (throttled_freq >= qcom_cpufreq_hw_get(cpu)) + enable_irq(data->throttle_irq); + else + mod_delayed_work(system_highpri_wq, &data->throttle_work, + msecs_to_jiffies(10)); + +out: + mutex_unlock(&data->throttle_lock); +} + +static void qcom_lmh_dcvs_poll(struct work_struct *work) +{ + struct qcom_cpufreq_data *data; + + data = container_of(work, struct qcom_cpufreq_data, throttle_work.work); + qcom_lmh_dcvs_notify(data); +} + +static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) +{ + struct qcom_cpufreq_data *c_data = data; + + /* Disable interrupt and enable polling */ + disable_irq_nosync(c_data->throttle_irq); + qcom_lmh_dcvs_notify(c_data); + + return 0; +} + static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x110, .reg_volt_lut = 0x114, + .reg_current_vote = 0x704, .reg_perf_state = 0x920, .lut_row_size = 32, }; @@ -274,6 +371,51 @@ static const struct of_device_id qcom_cpufreq_hw_match[] = { }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); +static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index) +{ + struct qcom_cpufreq_data *data = policy->driver_data; + struct platform_device *pdev = cpufreq_get_driver_data(); + char irq_name[15]; + int ret; + + /* + * Look for LMh interrupt. If no interrupt line is specified / + * if there is an error, allow cpufreq to be enabled as usual. + */ + data->throttle_irq = platform_get_irq(pdev, index); + if (data->throttle_irq <= 0) + return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0; + + data->cancel_throttle = false; + data->policy = policy; + + mutex_init(&data->throttle_lock); + INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll); + + snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu); + ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq, + IRQF_ONESHOT, irq_name, data); + if (ret) { + dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret); + return 0; + } + + return 0; +} + +static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data) +{ + if (data->throttle_irq <= 0) + return; + + mutex_lock(&data->throttle_lock); + data->cancel_throttle = true; + mutex_unlock(&data->throttle_lock); + + cancel_delayed_work_sync(&data->throttle_work); + free_irq(data->throttle_irq, data); +} + static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct platform_device *pdev = cpufreq_get_driver_data(); @@ -370,6 +512,10 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); } + ret = qcom_cpufreq_hw_lmh_init(policy, index); + if (ret) + goto error; + return 0; error: kfree(data); @@ -389,6 +535,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) dev_pm_opp_remove_all_dynamic(cpu_dev); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); + qcom_cpufreq_hw_lmh_exit(data); kfree(policy->freq_table); kfree(data); iounmap(base); From patchwork Mon Aug 9 19:16:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D156AC43214 for ; Mon, 9 Aug 2021 19:16:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B78D661051 for ; Mon, 9 Aug 2021 19:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236066AbhHITQt (ORCPT ); Mon, 9 Aug 2021 15:16:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236028AbhHITQc (ORCPT ); Mon, 9 Aug 2021 15:16:32 -0400 Received: from mail-qt1-x82c.google.com (mail-qt1-x82c.google.com [IPv6:2607:f8b0:4864:20::82c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3D70C061798 for ; Mon, 9 Aug 2021 12:16:11 -0700 (PDT) Received: by mail-qt1-x82c.google.com with SMTP id l3so5008647qtk.10 for ; Mon, 09 Aug 2021 12:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uRDZmyuq4axbYzHmiE0iOEImexM18sedZH7tLrs/dF0=; b=RyPkY8wsR357mYKU94l07YIoW5mMyDlM65dUaySXh+5pQxuey/rLJISydLl3d4PC3m J92PQ4OfZygbBDTu7TNcZPwWg+cfknKPsjbQNevYbZLeLPK3uCRi3oXQDbB92W0AJrg2 UCS58rbfFGydfCLsx0RRvFHGwKZ2psqjkCZRrhlA6VMzWunH9YV9Y8Y64UgboCfAlLFs MvxfyYNyD/JK5SiWZ1JmRIiy7f2B+MN1zHdUBR+lzay3vPftLl58wFY3GmeiGfy+zb3W t2ix5Y+K8FwXITROTkZgfys+3HND2DQPPzNmWLs7hjOpGwkt8e8XWhImLRe3jEjWOIR0 GV3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uRDZmyuq4axbYzHmiE0iOEImexM18sedZH7tLrs/dF0=; b=o+A2laE8YggKEOo7CSuuhSBQcXzEG5DTnZxeV5/v4sobZ+fRwGRI9hwXrNAf9VTq+h LczCex7uEAVraYYAMhe2tZljcr8J7psKEvr3rB8A2ocOW2ps75S3mt2NGojFfJNEHg+s Jh/CHBANaGB45FtVbObZ+rFzYhzq196vXJ+RJk1/scv57jI5KSzVKaKke2gXMhbcie+f nAmmURhoQCNAnPn2Q/+aS3UUo7kmx3tlXt/F7Aa4CP9bXdWhh2kkwcE5G+MJuC8ypQrD 2tNI8aPipofWCYEWDExH8dmqaLqYPeR905X63cGYWwmmg7xyUgYXZ48dJV7zuBB/dOVj JdnA== X-Gm-Message-State: AOAM533eTJr23vvdD+YxGTAwLcOPeQP/jAIyOgX49FiCNXZtQRKoFe7l BYzcPzk6Vq/shjyHT8uqBe+IaQ== X-Google-Smtp-Source: ABdhPJy4EgtTS5uDMgBaKUSLduB3HPDHZqpcu0jSUO5XCeRCyNlLkiTKjNDel1pIi3ANsLdT+eFwjg== X-Received: by 2002:ac8:588f:: with SMTP id t15mr21584134qta.367.1628536570810; Mon, 09 Aug 2021 12:16:10 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:10 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 4/6] arm64: dts: qcom: sdm45: Add support for LMh node Date: Mon, 9 Aug 2021 15:16:02 -0400 Message-Id: <20210809191605.3742979-5-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Reviewed-by: Bjorn Andersson Signed-off-by: Thara Gopinath --- v4->v5: - Renamed dt binding property qcom,lmh-cpu to cpus as per Rob Herring's review comments. - Changed LMh reg space size from the wierd size 0x401 to 0x400. v3->v4: - Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it a phandle pointing to the cpu node instead of a number as per Rob Herring's review comments. - Added suffix -millicelsius to all temperature properties as per Rob Herring's review comments. v2->v3: - Changed the LMh low and high trip to 94500 and 95000 mC from 74500 and 75000 mC. This was a bug that got introduced in v2. v1->v2: - Dropped dt property qcom,support-lmh as per Bjorn's review comments. - Changed lmh compatible from generic to platform specific. - Introduced properties specifying arm, low and high temp thresholds for LMh as per Daniel's suggestion. arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..d90c896cbac8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3646,6 +3646,30 @@ swm: swm@c85 { }; }; + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + sound: sound { }; @@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 { reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; From patchwork Mon Aug 9 19:16:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6D1AC4338F for ; Mon, 9 Aug 2021 19:16:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DEB660FE3 for ; Mon, 9 Aug 2021 19:16:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236053AbhHITQl (ORCPT ); Mon, 9 Aug 2021 15:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236016AbhHITQh (ORCPT ); Mon, 9 Aug 2021 15:16:37 -0400 Received: from mail-qv1-xf29.google.com (mail-qv1-xf29.google.com [IPv6:2607:f8b0:4864:20::f29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 924F1C0617A2 for ; Mon, 9 Aug 2021 12:16:12 -0700 (PDT) Received: by mail-qv1-xf29.google.com with SMTP id em4so9613831qvb.0 for ; Mon, 09 Aug 2021 12:16:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=86AhPDAQOdkdMXmbEk4DdTqD+0llGfC19Iuwbx+jYlY=; b=za+dJFHbHDpdbxK+0tzTO8rfizVeZpKNcmSJV7XZA/+BOExPQVxv088KKTm6EmlP9N z9PGnpxi8JkZVNOGniRIFV95L/YhUBhm7Ol3lJh+BWTC4u8XLec7Jf0NzsdFemkHdk+x dpPwab5w61uQf5aRFqowfDbRzp4SFROCkS1i/3xWNm8qrpMeFMMD9jEK373Od4fdKs87 txoOJObk/EgqUur/AwZZO+2P4er0DgPemG2JgvnHSBuSzLeQg+CUZJ5rqSK+BPcobEVS kWz9xK6duj8tuXxx3dUu4Nw8MXZsltXI20nPi8iualiOK6ArkNUmzzWik47ECsWcvecQ JNkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=86AhPDAQOdkdMXmbEk4DdTqD+0llGfC19Iuwbx+jYlY=; b=J6vxTG+/LibPxubfTZINOcyT2nldUOiSjx5ls4GNIXaDxCokGyGzQQuPTR3tkwoUCm xhEZIpZeqqft83PivUTSIkycFuD+xn84fD5+FkRr329yEkW+ettLqy03VLhepTsz6Sem 7JMHPv4jJOsIXqeZaVa2iCuzbqVFqeKgdxGzyaqfnVOA5jE1yGdk7JqXMATZUJ264W22 Q1lnG/OEy39LrBxGGjXFJc0gHJlVQ+0YPC+pnHC/JN+/muy29VNNCMlVJW8AlzeC/Ca1 X2ci2SwBgdlm5vidz5sELIWqGBGk6nQbHaCZCzubsz5jqXT7z6eYoGF1tCtOhfSmToAn +Vgw== X-Gm-Message-State: AOAM5302RTYIqBXBwK2c/cKAsWJQPAJ1zeKDZvfcqei11qsaMMO/Yk7A q/Dt9YhKEOIRAkoFnFobsPhPpA== X-Google-Smtp-Source: ABdhPJz3j+7z1hrIGUiV9k5Z9fyf/Rey8b1Wazh0VMUqmUrnwbJ1go0uenr/scr14ulYN/oQ2WZfRA== X-Received: by 2002:a05:6214:10c8:: with SMTP id r8mr25099944qvs.28.1628536571760; Mon, 09 Aug 2021 12:16:11 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:11 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 5/6] arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones Date: Mon, 9 Aug 2021 15:16:03 -0400 Message-Id: <20210809191605.3742979-6-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that Limits h/w is enabled to monitor thermal events around cpus and throttle the cpu frequencies, remove cpufreq cooling device for the CPU thermal zones which does software throttling of cpu frequencies. Reviewed-by: Bjorn Andersson Signed-off-by: Thara Gopinath --- v2->v3: - Improved the subject header and descrption to better reflect the patch as per Matthias's review comments. v1->v2: Removing only cooling maps for cpu specific thermal zones keeping the trip point definitions intact as per Daniel's suggestion. This is to ensure that thermal zone temparature and trip violation information is available to any userspace daemon monitoring these zones. arch/arm64/boot/dts/qcom/sdm845.dtsi | 136 --------------------------- 1 file changed, 136 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d90c896cbac8..b348c1efa1fb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4994,23 +4994,6 @@ cpu0_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu1-thermal { @@ -5038,23 +5021,6 @@ cpu1_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu2-thermal { @@ -5082,23 +5048,6 @@ cpu2_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu3-thermal { @@ -5126,23 +5075,6 @@ cpu3_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu4-thermal { @@ -5170,23 +5102,6 @@ cpu4_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu5-thermal { @@ -5214,23 +5129,6 @@ cpu5_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu6-thermal { @@ -5258,23 +5156,6 @@ cpu6_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu7-thermal { @@ -5302,23 +5183,6 @@ cpu7_crit: cpu_crit { type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; aoss0-thermal { From patchwork Mon Aug 9 19:16:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thara Gopinath X-Patchwork-Id: 12427177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18309C19F35 for ; Mon, 9 Aug 2021 19:16:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0121B610A7 for ; Mon, 9 Aug 2021 19:16:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236093AbhHITQl (ORCPT ); Mon, 9 Aug 2021 15:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236050AbhHITQh (ORCPT ); Mon, 9 Aug 2021 15:16:37 -0400 Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860A3C0617A4 for ; Mon, 9 Aug 2021 12:16:13 -0700 (PDT) Received: by mail-qt1-x834.google.com with SMTP id w10so13414883qtj.3 for ; Mon, 09 Aug 2021 12:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gv+OB+zM5345b30boI1Lb87AMcz6Zm625J86U+m0DDQ=; b=u66mof9UZWfzozysTRhTFMa9uWwaPMPgEfMLgNOAo7IkTgPRCA5TW77iQaHcCBhAat AEbjRBTLS46wv7WROSGETRDxspeu4zVZY5Ehjd7Ne+/K01BlLWqrvVoBbAociBeOcIuK GRsA0F0AcacQm38xfXATCKlu/IQaxs735+fdkRzVQuJOpUC1Xs5x9MYqPKRCHcGesFGm 6MXrGM7JfT2fTXZtjI4YbPuDwU/tgaxO9tLa3ReOsQuQUjqKxOTgFrBLi3pweFUPpAkX 7f6TALay4zXZF85OAQbS47wbTNRGlGMVO93HP+RYybUpWTrkMwNnmaogXYYU083Y0uDc 1Hvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gv+OB+zM5345b30boI1Lb87AMcz6Zm625J86U+m0DDQ=; b=FTLU2iy9VNLkWEpPlQG0AjiGxxyw8+JJjOD6YSecutLtVWirhbghSF+/Xp19r7cgEO Gm7Kel2jXSK2dQ2YRYobaUc8EVKqcWf5ttRWOy/tOPqwYrm5yVG342fWwzbWsMQ3o2YX lMSwtkauRXxJvhLaI8/fEAACcMhczfokX/R2LxE+I/Az/dzi43GpG3cK+opJ5bu/D7UP VSfdP9P4vyED+SXfzhkgeiA8rIEYs1HuBlD6MWapuJERN/Y7hNUQacQBf0aGJgr930bC Ep4LCqXp8a1iqbMSjQyeBPQyF1Zysh8EvNcbZlBibG6q3s+s7LLfjGo+yFtV4LiwWx5L M76Q== X-Gm-Message-State: AOAM533YVwfalhlSSKEmhf0rUotnvXcODy7lol13hV0wZOB9jBIfHJKk XFTIaKdBi/QBr0PLjD+ZjYSGTw== X-Google-Smtp-Source: ABdhPJw5/xxDaedKxpjvJ6yLlI9xIoe/03yr2dJSVYEpzYIHPS8T9azPUbXY6puHqWC3RXKBjJlQFA== X-Received: by 2002:ac8:5a91:: with SMTP id c17mr9079858qtc.42.1628536572691; Mon, 09 Aug 2021 12:16:12 -0700 (PDT) Received: from pop-os.fios-router.home (pool-71-163-245-5.washdc.fios.verizon.net. [71.163.245.5]) by smtp.googlemail.com with ESMTPSA id n14sm7303398qti.47.2021.08.09.12.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 12:16:12 -0700 (PDT) From: Thara Gopinath To: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org Cc: steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [Patch v5 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh Date: Mon, 9 Aug 2021 15:16:04 -0400 Message-Id: <20210809191605.3742979-7-thara.gopinath@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210809191605.3742979-1-thara.gopinath@linaro.org> References: <20210809191605.3742979-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt binding documentation to describe Qualcomm Limits Management Hardware node. Signed-off-by: Thara Gopinath --- v4->v5: - Renamed dt binding property qcom,lmh-cpu to cpus as per Rob Herring's review comments. - Fixed examples and consolidated to just one example. - Other minor fixes as pointed out by Rob Herring. v3->v4: - Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it a phandle pointing to the cpu node instead of a number as per Rob Herring's review comments. - Added suffix -millicelsius to all temperature properties as per Rob Herring's review comments. - Dropped unnecessary #includes in the example as pointed out by Bjorn. - Other minor fixes. .../devicetree/bindings/thermal/qcom-lmh.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml new file mode 100644 index 000000000000..289e9a845600 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Limits Management Hardware(LMh) + +maintainers: + - Thara Gopinath + +description: + Limits Management Hardware(LMh) is a hardware infrastructure on some + Qualcomm SoCs that can enforce temperature and current limits as + programmed by software for certain IPs like CPU. + +properties: + compatible: + enum: + - qcom,sdm845-lmh + + reg: + items: + - description: core registers + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + cpus: + description: + phandle of the first cpu in the LMh cluster + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,lmh-temp-arm-millicelsius: + description: + An integer expressing temperature threshold at which the LMh thermal + FSM is engaged. + + qcom,lmh-temp-low-millicelsius: + description: + An integer expressing temperature threshold at which the state machine + will attempt to remove frequency throttling. + + qcom,lmh-temp-high-millicelsius: + description: + An integer expressing temperature threshold at which the state machine + will attempt to throttle the frequency. + +required: + - compatible + - reg + - interrupts + - '#interrupt-cells' + - interrupt-controller + - cpus + - qcom,lmh-temp-arm-millicelsius + - qcom,lmh-temp-low-millicelsius + - qcom,lmh-temp-high-millicelsius + +additionalProperties: false + +examples: + - | + #include + + lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0x17d70800 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + };