From patchwork Mon Aug 16 00:12:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1035EC4338F for ; Mon, 16 Aug 2021 00:15:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE38E6137D for ; Mon, 16 Aug 2021 00:15:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CE38E6137D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=wt74nfLlS7MU0O9JfqfXLi3oVXRNv+5Aufl8kgs0jtA=; b=hUhnjT6oCKPbxa2s+lacqsQzyo JUlSFBEwkxliz4io1JA8AGreTyQbo9P+REtsTib0KgrmefjfuzGrNJr1wpawkgAa/9TH5bb1/pizp 2E7QzQlgr0N7JLb8ukIqw/9CktytgyyprZsxUwKzoDmnZs1Rz5/7zMrxWSBVJI5qtX2s+Sk8nzMwD qtrbYN9X4MCSaJIyoONL0wkQDF0nB9JMfhbI6vk3iL+se1jTVTkdJXEKcF1iNw4/LTu/ONrmw39Xu Ypdj9yoVjeBkeJ00KRpB2D4eGffqYPNmw1zdL9UTkdun5Dt5qtWjveVeN+6QXxuVFw4WhIYDVd7uM oC0blwIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQGA-00Flg1-W4; Mon, 16 Aug 2021 00:13:47 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEp-00FlAb-AJ for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:24 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id t101-20020a25aaee0000b0290578c0c455b2so14988685ybi.13 for ; Sun, 15 Aug 2021 17:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=onAqEh8W0SBicAWR55u2ngfwbUkFlrlMLEeDkUeYr84=; b=qhpICAaFLhU3+IHGm11sW/Isc3WfyB2RHrfJtKUbGw63J9vM6gdE81PvZpG2zwzw8O xvVYLTVWjzq99ack7VgFOvIFPZ9F8t1LoJ+Bka5jr0/d1fVgY11AhngDstTL1cvP8CGl uzx6mHO3mvAm1M8LD8tT2AZJBhRb1SK4+nTn70NI8oIPj2hNdSXzcfTaW9wyiq8hjMmt SeTDHthVV5479sAgDnHPGWxL3jKaNRJ7PjRH2ZZ+VZci3oTPKyXAAOqKsDZ0WtPr0VeB 9t45HJPdPMTdj85xkXn2iZcBVWBjs8VxIxPa4CqJJyRRVVNRxf2OeHlXRUStSFQlttQb 94Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=onAqEh8W0SBicAWR55u2ngfwbUkFlrlMLEeDkUeYr84=; b=fFYH0LgNJaImCqZNW3v4k9iY2Dz2Wvj8I+6DferUZOFp0Nc+lBF4rj/g9SzkF9Z2cm tcIbpxFUv79o7Mv7D4Y9u0djsm7h+4r60UFhBmS0wV+7tE06znWKKqdzifQtVF5WBdmz qctjPwxgIAaFk/rV4zXrNrVlMQPlP3SNklVUMZG51XhvAETMG77w+x9JY/Fek4pUq1Jx Ev0fzlRcvW/x/3o0bcE/zDNYKYvGFwe5DaSc4w7mJ4Xce6i2BdmQfgUTyEgW5x17l0PY ls3OgsDSDVLXMNv5KQjXhzU5dtMCoE/HhGhnSBiG53GkGyutStx07HxyvtmyKQaeq5Ta utAg== X-Gm-Message-State: AOAM530VNnfraUmhKLwOEQbIbzmILt3JgqDOPS3SPoFEyQvlBNGf6Mj3 n7maaOOeafKaVaOIN8FD329rbnzchR8= X-Google-Smtp-Source: ABdhPJy6FWA8u3sJLeHS6AWC8Xv9Z0rmwcuGesbQJOl0Ryv15/E1haP7bvTFN3gsAs53WozMzCacm0BdTVs= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a25:8c4:: with SMTP id 187mr17077125ybi.369.1629072741950; Sun, 15 Aug 2021 17:12:21 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:11 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-2-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 1/7] KVM: arm64: Refactor update_vtimer_cntvoff() From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171223_402571_AE10D80C X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Make the implementation of update_vtimer_cntvoff() generic w.r.t. guest timer context and spin off into a new helper method for later use. Require callers of this new helper method to grab the kvm lock beforehand. No functional change intended. Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- arch/arm64/kvm/arch_timer.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 3df67c127489..c0101db75ad4 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -747,22 +747,32 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) return 0; } -/* Make the updates of cntvoff for all vtimer contexts atomic */ -static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) +/* Make offset updates for all timer contexts atomic */ +static void update_timer_offset(struct kvm_vcpu *vcpu, + enum kvm_arch_timers timer, u64 offset) { int i; struct kvm *kvm = vcpu->kvm; struct kvm_vcpu *tmp; - mutex_lock(&kvm->lock); + lockdep_assert_held(&kvm->lock); + kvm_for_each_vcpu(i, tmp, kvm) - timer_set_offset(vcpu_vtimer(tmp), cntvoff); + timer_set_offset(vcpu_get_timer(tmp, timer), offset); /* * When called from the vcpu create path, the CPU being created is not * included in the loop above, so we just set it here as well. */ - timer_set_offset(vcpu_vtimer(vcpu), cntvoff); + timer_set_offset(vcpu_get_timer(vcpu, timer), offset); +} + +static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) +{ + struct kvm *kvm = vcpu->kvm; + + mutex_lock(&kvm->lock); + update_timer_offset(vcpu, TIMER_VTIMER, cntvoff); mutex_unlock(&kvm->lock); } From patchwork Mon Aug 16 00:12:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D7C0C4338F for ; Mon, 16 Aug 2021 00:17:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21E046137D for ; Mon, 16 Aug 2021 00:17:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 21E046137D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=mQn9I0rkw09M57jHG++RCqtz6PgIGyKd3QMcCCFgeqY=; b=m+0zCklOI8G5BHe9FWkFk4KihO TRtbV4rB3iKlXWD07USZ8DW+KTp5Hkjxg6GqkcttG523nNKAGX0O5+TL7ndFGm1UGr5DLcN5q6gAL PZAxiQGhOmO+ucbuDMO7xvoQuxAdJElFgUOH+r1l3SP1dFNxi5kdF/dWRaJsPuTuaqDmBCOo2oxmh fNPEdEYbob3x3gCVtqh0FeSdt7+oGu1Pp7MqoqWNmkqJ0B+p8+SuRMzZNwAKj6v5LSfrbUcTOC9bJ fHPjqVkT2IW5HwHq2tXpdWJnyAxPtttJv9QLwIkKo9F9h3iGchF8gG/wX7heYVf1Zvu2YYhXZJzLx QlGj+Irw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQHz-00FmaC-Fz; Mon, 16 Aug 2021 00:15:40 +0000 Received: from mail-qk1-x749.google.com ([2607:f8b0:4864:20::749]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEs-00FlBD-3P for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:27 +0000 Received: by mail-qk1-x749.google.com with SMTP id a24-20020a05620a067800b003c9e325c3b2so2045455qkh.2 for ; Sun, 15 Aug 2021 17:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=uLRkJfCEmqyHmwt67N1JORfBg6VVerDIPLLp0n4Mv0U=; b=az5D41bG34bsZyE4U/Nl4rUJhZpPihdRW7A67FKbR51vbYA8/c4WWz5DmGb6kA+SAI Fy5fnGj6b0cIT+KDkY4NvSAeSZiTilmdZNQaaMzjxMO3xmKhydttHM6ZXtRi4ct/Q+y6 byU+NodQcgiK/WX5AG7ikc0vn5J7JGvnBxHJ0rwHeo05kMP95N7l+syBD9e9ekADqFC6 jH8vf2L+PHooPrAuSTPQcLlU5D1nZ4hW3OeUxX8NM/dKDjfhQc+1eniThWPOG8bF8uRK M1f63eAHNJnsgC+M4PSzqApfazG0gApt0+KDADuE1BF+Pxg4PKz3G2VuYnk2cSwbBgrG 6bwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=uLRkJfCEmqyHmwt67N1JORfBg6VVerDIPLLp0n4Mv0U=; b=GZLLPbkkvb4JvrvmkoamQMhjWeJEGnlg13nVTu7wPCPR3Fe2soZBAIRkCpsLdHGpWW G9+cxPErZgDVbnb2H4eb/FOudOBKxHWOQGnsyj1Q0SLCZVOX0gFtJkJXjf9c5zmflo0r grQr1W1XhUIfz5ygOcljMnFmoM8PQpiwoerMP2TNfP+u5JMoI3Yw92eC24s1U52keysW wuYQhwarqinkVAE7cpCSAeKRpo7X7MGUC9R1xqzJAlvB66V1sx+YZk5IJgvqZtOooehJ v9KTNUXgt0ixSp1M9MyVnQfwnvUD8irPHdwMemIuustIQUbYh9z7HIXsFXcnrlGvHR9S biYQ== X-Gm-Message-State: AOAM533pY3zbPN8Bh4eDe+2fGz9S3STDSD6QQubAENRXZ20hcERf3XGW PIDRUUlqzFObtHmhIA3TFznPq5ltSVo= X-Google-Smtp-Source: ABdhPJxN9vYt2dk3pmPjMhg9I52ySGOOv1oZG7v2jUbr/ARWQpGX10zXw+GycL4prPFR8PpVJgnut/nd4JU= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a0c:b216:: with SMTP id x22mr13766363qvd.55.1629072743021; Sun, 15 Aug 2021 17:12:23 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:12 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-3-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 2/7] KVM: arm64: Separate guest/host counter offset values From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171226_210448_0393C789 X-CRM114-Status: GOOD ( 16.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In some instances, a VMM may want to update the guest's counter-timer offset in a transparent manner, meaning that changes to the hardware value do not affect the synthetic register presented to the guest or the VMM through said guest's architectural state. Lay the groundwork to separate guest offset register writes from the hardware values utilized by KVM. Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- arch/arm64/kvm/arch_timer.c | 42 +++++++++++++++++++++++++++--------- include/kvm/arm_arch_timer.h | 3 +++ 2 files changed, 35 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index c0101db75ad4..cf2f4a034dbe 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -84,11 +84,9 @@ u64 timer_get_cval(struct arch_timer_context *ctxt) static u64 timer_get_offset(struct arch_timer_context *ctxt) { - struct kvm_vcpu *vcpu = ctxt->vcpu; - switch(arch_timer_ctx_index(ctxt)) { case TIMER_VTIMER: - return __vcpu_sys_reg(vcpu, CNTVOFF_EL2); + return ctxt->host_offset; default: return 0; } @@ -128,17 +126,33 @@ static void timer_set_cval(struct arch_timer_context *ctxt, u64 cval) static void timer_set_offset(struct arch_timer_context *ctxt, u64 offset) { - struct kvm_vcpu *vcpu = ctxt->vcpu; - switch(arch_timer_ctx_index(ctxt)) { case TIMER_VTIMER: - __vcpu_sys_reg(vcpu, CNTVOFF_EL2) = offset; + ctxt->host_offset = offset; break; default: WARN(offset, "timer %ld\n", arch_timer_ctx_index(ctxt)); } } +static void timer_set_guest_offset(struct arch_timer_context *ctxt, u64 offset) +{ + struct kvm_vcpu *vcpu = ctxt->vcpu; + + switch (arch_timer_ctx_index(ctxt)) { + case TIMER_VTIMER: { + u64 host_offset = timer_get_offset(ctxt); + + host_offset += offset - __vcpu_sys_reg(vcpu, CNTVOFF_EL2); + __vcpu_sys_reg(vcpu, CNTVOFF_EL2) = offset; + timer_set_offset(ctxt, host_offset); + break; + } + default: + WARN_ONCE(offset, "timer %ld\n", arch_timer_ctx_index(ctxt)); + } +} + u64 kvm_phys_timer_read(void) { return timecounter->cc->read(timecounter->cc); @@ -749,7 +763,8 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) /* Make offset updates for all timer contexts atomic */ static void update_timer_offset(struct kvm_vcpu *vcpu, - enum kvm_arch_timers timer, u64 offset) + enum kvm_arch_timers timer, u64 offset, + bool guest_visible) { int i; struct kvm *kvm = vcpu->kvm; @@ -758,13 +773,20 @@ static void update_timer_offset(struct kvm_vcpu *vcpu, lockdep_assert_held(&kvm->lock); kvm_for_each_vcpu(i, tmp, kvm) - timer_set_offset(vcpu_get_timer(tmp, timer), offset); + if (guest_visible) + timer_set_guest_offset(vcpu_get_timer(tmp, timer), + offset); + else + timer_set_offset(vcpu_get_timer(tmp, timer), offset); /* * When called from the vcpu create path, the CPU being created is not * included in the loop above, so we just set it here as well. */ - timer_set_offset(vcpu_get_timer(vcpu, timer), offset); + if (guest_visible) + timer_set_guest_offset(vcpu_get_timer(vcpu, timer), offset); + else + timer_set_offset(vcpu_get_timer(vcpu, timer), offset); } static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) @@ -772,7 +794,7 @@ static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) struct kvm *kvm = vcpu->kvm; mutex_lock(&kvm->lock); - update_timer_offset(vcpu, TIMER_VTIMER, cntvoff); + update_timer_offset(vcpu, TIMER_VTIMER, cntvoff, true); mutex_unlock(&kvm->lock); } diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 51c19381108c..9d65d4a29f81 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -42,6 +42,9 @@ struct arch_timer_context { /* Duplicated state from arch_timer.c for convenience */ u32 host_timer_irq; u32 host_timer_irq_flags; + + /* offset relative to the host's physical counter-timer */ + u64 host_offset; }; struct timer_map { From patchwork Mon Aug 16 00:12:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A4F7C4338F for ; Mon, 16 Aug 2021 00:17:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 22AD16137D for ; Mon, 16 Aug 2021 00:17:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 22AD16137D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=NWC/MpkmvS4LdkymyuApzZh+M8JFlVUNZjMEUA/21BE=; b=XhymeL7GcUy6QJ1DN3mDjO6yJX OxNpmEtDJrZF+YTaird2VmnC75W1NnXHBq0x/H0wJWE8mh2c7Lu/E8XfIdmdZeiinfPsV8w2dtg0D qBm3axgP+gfCuSNR2h90FduTjcvAM8we64zXHS12K9KAcmbQIRmLKJVqwcFyQQsjseZwhsORMZ+EN 6igJis78A5ArzCoUIAsE71ACOL6BojPJTIiM27NgV+eWQ6Ug2Yyu0ikPGh1j4BmFFXm0eTP86MsJh mci0p4ZqyzIOL249PrO0WHMOcB0PfIllIYIMlEjDEHelt1GLGufTIY5EzoWIs7vUNZ9FIRHlfdIDk 6py7K3gg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQHN-00FmHC-6x; Mon, 16 Aug 2021 00:15:02 +0000 Received: from mail-il1-x149.google.com ([2607:f8b0:4864:20::149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEr-00FlBX-GK for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:27 +0000 Received: by mail-il1-x149.google.com with SMTP id b13-20020a92dccd0000b0290223ea53d878so8708824ilr.19 for ; Sun, 15 Aug 2021 17:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=yxA2cYvOw4or+4AZfWJZCSU9QyWVjXr9zaqNQ/48i2s=; b=nDtqvdQ7zdtXwYiwMQDF1s28Q9lRq1TBtvEl+wjguLSzHMES3Pf850aZrjq+l1VkiK Fucj07/fJK/i61BnxLOsPalL7upt2tFLHRujsOoNh43R4Qq1Ub/pcwk7Vi8h63ayHMWD M26bjm8VVbjK7WXmzXvj3wgfnn1F8pZojrfk/J3vw2GLKqjxQrY2ca2Bw62oTOHWH42v 4knKF0JoyrwcPu5g+9oTCbo142kzPsweaYVEm90m9r2APr0C/bzyvPL5gKpvocVWL5e/ 6tMpeTHVVge3uNusTDxpWcxoHgP0nBT0OEsVuIp/CrPkgqepYBV3TMztvlob3v85IbY7 b/kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=yxA2cYvOw4or+4AZfWJZCSU9QyWVjXr9zaqNQ/48i2s=; b=MJlIiCrFDG0jgpoihotzyCau/T6bVr3BP282T7hc3BZuejHegKYPzsc9NKLHrUfLU2 JNsQ6CTDEsnObBWndGkIesVYRrhatXbaCKFRfOeflrDHO9nC0VoK1xNDI+bgeFbm+XQx J9hR4SuUr0IdvMc2vJpPpw+X8maFd6wbNFlCZxX1lycpb7mvdhwzMaf2MUg2D8CG//9Z q73fn5KdLueIeiXHtq5EPnNf/LzOLRTR8W28cjMsb7Lw2iSGRlXTANIdAEz0+QR8vRiH td1Auz265ThY6d5dnhvOL7lYQZpXbJeRvt81z76N8dtVVMZ7v2m49m4hu+rXQmtiO5fd AXPg== X-Gm-Message-State: AOAM533mhki05gFZvNuj/h5B0ZjVzktja9KMkNm7bx+DevmpFZVAq+8P LOSRXVPVfOX3rgOSiceIE5GnzaX6XfI= X-Google-Smtp-Source: ABdhPJx644XoMFt3hlty2696xX3FxZmd66p9kDnVbuGf4x2YsF8E74EImbYhqgKOdzTd2jkXFJuzEGDoHCY= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a92:6610:: with SMTP id a16mr9329536ilc.71.1629072744206; Sun, 15 Aug 2021 17:12:24 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:13 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-4-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 3/7] KVM: arm64: Allow userspace to configure a vCPU's virtual offset From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171225_614081_3992D733 X-CRM114-Status: GOOD ( 16.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow userspace to access the guest's virtual counter-timer offset through the ONE_REG interface. The value read or written is defined to be an offset from the guest's physical counter-timer. Add some documentation to clarify how a VMM should use this and the existing CNTVCT_EL0. Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- Documentation/virt/kvm/api.rst | 10 ++++++++++ arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/arch_timer.c | 23 +++++++++++++++++++++++ arch/arm64/kvm/guest.c | 6 +++++- include/kvm/arm_arch_timer.h | 1 + 5 files changed, 40 insertions(+), 1 deletion(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index dae68e68ca23..adb04046a752 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2463,6 +2463,16 @@ arm64 system registers have the following id bit patterns:: derived from the register encoding for CNTV_CVAL_EL0. As this is API, it must remain this way. +.. warning:: + + The value of KVM_REG_ARM_TIMER_OFFSET is defined as an offset from + the guest's view of the physical counter-timer. + + Userspace should use either KVM_REG_ARM_TIMER_OFFSET or + KVM_REG_ARM_TIMER_CNT to pause and resume a guest's virtual + counter-timer. Mixed use of these registers could result in an + unpredictable guest counter value. + arm64 firmware pseudo-registers have the following bit pattern:: 0x6030 0000 0014 diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index b3edde68bc3e..949a31bc10f0 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -255,6 +255,7 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) +#define KVM_REG_ARM_TIMER_OFFSET ARM64_SYS_REG(3, 4, 14, 0, 3) /* KVM-as-firmware specific pseudo-registers */ #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index cf2f4a034dbe..9d9bac3ec40e 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -92,6 +92,18 @@ static u64 timer_get_offset(struct arch_timer_context *ctxt) } } +static u64 timer_get_guest_offset(struct arch_timer_context *ctxt) +{ + struct kvm_vcpu *vcpu = ctxt->vcpu; + + switch (arch_timer_ctx_index(ctxt)) { + case TIMER_VTIMER: + return __vcpu_sys_reg(vcpu, CNTVOFF_EL2); + default: + return 0; + } +} + static void timer_set_ctl(struct arch_timer_context *ctxt, u32 ctl) { struct kvm_vcpu *vcpu = ctxt->vcpu; @@ -852,6 +864,10 @@ int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value) timer = vcpu_vtimer(vcpu); kvm_arm_timer_write(vcpu, timer, TIMER_REG_CVAL, value); break; + case KVM_REG_ARM_TIMER_OFFSET: + timer = vcpu_vtimer(vcpu); + update_vtimer_cntvoff(vcpu, value); + break; case KVM_REG_ARM_PTIMER_CTL: timer = vcpu_ptimer(vcpu); kvm_arm_timer_write(vcpu, timer, TIMER_REG_CTL, value); @@ -896,6 +912,9 @@ u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid) case KVM_REG_ARM_TIMER_CVAL: return kvm_arm_timer_read(vcpu, vcpu_vtimer(vcpu), TIMER_REG_CVAL); + case KVM_REG_ARM_TIMER_OFFSET: + return kvm_arm_timer_read(vcpu, + vcpu_vtimer(vcpu), TIMER_REG_OFFSET); case KVM_REG_ARM_PTIMER_CTL: return kvm_arm_timer_read(vcpu, vcpu_ptimer(vcpu), TIMER_REG_CTL); @@ -933,6 +952,10 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, val = kvm_phys_timer_read() - timer_get_offset(timer); break; + case TIMER_REG_OFFSET: + val = timer_get_guest_offset(timer); + break; + default: BUG(); } diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 1dfb83578277..17fc06e2b422 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -591,7 +591,7 @@ static unsigned long num_core_regs(const struct kvm_vcpu *vcpu) * ARM64 versions of the TIMER registers, always available on arm64 */ -#define NUM_TIMER_REGS 3 +#define NUM_TIMER_REGS 4 static bool is_timer_reg(u64 index) { @@ -599,6 +599,7 @@ static bool is_timer_reg(u64 index) case KVM_REG_ARM_TIMER_CTL: case KVM_REG_ARM_TIMER_CNT: case KVM_REG_ARM_TIMER_CVAL: + case KVM_REG_ARM_TIMER_OFFSET: return true; } return false; @@ -614,6 +615,9 @@ static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) uindices++; if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices)) return -EFAULT; + uindices++; + if (put_user(KVM_REG_ARM_TIMER_OFFSET, uindices)) + return -EFAULT; return 0; } diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 9d65d4a29f81..615f9314f6a5 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -21,6 +21,7 @@ enum kvm_arch_timer_regs { TIMER_REG_CVAL, TIMER_REG_TVAL, TIMER_REG_CTL, + TIMER_REG_OFFSET, }; struct arch_timer_context { From patchwork Mon Aug 16 00:12:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E684BC4338F for ; Mon, 16 Aug 2021 00:17:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF4AC61151 for ; Mon, 16 Aug 2021 00:17:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AF4AC61151 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=5uYHhZkK1HBBGl8cZK1j7Pu+WuajPVHarK/Q1Skw460=; b=NFBe+1jvXgOk1njI6Hzvh/d6u2 PnZpR9E2WlyiTcWYVx1jsKgLezLXyaavcrHWdzz4M0T3+seDlsXDS+cy9TzjlQp2bY98RwPS40kCr T6xuZQ1BSVDmjw8T8ENkzYo9g0Z6ucu1PCN+WUdzKsWDVMKy8kBdgfD3FmsLLTCcutjz6Sh/LJ3PU D2a1ewV7rWK68jUSNmm0rbbC1m9Fiimiw3Ioxs8arWWwqb5Psv5ensyQRPGM5peaY+pU3JDPfHzeE JQkgI4VM7yn2X3Tj1aonn/Igwc6xb0+JBJbahFOCqrNdKgLb+7aajB5Daevn+hM1BodHkmH30/HS1 hufeeI1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQIU-00Fmnh-Ce; Mon, 16 Aug 2021 00:16:10 +0000 Received: from mail-io1-xd49.google.com ([2607:f8b0:4864:20::d49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEs-00FlBn-Pa for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:28 +0000 Received: by mail-io1-xd49.google.com with SMTP id k8-20020a0566022d88b02905a426848884so4683922iow.20 for ; Sun, 15 Aug 2021 17:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=E6Kp8VbK7wYZ6N9mrulVFPxuQLG+WCCQs9laQvbnKBA=; b=eK7WWUKmJs5BwvM+R2hcGD3Ji+r55jFV4Y/m0xTcQXO98TkC2SBcgDjIkEKOS9I1Dz Z+KOH8cQFMH84TGr26zZrToaIDDcz6SXm6LdwgOCkRBlwDQQ5lVdgLyuM5sH5fLSk9fc JhMeDb3aUR/SqI4YoPBMrFE4S+q+z+YOsV2INlxYp+KJ0vfmin10q/SkJ/PkzJpd6YF9 HZXZfIaCHE0BNeGw8ZyDDB0LknniqFmW5oeMGIGzpNd+2D+alqEycIL9pYhyFfyJyI+q R19Dnfa2/y4llJ/H8cnGQAjI4S4uO2CP9g91opOsuqp2kVlxEIrFtgU6V7IqCgXM47tr unWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=E6Kp8VbK7wYZ6N9mrulVFPxuQLG+WCCQs9laQvbnKBA=; b=GOaLp7yyKJVmpcyBAwoTzMzVk6j39lQIaNCw55H8r5Xgm1DsRzbBR3YlSrd+GD2ik4 GMfnEq8sL0rVHeNkXdhnHehc10zsRWoGo5z/7GONXtocIqnWVBx491ARH8OXb98gNC/k 6mvJTywZ1CQy1UXG0dZ/w9iqep66uIiDUXowzmp/qEFFlKfnumlMybCUADjxWcHjE8oD FEm1DYj6KMmNSX92IE+HbdPr2e0rcuHhfNXeJoXepaUS589toWW5pSXGvtdR+LmgvTWR +sN6puDO9TFbjKTABKH2tBrIIUFz/BokSEnMhnEGpMZtzLy+iF4/h+2cT/5FrdMofCcb vnKA== X-Gm-Message-State: AOAM532I2rsSLzcoQ1wKoA8ZZQzZ2I0B1CMGKh6wptdk7ON3c+WRhxXu fceLUBY2HjfX0DWH+gi9V1ll16KToBQ= X-Google-Smtp-Source: ABdhPJxOjPTqr7vVT3cx9Io5XzVFMI5B6VGMeC/E76yIdgKYAKoQGgpGvWdy7jxo2YMnwnmcnxIE8cMv4gU= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:1d1a:: with SMTP id i26mr147868ila.96.1629072745284; Sun, 15 Aug 2021 17:12:25 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:14 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-5-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 4/7] arm64: cpufeature: Enumerate support for FEAT_ECV >= 0x2 From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171226_883709_5059B8FD X-CRM114-Status: GOOD ( 11.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a new cpucap to indicate if the system supports full enhanced counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). Signed-off-by: Oliver Upton --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 943d31d92b5b..c7ddf9a71134 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -847,6 +847,7 @@ #define ID_AA64MMFR0_ASID_SHIFT 4 #define ID_AA64MMFR0_PARANGE_SHIFT 0 +#define ID_AA64MMFR0_ECV_PHYS 0x2 #define ID_AA64MMFR0_TGRAN4_NI 0xf #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 #define ID_AA64MMFR0_TGRAN64_NI 0xf diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0ead8bfedf20..b44cef8deacc 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .min_field_value = 1, }, + { + .desc = "Enhanced Counter Virtualization (Physical)", + .capability = ARM64_HAS_ECV2, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR0_ECV_SHIFT, + .matches = has_cpuid_feature, + .min_field_value = ID_AA64MMFR0_ECV_PHYS, + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 49305c2e6dfd..f73a30d5fb1c 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -18,6 +18,7 @@ HAS_CRC32 HAS_DCPODP HAS_DCPOP HAS_E0PD +HAS_ECV2 HAS_EPAN HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH From patchwork Mon Aug 16 00:12:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE7D6C4338F for ; Mon, 16 Aug 2021 00:18:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3C696137D for ; Mon, 16 Aug 2021 00:18:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A3C696137D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=vQZ6SVfrlkA0BXe2gWHGFSjVe8BaqD9wOhZu9Aj5SP0=; b=3FMLExXKM+zrTetD39nzodfEcT 9aVzS47ZD2Ejqzk5AcU1zAxDUbzISWQY68kjyK92dJzOK549DzFeVVofLHTSN/OvGqwIzSRKq35pQ vPQUx2fnFa66OJbfITUYa8FgdJGEwvh2vr6YcdBhjxFyOj4FH5Nf+EZP0AS81lBe4EFU1XBzmd58J pO8ge/btBTo8uZ0BB8Kv90LlgSWHzWbUvUtJMWvma52aCBpQv/dF4vPJhVnpSw1lh6OsfWgJj4YX9 83/UlSXvLKZxYTP55YSl4dtpOhdRC+kTPnlwdyt0h8IhgVp+06du8i5ecwjVAr52n6qKKdldqhs1m A30EgG9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQJI-00Fn6V-4h; Mon, 16 Aug 2021 00:17:01 +0000 Received: from mail-io1-xd4a.google.com ([2607:f8b0:4864:20::d4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEu-00FlCO-5d for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:30 +0000 Received: by mail-io1-xd4a.google.com with SMTP id c14-20020a6bfd0e0000b02905b2d3028604so2789619ioi.7 for ; Sun, 15 Aug 2021 17:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=kqHsZtsc3rsaBs8YykjTfYieWZWleao7VNediAJYDnk=; b=pBfl7TLYi2YLH2KPmg5hiwpPawDYkYoGHwz5MgNuqHogNQOycSiur/P2y49NBm+drR /Cr/PD+jyTL6ih41g24jrrVagY3NLpgLtUj7KMGNB+PWgZvQ5q3kftrWanrcKQHkYMG4 MXsF+os6IWikIejEb/aOrCg8aHt/qnJB8EHcLlal0zUwK4kYn4aP7Q7eUjySY5BwB0sB uoRPcQJDOg3Hmhj5XtcQXkZ8WMNW0jLoNQdOWmL9zjM1xhxVdC2HdjuToBMw/m2Bn1ql z9OVr+DzoxrQ4f92gctg3MtAtVc3lHqYtR/AgT6/72E6J6DzA0IvYww3or7GzwqVSGNc Bc5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=kqHsZtsc3rsaBs8YykjTfYieWZWleao7VNediAJYDnk=; b=gUvzSWaCs6UFfn45IkDSm/dMLemHAyupwpIbMTGRRIoz2rNIYG7EO7TzVEza91O9Z9 mtqBITit0cBuv8FESAadJNvV6fqyWrPlEhXIJhbPoaNU3/KNaqjPtlGNwZvTioqSbHYo 7FILtN4cUKmfAB6nEQ8xsm7gie1bJQCHC38rEGS/QTgYeEQrJIPxkNeku6lTKaptm6N6 lYoZwvigd88cWcCGGo+xWQdOMenhHwEWHE3FOGtNt8d7TO++Ro2qRCjFYQ5vMGftwgr6 p8jVe51veJWN7XXBj+UuZFL4ZZGHksLFd6DwXb+cuADde4f3lK2gqbQ8PLpJA2WhH0jJ U8Xw== X-Gm-Message-State: AOAM530qqR+elGWHftRuGve94Bu9TrrJpXqEKg7kkfHwUkDvR/71+bPl lWbijVuzLZZ4BXFEUKbwAdJex7ELF4g= X-Google-Smtp-Source: ABdhPJwUzuhENHzkbWfNuyab+2wrwAQ/8Ih1khTW27au7+6FctA+taj7GfdJ29iI5mvEVIhWGnjQzHbS5IM= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6638:1448:: with SMTP id l8mr4001325jad.55.1629072746337; Sun, 15 Aug 2021 17:12:26 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:15 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-6-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 5/7] KVM: arm64: Allow userspace to configure a guest's counter-timer offset From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171228_301086_6476EDF6 X-CRM114-Status: GOOD ( 26.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Presently, KVM provides no facilities for correctly migrating a guest that depends on the physical counter-timer. While most guests (barring NV, of course) should not depend on the physical counter-timer, an operator may wish to provide a consistent view of the physical counter-timer across migrations. Provide userspace with a new vCPU attribute to modify the guest counter-timer offset. Unlike KVM_REG_ARM_TIMER_OFFSET, this attribute is hidden from the guest's architectural state. The value offsets *both* the virtual and physical counter-timer views for the guest. Only support this attribute on ECV systems as ECV is required for hardware offsetting of the physical counter-timer. Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- Documentation/arm64/booting.rst | 7 ++ Documentation/virt/kvm/devices/vcpu.rst | 28 ++++++++ arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/arch_timer.c | 96 ++++++++++++++++++++++++- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 ++ arch/arm64/kvm/hyp/nvhe/timer-sr.c | 9 +++ arch/arm64/kvm/hyp/vhe/timer-sr.c | 5 ++ include/clocksource/arm_arch_timer.h | 1 + 10 files changed, 155 insertions(+), 2 deletions(-) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index a9192e7a231b..bfdbc9df7b55 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -311,6 +311,13 @@ Before jumping into the kernel, the following conditions must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. + For CPUs with the Enhanced Counter Virtualization (FEAT_ECV) extension + present with ID_AA64MMFR0_EL1.ECV >= 0x2: + + - if EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.ECVEn (bit 28) must be initialized to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst index 2acec3b9ef65..f240ecc174ef 100644 --- a/Documentation/virt/kvm/devices/vcpu.rst +++ b/Documentation/virt/kvm/devices/vcpu.rst @@ -139,6 +139,34 @@ configured values on other VCPUs. Userspace should configure the interrupt numbers on at least one VCPU after creating all VCPUs and before running any VCPUs. +2.2. ATTRIBUTE: KVM_ARM_VCPU_TIMER_PHYS_OFFSET +----------------------------------------- + +:Parameters: in kvm_device_attr.addr the address for the timer offset is a + pointer to a __u64 + +Returns: + + ======= ================================== + -EFAULT Error reading/writing the provided + parameter address + -ENXIO Timer offsetting not implemented + ======= ================================== + +Specifies the guest's counter-timer offset from the host's virtual counter. +The guest's physical counter value is then derived by the following +equation: + + guest_cntpct = host_cntvct - KVM_ARM_VCPU_TIMER_PHYS_OFFSET + +The guest's virtual counter value is derived by the following equation: + + guest_cntvct = host_cntvct - KVM_REG_ARM_TIMER_OFFSET + - KVM_ARM_VCPU_TIMER_PHYS_OFFSET + +KVM does not allow the use of varying offset values for different vCPUs; +the last written offset value will be broadcasted to all vCPUs in a VM. + 3. GROUP: KVM_ARM_VCPU_PVTIME_CTRL ================================== diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index aed2aa61766a..052a6f987095 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -64,6 +64,7 @@ #define __KVM_HOST_SMCCC_FUNC___pkvm_cpu_set_vector 18 #define __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize 19 #define __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc 20 +#define __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntpoff 21 #ifndef __ASSEMBLY__ @@ -199,6 +200,7 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa, extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu); extern void __kvm_timer_set_cntvoff(u64 cntvoff); +extern void __kvm_timer_set_cntpoff(u64 cntpoff); extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index c7ddf9a71134..e02b7cd574e6 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -586,6 +586,8 @@ #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) +#define SYS_CNTPOFF_EL2 sys_reg(3, 4, 14, 0, 6) + /* VHE encodings for architectural EL0/1 system registers */ #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 949a31bc10f0..70e2893c1749 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -366,6 +366,7 @@ struct kvm_arm_copy_mte_tags { #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 +#define KVM_ARM_VCPU_TIMER_PHYS_OFFSET 2 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 9d9bac3ec40e..46380c389683 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -86,8 +86,11 @@ static u64 timer_get_offset(struct arch_timer_context *ctxt) { switch(arch_timer_ctx_index(ctxt)) { case TIMER_VTIMER: + case TIMER_PTIMER: return ctxt->host_offset; default: + WARN_ONCE(1, "unrecognized timer %ld\n", + arch_timer_ctx_index(ctxt)); return 0; } } @@ -140,6 +143,7 @@ static void timer_set_offset(struct arch_timer_context *ctxt, u64 offset) { switch(arch_timer_ctx_index(ctxt)) { case TIMER_VTIMER: + case TIMER_PTIMER: ctxt->host_offset = offset; break; default: @@ -568,6 +572,11 @@ static void set_cntvoff(u64 cntvoff) kvm_call_hyp(__kvm_timer_set_cntvoff, cntvoff); } +static void set_cntpoff(u64 cntpoff) +{ + kvm_call_hyp(__kvm_timer_set_cntpoff, cntpoff); +} + static inline void set_timer_irq_phys_active(struct arch_timer_context *ctx, bool active) { int r; @@ -643,6 +652,8 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) } set_cntvoff(timer_get_offset(map.direct_vtimer)); + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + set_cntpoff(timer_get_offset(vcpu_ptimer(vcpu))); kvm_timer_unblocking(vcpu); @@ -810,6 +821,22 @@ static void update_vtimer_cntvoff(struct kvm_vcpu *vcpu, u64 cntvoff) mutex_unlock(&kvm->lock); } +static void update_ptimer_cntpoff(struct kvm_vcpu *vcpu, u64 cntpoff) +{ + struct kvm *kvm = vcpu->kvm; + u64 cntvoff; + + mutex_lock(&kvm->lock); + + /* adjustments to the physical offset also affect vtimer */ + cntvoff = timer_get_offset(vcpu_vtimer(vcpu)); + cntvoff += cntpoff - timer_get_offset(vcpu_ptimer(vcpu)); + + update_timer_offset(vcpu, TIMER_PTIMER, cntpoff, false); + update_timer_offset(vcpu, TIMER_VTIMER, cntvoff, false); + mutex_unlock(&kvm->lock); +} + void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) { struct arch_timer_cpu *timer = vcpu_timer(vcpu); @@ -1346,6 +1373,9 @@ void kvm_timer_init_vhe(void) val = read_sysreg(cnthctl_el2); val |= (CNTHCTL_EL1PCEN << cnthctl_shift); val |= (CNTHCTL_EL1PCTEN << cnthctl_shift); + + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + val |= CNTHCTL_ECV; write_sysreg(val, cnthctl_el2); } @@ -1360,7 +1390,8 @@ static void set_timer_irqs(struct kvm *kvm, int vtimer_irq, int ptimer_irq) } } -int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +static int kvm_arm_timer_set_attr_irq(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) { int __user *uaddr = (int __user *)(long)attr->addr; struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); @@ -1393,7 +1424,37 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) return 0; } -int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +static int kvm_arm_timer_set_attr_offset(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + u64 __user *uaddr = (u64 __user *)(long)attr->addr; + u64 offset; + + if (!cpus_have_final_cap(ARM64_HAS_ECV2)) + return -ENXIO; + + if (get_user(offset, uaddr)) + return -EFAULT; + + update_ptimer_cntpoff(vcpu, offset); + return 0; +} + +int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_TIMER_IRQ_VTIMER: + case KVM_ARM_VCPU_TIMER_IRQ_PTIMER: + return kvm_arm_timer_set_attr_irq(vcpu, attr); + case KVM_ARM_VCPU_TIMER_PHYS_OFFSET: + return kvm_arm_timer_set_attr_offset(vcpu, attr); + default: + return -ENXIO; + } +} + +static int kvm_arm_timer_get_attr_irq(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) { int __user *uaddr = (int __user *)(long)attr->addr; struct arch_timer_context *timer; @@ -1414,12 +1475,43 @@ int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) return put_user(irq, uaddr); } +static int kvm_arm_timer_get_attr_offset(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + u64 __user *uaddr = (u64 __user *)(long)attr->addr; + u64 offset; + + if (!cpus_have_final_cap(ARM64_HAS_ECV2)) + return -ENXIO; + + offset = timer_get_offset(vcpu_ptimer(vcpu)); + return put_user(offset, uaddr); +} + +int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_TIMER_IRQ_VTIMER: + case KVM_ARM_VCPU_TIMER_IRQ_PTIMER: + return kvm_arm_timer_get_attr_irq(vcpu, attr); + case KVM_ARM_VCPU_TIMER_PHYS_OFFSET: + return kvm_arm_timer_get_attr_offset(vcpu, attr); + default: + return -ENXIO; + } +} + int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) { switch (attr->attr) { case KVM_ARM_VCPU_TIMER_IRQ_VTIMER: case KVM_ARM_VCPU_TIMER_IRQ_PTIMER: return 0; + case KVM_ARM_VCPU_TIMER_PHYS_OFFSET: + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + return 0; + break; } return -ENXIO; diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 2da6aa8da868..f1b8da4737dc 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -68,6 +68,11 @@ static void handle___kvm_timer_set_cntvoff(struct kvm_cpu_context *host_ctxt) __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); } +static void handle___kvm_timer_set_cntpoff(struct kvm_cpu_context *host_ctxt) +{ + __kvm_timer_set_cntpoff(cpu_reg(host_ctxt, 1)); +} + static void handle___kvm_enable_ssbs(struct kvm_cpu_context *host_ctxt) { u64 tmp; @@ -185,6 +190,7 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__pkvm_host_share_hyp), HANDLE_FUNC(__pkvm_create_private_mapping), HANDLE_FUNC(__pkvm_prot_finalize), + HANDLE_FUNC(__kvm_timer_set_cntpoff), }; static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) diff --git a/arch/arm64/kvm/hyp/nvhe/timer-sr.c b/arch/arm64/kvm/hyp/nvhe/timer-sr.c index 9072e71693ba..e98a949f5227 100644 --- a/arch/arm64/kvm/hyp/nvhe/timer-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/timer-sr.c @@ -15,6 +15,11 @@ void __kvm_timer_set_cntvoff(u64 cntvoff) write_sysreg(cntvoff, cntvoff_el2); } +void __kvm_timer_set_cntpoff(u64 cntpoff) +{ + write_sysreg_s(cntpoff, SYS_CNTPOFF_EL2); +} + /* * Should only be called on non-VHE systems. * VHE systems use EL2 timers and configure EL1 timers in kvm_timer_init_vhe(). @@ -26,6 +31,8 @@ void __timer_disable_traps(struct kvm_vcpu *vcpu) /* Allow physical timer/counter access for the host */ val = read_sysreg(cnthctl_el2); val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + val &= ~CNTHCTL_ECV; write_sysreg(val, cnthctl_el2); } @@ -42,6 +49,8 @@ void __timer_enable_traps(struct kvm_vcpu *vcpu) * Physical counter access is allowed */ val = read_sysreg(cnthctl_el2); + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + val |= CNTHCTL_ECV; val &= ~CNTHCTL_EL1PCEN; val |= CNTHCTL_EL1PCTEN; write_sysreg(val, cnthctl_el2); diff --git a/arch/arm64/kvm/hyp/vhe/timer-sr.c b/arch/arm64/kvm/hyp/vhe/timer-sr.c index 4cda674a8be6..231e16a071a5 100644 --- a/arch/arm64/kvm/hyp/vhe/timer-sr.c +++ b/arch/arm64/kvm/hyp/vhe/timer-sr.c @@ -10,3 +10,8 @@ void __kvm_timer_set_cntvoff(u64 cntvoff) { write_sysreg(cntvoff, cntvoff_el2); } + +void __kvm_timer_set_cntpoff(u64 cntpoff) +{ + write_sysreg_s(cntpoff, SYS_CNTPOFF_EL2); +} diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 73c7139c866f..7252ffa3d675 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -21,6 +21,7 @@ #define CNTHCTL_EVNTEN (1 << 2) #define CNTHCTL_EVNTDIR (1 << 3) #define CNTHCTL_EVNTI (0xF << 4) +#define CNTHCTL_ECV (1 << 12) enum arch_timer_reg { ARCH_TIMER_REG_CTRL, From patchwork Mon Aug 16 00:12:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00084C4338F for ; Mon, 16 Aug 2021 00:19:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B6E3C61151 for ; Mon, 16 Aug 2021 00:19:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B6E3C61151 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=1CPu0kqVkGPHKFhaHmTO1E3trBDWjySPqjPUG6coE58=; b=OpRBYBSA6ePgoJrTqBRxVPdD0u IdvAxW2dbaZI6zLih0mgztCSp9yYMmtNpzU1wc6aDPgtkOrlxerWjnBkMj3qF+UW1NkQZmMqCXINb 1zGxSd/bk7T2VioXAR5q/5NNG7n9QPN30YFtp7a2HkOSBI8m3oTQu9W7ibYAWAZgwRjFGA3Twkult ZlJT4lZq2Bbeg4CpmE0cRxofwZtGFndLK2CG2zfQn4qARZ0dF5KeRm/7DKyQ5/c/K7Zuzh2Jrbvm1 EJ9VZsiODXpgyJ+GnmQnvDv2BUfkyGsjamqak3XwRpoAMHVPFGFj5Ov7wit0/E9/yV9/DOdcEySg9 UN8sKwWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQJs-00FnMG-Cw; Mon, 16 Aug 2021 00:17:37 +0000 Received: from mail-qv1-xf4a.google.com ([2607:f8b0:4864:20::f4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEv-00FlD5-23 for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:30 +0000 Received: by mail-qv1-xf4a.google.com with SMTP id n14-20020a0c9d4e0000b0290354a5f8c800so11767695qvf.17 for ; Sun, 15 Aug 2021 17:12:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=IzZpuEsgwV0AULnFn0VDAkOlC3SkP0x8cjQf8LHfPG8=; b=Z6KJIWUoRZm4gv1SxUSGM1H6/YnrARuwOEm5BdLr/NIw2XcC76fYJA/umAxe1eKVRy roA/HxRxx9DEMfnoH0VYW9Dq7WKsVqbZsfl1UXp5C/+7nEOY8tPdtSNnp4an2z/fhNP/ /hSJ1Yvy7h7zW7dQBoz3hSL9+ruqcYlSuE/QwBGN4ED8WT9ee1x0wY5zXsU7K4Wilody ju6OQD7sBLOx6tKwDvk16FD6QRCIOyUPis0cP8sn5jutVX57b7PmSIos9ixZ9RnXzIZA G4LmfbIOdX/Jzm+JanelRb5nJzx8rt9LZLR+Ox5DuoF1uojBAVpWBWsEZP0xlBp886dY UhXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=IzZpuEsgwV0AULnFn0VDAkOlC3SkP0x8cjQf8LHfPG8=; b=j7ClDX3YclTcWqcfn4N7AL2vkkOtsZvGfl0ZZo1p/Au3QbJ3SEPbDvSsjfJMXjo32D Y7Jbi8dEFNPmy+xSJSnXsk8PyhtY1TddWrxgU3UwNJFtXXTj0WDm2WyRHiIFXFF10m3F uGHx3spqiZ6TJIPnfggMMA3hp8EDoO8T28duDx/DvMOAl2bZkqaPOdb8D/yFFCsO97Ty puSCKiWD5f8/l71JwfPcui9mNRp6tUXhPICYa/tvMJMbgeKQhf9Q8sKaKf2PeNx26LDR pF5Orz7gCxbh0Rc55gq3Dc0ryTTXvh6fTb2Nr63Pe8ezBO9LgzfW9z+o53eoXd7gbOug 2ADQ== X-Gm-Message-State: AOAM532LYQdGrtwuHA1Ls++DEwszK7PQgpcQsxYgZ2x1HR7xQgGpWhYs iVyuJip/HikRvkzuK4hJXuXyHdyet68= X-Google-Smtp-Source: ABdhPJyq1E1IRX+IFCz2UT4Lu7i7B0G3RsUFCvBiLDi44WCVFhrddU+e2oHM6bxVIVMm1WK477KidWJeex0= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6214:10c4:: with SMTP id r4mr13783414qvs.58.1629072747465; Sun, 15 Aug 2021 17:12:27 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:16 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-7-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 6/7] KVM: arm64: Configure timer traps in vcpu_load() for VHE From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171229_176647_1D34C174 X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In preparation for emulated physical counter-timer offsetting, configure traps on every vcpu_load() for VHE systems. As before, these trap settings do not affect host userspace, and are only active for the guest. Suggested-by: Marc Zyngier Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- arch/arm64/kvm/arch_timer.c | 10 +++++++--- arch/arm64/kvm/arm.c | 4 +--- include/kvm/arm_arch_timer.h | 2 -- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 46380c389683..1689c2e20cd3 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -51,6 +51,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, struct arch_timer_context *timer, enum kvm_arch_timer_regs treg); +static void kvm_timer_enable_traps_vhe(void); u32 timer_get_ctl(struct arch_timer_context *ctxt) { @@ -663,6 +664,9 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) if (map.emul_ptimer) timer_emulate(map.emul_ptimer); + + if (has_vhe()) + kvm_timer_enable_traps_vhe(); } bool kvm_timer_should_notify_user(struct kvm_vcpu *vcpu) @@ -1355,12 +1359,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) } /* - * On VHE system, we only need to configure the EL2 timer trap register once, - * not for every world switch. + * On VHE system, we only need to configure the EL2 timer trap register on + * vcpu_load(), but not every world switch into the guest. * The host kernel runs at EL2 with HCR_EL2.TGE == 1, * and this makes those bits have no effect for the host kernel execution. */ -void kvm_timer_init_vhe(void) +static void kvm_timer_enable_traps_vhe(void) { /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */ u32 cnthctl_shift = 10; diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 0de4b41c3706..f882a7fb3a1b 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1559,9 +1559,7 @@ static void cpu_hyp_reinit(void) cpu_hyp_reset(); - if (is_kernel_in_hyp_mode()) - kvm_timer_init_vhe(); - else + if (!is_kernel_in_hyp_mode()) cpu_init_hyp_mode(); cpu_set_hyp_vector(); diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 615f9314f6a5..254653b42da0 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -87,8 +87,6 @@ u64 kvm_phys_timer_read(void); void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu); -void kvm_timer_init_vhe(void); - bool kvm_arch_timer_get_input_level(int vintid); #define vcpu_timer(v) (&(v)->arch.timer_cpu) From patchwork Mon Aug 16 00:12:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12437523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17740C4338F for ; Mon, 16 Aug 2021 00:21:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C903A61250 for ; Mon, 16 Aug 2021 00:21:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C903A61250 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=EN91qUtRMjWWUi4II7Nk4R+nhGWodcDv7fpHCQqGzBw=; b=YJBuBnTpo0YDJsLCbAkOviqWxx Yx5TWvqkCS112s7jy+eXY73s9rGalSqWHKhPpA4nxisuFhQB190ydQN3L1WHmTSThhlOKGpkwvyPU mGglvdqfIL9iALfX2+Y9K+Y5boyhzBeXfBygNaISg2DdSMGkJZVd5jLJ00wv60+yYCNo5Mu5jXaHb Qz+4kUOdhY1sWrTuxUgKCzS8aD9uI3B5awCBaxCnr1Zy8CN78Jy+28OB6pN8pEO8MFt+VioKn3IcR /W+YpWaQyWcuBd9K36KJ8N2xtA6I8emPg5AdGSyRBA49BrC7ynIaiynsCRdhd7+SVjkMrwbqmUXiJ j6FsT5Ng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQKy-00Fnmj-6t; Mon, 16 Aug 2021 00:18:45 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFQEv-00FlDd-UL for linux-arm-kernel@lists.infradead.org; Mon, 16 Aug 2021 00:12:32 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id f3-20020a25cf030000b029055a2303fc2dso15054577ybg.11 for ; Sun, 15 Aug 2021 17:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=10Jw6wv5f8g0YFvtptDq44Mn28B+Ho/XFC6x/+px8Jk=; b=gRF2kZWPiNTNBF8rdEwFW/mIlkRiajRYjn/LV7U4oGIMEj2P6ZR+kLbq6lKxHr/tPB NqZgYJQILBazx5IH9eSTClPREQffNoKr35iKG/toTL+NHJRLjt7lijMDiFXf0Napejm/ FEpzlWloHyCxhD47vxS9bfsOdtWxWShkds+RGn+WvBXuvyXlcUDzqnv76KHfenqvYNDX hOY2oqNHopp8fGC/+P2FNBBz4AGv3I8dR/QyXLxtu22JWqGKi0U7G6+dAcjqTwD+e0m1 kv1qKyHInhYHJSQ+4kb7nnnTVQeTn8Pv1aLlipxmOlzEXEiGgOnQpeBf+26/5lu/lW4b K6LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=10Jw6wv5f8g0YFvtptDq44Mn28B+Ho/XFC6x/+px8Jk=; b=KU+eDXaw36ndYq35KfBN8h4204BI4VU3mXRuXdEQzEmcpZhI7gjtAEfkNWug9GAySO UViW6V96iXirUB9IrG0kM5sUtG6GX2rEruwPrzMCamlrM9XLHeZj2rP9lylru85uc7Zr aSsnUs3UYShPRp50VE4B29q+Vr/4oNmHiqcZeHgb1S0y6c27Aa0I1N87EOxI/B9V/eiW 7qS3986Yroo56A+DNSVEh7F79/bhsRLX2qQ6NcTMXWKkbQo62hQh0HzxIXPNXt47uvaO PnSuZOqoIdzkX4FmcLmZcJk8DlenyFzdgAOjDMV3xbj32snq2ADap+4FOIrRfbh8kaP7 07qA== X-Gm-Message-State: AOAM530Rs9of9Hn6wu9tZP1otmsqkZPoP+0F+K6gEnTAklsORyv7XchT j508Vfj9Fr0O81lwwnRQjYOOjKQoAWM= X-Google-Smtp-Source: ABdhPJztz5C253+NtWzjQSwoelAaDfRRtU7/I5kt15U8RETLbtxIiOZ6HZ/kktZIo5RBhkz+6dG8DZtVEe4= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a25:4091:: with SMTP id n139mr17460918yba.425.1629072748385; Sun, 15 Aug 2021 17:12:28 -0700 (PDT) Date: Mon, 16 Aug 2021 00:12:17 +0000 In-Reply-To: <20210816001217.3063400-1-oupton@google.com> Message-Id: <20210816001217.3063400-8-oupton@google.com> Mime-Version: 1.0 References: <20210816001217.3063400-1-oupton@google.com> X-Mailer: git-send-email 2.33.0.rc1.237.g0d66db33f3-goog Subject: [PATCH v7 7/7] KVM: arm64: Emulate physical counter offsetting on non-ECV systems From: Oliver Upton To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Cc: Paolo Bonzini , Sean Christopherson , Marc Zyngier , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210815_171230_060987_34105CD5 X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Unfortunately, ECV hasn't yet arrived in any tangible hardware. At the same time, controlling the guest view of the physical counter-timer is useful. Support guest counter-timer offsetting on non-ECV systems by trapping guest accesses to the physical counter-timer. Emulate reads of the physical counter in the fast exit path. Signed-off-by: Oliver Upton Reviewed-by: Andrew Jones --- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/arch_timer.c | 47 +++++++++++++------------ arch/arm64/kvm/hyp/include/hyp/switch.h | 32 +++++++++++++++++ arch/arm64/kvm/hyp/nvhe/timer-sr.c | 11 ++++-- include/kvm/arm_arch_timer.h | 3 ++ 5 files changed, 71 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e02b7cd574e6..b468acf7add0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -505,6 +505,8 @@ #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) +#define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) +#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 1689c2e20cd3..625762c4234f 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -51,7 +51,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, struct arch_timer_context *timer, enum kvm_arch_timer_regs treg); -static void kvm_timer_enable_traps_vhe(void); +static void kvm_timer_enable_traps_vhe(struct kvm_vcpu *vcpu); u32 timer_get_ctl(struct arch_timer_context *ctxt) { @@ -179,8 +179,13 @@ static void get_timer_map(struct kvm_vcpu *vcpu, struct timer_map *map) { if (has_vhe()) { map->direct_vtimer = vcpu_vtimer(vcpu); - map->direct_ptimer = vcpu_ptimer(vcpu); - map->emul_ptimer = NULL; + if (!ptimer_emulation_required(vcpu)) { + map->direct_ptimer = vcpu_ptimer(vcpu); + map->emul_ptimer = NULL; + } else { + map->direct_ptimer = NULL; + map->emul_ptimer = vcpu_ptimer(vcpu); + } } else { map->direct_vtimer = vcpu_vtimer(vcpu); map->direct_ptimer = NULL; @@ -666,7 +671,7 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) timer_emulate(map.emul_ptimer); if (has_vhe()) - kvm_timer_enable_traps_vhe(); + kvm_timer_enable_traps_vhe(vcpu); } bool kvm_timer_should_notify_user(struct kvm_vcpu *vcpu) @@ -1364,22 +1369,29 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) * The host kernel runs at EL2 with HCR_EL2.TGE == 1, * and this makes those bits have no effect for the host kernel execution. */ -static void kvm_timer_enable_traps_vhe(void) +static void kvm_timer_enable_traps_vhe(struct kvm_vcpu *vcpu) { /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */ u32 cnthctl_shift = 10; - u64 val; + u64 val, mask; + + mask = CNTHCTL_EL1PCEN << cnthctl_shift; + mask |= CNTHCTL_EL1PCTEN << cnthctl_shift; - /* - * VHE systems allow the guest direct access to the EL1 physical - * timer/counter. - */ val = read_sysreg(cnthctl_el2); - val |= (CNTHCTL_EL1PCEN << cnthctl_shift); - val |= (CNTHCTL_EL1PCTEN << cnthctl_shift); if (cpus_have_final_cap(ARM64_HAS_ECV2)) val |= CNTHCTL_ECV; + + /* + * VHE systems allow the guest direct access to the EL1 physical + * timer/counter if offsetting isn't requested on a non-ECV system. + */ + if (ptimer_emulation_required(vcpu)) + val &= ~mask; + else + val |= mask; + write_sysreg(val, cnthctl_el2); } @@ -1434,9 +1446,6 @@ static int kvm_arm_timer_set_attr_offset(struct kvm_vcpu *vcpu, u64 __user *uaddr = (u64 __user *)(long)attr->addr; u64 offset; - if (!cpus_have_final_cap(ARM64_HAS_ECV2)) - return -ENXIO; - if (get_user(offset, uaddr)) return -EFAULT; @@ -1485,9 +1494,6 @@ static int kvm_arm_timer_get_attr_offset(struct kvm_vcpu *vcpu, u64 __user *uaddr = (u64 __user *)(long)attr->addr; u64 offset; - if (!cpus_have_final_cap(ARM64_HAS_ECV2)) - return -ENXIO; - offset = timer_get_offset(vcpu_ptimer(vcpu)); return put_user(offset, uaddr); } @@ -1511,11 +1517,8 @@ int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) switch (attr->attr) { case KVM_ARM_VCPU_TIMER_IRQ_VTIMER: case KVM_ARM_VCPU_TIMER_IRQ_PTIMER: - return 0; case KVM_ARM_VCPU_TIMER_PHYS_OFFSET: - if (cpus_have_final_cap(ARM64_HAS_ECV2)) - return 0; - break; + return 0; } return -ENXIO; diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index e4a2f295a394..71dd613438c2 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -405,6 +406,34 @@ static inline bool __hyp_handle_ptrauth(struct kvm_vcpu *vcpu) return true; } +static inline u64 __timer_read_cntpct(struct kvm_vcpu *vcpu) +{ + return __arch_counter_get_cntpct() - vcpu_ptimer(vcpu)->host_offset; +} + +static inline bool __hyp_handle_counter(struct kvm_vcpu *vcpu) +{ + u32 sysreg; + int rt; + u64 rv; + + if (cpus_have_final_cap(ARM64_HAS_ECV2)) + return false; + + if (kvm_vcpu_trap_get_class(vcpu) != ESR_ELx_EC_SYS64) + return false; + + sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); + if (sysreg != SYS_CNTPCT_EL0 && sysreg != SYS_CNTPCTSS_EL0) + return false; + + rt = kvm_vcpu_sys_get_rt(vcpu); + rv = __timer_read_cntpct(vcpu); + vcpu_set_reg(vcpu, rt, rv); + __kvm_skip_instr(vcpu); + return true; +} + /* * Return true when we were able to fixup the guest exit and should return to * the guest, false when we should restore the host state and return to the @@ -439,6 +468,9 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) if (*exit_code != ARM_EXCEPTION_TRAP) goto exit; + if (__hyp_handle_counter(vcpu)) + goto guest; + if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) && kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 && handle_tx2_tvm(vcpu)) diff --git a/arch/arm64/kvm/hyp/nvhe/timer-sr.c b/arch/arm64/kvm/hyp/nvhe/timer-sr.c index e98a949f5227..8c19cd42d445 100644 --- a/arch/arm64/kvm/hyp/nvhe/timer-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/timer-sr.c @@ -46,12 +46,19 @@ void __timer_enable_traps(struct kvm_vcpu *vcpu) /* * Disallow physical timer access for the guest - * Physical counter access is allowed */ val = read_sysreg(cnthctl_el2); if (cpus_have_final_cap(ARM64_HAS_ECV2)) val |= CNTHCTL_ECV; val &= ~CNTHCTL_EL1PCEN; - val |= CNTHCTL_EL1PCTEN; + + /* + * Disallow physical counter access for the guest if offsetting is + * requested on a non-ECV system. + */ + if (ptimer_emulation_required(vcpu)) + val &= ~CNTHCTL_EL1PCTEN; + else + val |= CNTHCTL_EL1PCTEN; write_sysreg(val, cnthctl_el2); } diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 254653b42da0..13b72b5ba169 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -96,6 +96,9 @@ bool kvm_arch_timer_get_input_level(int vintid); #define arch_timer_ctx_index(ctx) ((ctx) - vcpu_timer((ctx)->vcpu)->timers) +#define ptimer_emulation_required(v) \ + (!cpus_have_final_cap(ARM64_HAS_ECV2) && vcpu_ptimer(v)->host_offset) + u64 kvm_arm_timer_read_sysreg(struct kvm_vcpu *vcpu, enum kvm_arch_timers tmr, enum kvm_arch_timer_regs treg);