From patchwork Mon Aug 16 19:53:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12439153 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 779ACC4338F for ; Mon, 16 Aug 2021 19:53:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5613360F55 for ; Mon, 16 Aug 2021 19:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231776AbhHPTyE (ORCPT ); Mon, 16 Aug 2021 15:54:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:45126 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231613AbhHPTyB (ORCPT ); Mon, 16 Aug 2021 15:54:01 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id DB07461029; Mon, 16 Aug 2021 19:53:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629143609; bh=DIaYlAqGSSNogck6c8+7tffKBZEzgkCKP9DQtTZZp2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i1lj1zZWeDOIJvSC/PQpmO9GD/1bR5M3AvJBbXPbaBp7TnVPzmW7IH5aTO8MMVO0h Amt/B6bPl7CzJRTXW54bun3W/ZWNE5574yXaWuzpuzfSO3hjsv8apilrGcHguLxvgE 44sISCynwRiw8Xk1WCTpQiXkfWWGY3m8sCGMxRQUZld/bXHP8px7nllvzkkU5fbQDG fry1DQayQYDVvch1CfyVneLC2ocq0M2mHgI9Ex88/9B3TVof6fQ98hWPXg1uyySUbR D81m4BG5DGJOvZfNNfegPeiP7CrqcpXNCDxD0oXjAMqjT/hao+vKMONlnqoC/A7b7q ITmcH0LW00F5g== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mFifn-003CSx-NK; Mon, 16 Aug 2021 21:53:27 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: PCI: kirin: fix bus-range Date: Mon, 16 Aug 2021 21:53:25 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Using bus-range = <0 1> causes a runtime warning: [ 5.363450] pci_bus 0000:00: root bus resource [bus 00-01] [ 5.396998] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-01] (conflicts with (null) [bus 00-01]) [ 5.284831] pci 0000:00:00.0: PCI bridge to [bus 01-ff] On Kirin 960, changing to bus-range = <0 0xff> produces a cleaner log. Kirin 970 is more complex, so better to just drop bus-range as a hole. Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/pci/hisilicon,kirin-pcie.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index c0551d2e606d..d05deebe9dbb 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -66,7 +66,7 @@ examples: <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; reg-names = "dbi", "apb", "phy", "config"; - bus-range = <0x0 0x1>; + bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -97,7 +97,6 @@ examples: <0x0 0xfc180000 0x0 0x1000>, <0x0 0xf5000000 0x0 0x2000>; reg-names = "dbi", "apb", "config"; - bus-range = <0x0 0x1>; msi-parent = <&its_pcie>; #address-cells = <3>; #size-cells = <2>; From patchwork Mon Aug 16 19:53:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12439155 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 208C4C43214 for ; Mon, 16 Aug 2021 19:53:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04179610FA for ; Mon, 16 Aug 2021 19:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231796AbhHPTyE (ORCPT ); Mon, 16 Aug 2021 15:54:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:45116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231551AbhHPTyB (ORCPT ); Mon, 16 Aug 2021 15:54:01 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D844060FDA; Mon, 16 Aug 2021 19:53:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629143609; bh=caLJfVCBrhHltvej9gDHMlPcVZp5tUN5o8tTf2UDPNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q+tPPhtyI67B8799IQbsPrgjH5wg6OQNU5dFbMxi4ewmqnbvS6PYkkDRdP1ERu2Rk TuBxHDmN7pT/7XP7oi8nzbEVKaSEqIq6xbR3KFnZp8nwS8wnLUp+HzbfFPErM1fYxu Fe1Ml0C69ADkFQPv1QjlKo33hH5tOpPUH7oFs+sf93qNqaAEFpFgZSAYFcQPFXaDLB TH95jMG2La4yLViekw/nlJC/QD14MqotwBukFuX3OE67WJJ5irvqUdNVtVLM9LEL4o 8+74piwgH+EEyPmy8woP4pZDcUHgabNr3ZohvAAgJ32LQUX4MEw0p77u4RSblcuc3M EHhHvfX4peYBQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mFifn-003CT1-Oy; Mon, 16 Aug 2021 21:53:27 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 2/2] dt-bindings: PCI: kirin: fix HiKey970 example Date: Mon, 16 Aug 2021 21:53:26 +0200 Message-Id: <19e33efca23c7cd8644a5fd6ecb62fddc47ff108.1629143524.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The given example doesn't produce all of_nodes at sysfs. Update it to reflect what's actually working. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 63 ++++++++++--------- 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index d05deebe9dbb..5617a1b46d1e 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -97,7 +97,6 @@ examples: <0x0 0xfc180000 0x0 0x1000>, <0x0 0xf5000000 0x0 0x2000>; reg-names = "dbi", "apb", "config"; - msi-parent = <&its_pcie>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -116,43 +115,51 @@ examples: <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&gpio7 0 0>; hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>; - - pcie@0 { // Lane 0: PCIe switch: Bus 1, Device 0 - reg = <0 0 0 0 0>; + pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0 + reg = <0x80 0 0 0 0>; compatible = "pciclass,0604"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; ranges; - pcie@1,0 { // Lane 4: M.2 - reg = <0x800 0 0 0 0>; + + pcie@0,0 { // Lane 0: upstream + reg = <0 0 0 0 0>; compatible = "pciclass,0604"; device_type = "pci"; - reset-gpios = <&gpio3 1 0>; - clkreq-gpios = <&gpio27 3 0 >; - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - pcie@5,0 { // Lane 5: Mini PCIe - reg = <0x2800 0 0 0 0>; - compatible = "pciclass,0604"; - device_type = "pci"; - reset-gpios = <&gpio27 4 0 >; - clkreq-gpios = <&gpio17 0 0 >; - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - pcie@7,0 { // Lane 6: Ethernet - reg = <0x3800 0 0 0 0>; - compatible = "pciclass,0604"; - device_type = "pci"; - reset-gpios = <&gpio25 2 0 >; - clkreq-gpios = <&gpio20 6 0 >; #address-cells = <3>; #size-cells = <2>; ranges; + + pcie@1,0 { // Lane 4: M.2 + reg = <0x0800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio3 1 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@5,0 { // Lane 5: Mini PCIe + reg = <0x2800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio27 4 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@7,0 { // Lane 6: Ethernet + reg = <0x03800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio25 2 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; };