From patchwork Fri Dec 7 09:55:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 10717757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 228D117DB for ; Fri, 7 Dec 2018 09:56:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1146F2E700 for ; Fri, 7 Dec 2018 09:56:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 04CA82E747; Fri, 7 Dec 2018 09:56:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 937742E700 for ; Fri, 7 Dec 2018 09:56:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726006AbeLGJ4a (ORCPT ); Fri, 7 Dec 2018 04:56:30 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:44392 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725989AbeLGJ4Q (ORCPT ); Fri, 7 Dec 2018 04:56:16 -0500 Received: by mail-wr1-f65.google.com with SMTP id z5so3161185wrt.11 for ; Fri, 07 Dec 2018 01:56:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bxxkWbXvkYGqIeLqYBC5ySezjbblFHISKHwaIRuZ2sA=; b=CLZtFOZjBDIyzPIOLBqVmvJQLCJ7qRJHWugIZ8yGyxM+c9KR/1lXDS7A7hkSr8VfuO By4e23wgjXQ4PyqlklRLqrrbQTKByzzYwQJZwvrPN1zJR+y4PrsPT9+i4xnyCDTzND67 wKpNNeYqw+YHdvW/oCGg3EWeRRJQ6YtwXKq4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bxxkWbXvkYGqIeLqYBC5ySezjbblFHISKHwaIRuZ2sA=; b=tV4ONnu36eyphTH8T+X10TvZORbjGKpPLJCQfD6p42D3rFwDgEIJqU2k/c3mqGtHwY eC2zCgPSlaC0dKS+CGSgVw/KA5pzKdqnf8GOf6ifDeTBQYuAlOcbjn4nieyvFQBxtcgf pRkS3BGbFLarl2D+IC4jper7zMzK90ts+RivOBQhC3prOqeySgdUBLrdoC4lZKgdoUat lsDFGb00/6Qw+3HmHeiFF58u39PgrX7PcjpCeExwV2ahPUY3xnjGwcPTaOra2tJV7avV tt0/EQadXg444JFEH5h9DCRSuPME/gjNWjDNSjibbDDKGBKRNP0m87rGhsMg/oVKunKj 13ZA== X-Gm-Message-State: AA+aEWYGLrDY+4dsxY3vXmL7Yfef/IlnM2s21fAZ/6jLo61aAWe/vmIz 9+Uwjktk90cDcYn+QxeDPdO52g== X-Google-Smtp-Source: AFSGD/Xtb9f+h56HjFu8kVZbjl8aVLmpTM7BWjoMxaRvdCV8sesVt3l0BhAJQjOji98kXjdlJLXISw== X-Received: by 2002:a5d:480d:: with SMTP id l13mr1309494wrq.175.1544176573927; Fri, 07 Dec 2018 01:56:13 -0800 (PST) Received: from localhost.localdomain (58.red-81-47-145.staticip.rima-tde.net. [81.47.145.58]) by smtp.gmail.com with ESMTPSA id h129sm3153776wma.0.2018.12.07.01.56.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Dec 2018 01:56:13 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, mark.rutland@arm.com, kishon@ti.com Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.guo@linaro.org, vkoul@kernel.org Subject: [PATCH 1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings Date: Fri, 7 Dec 2018 10:55:57 +0100 Message-Id: <1544176558-7946-2-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544176558-7946-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1544176558-7946-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Vinod Koul --- .../devicetree/bindings/usb/qcom,usb-ssphy.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt new file mode 100644 index 0000000..fcf4e01 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt @@ -0,0 +1,78 @@ +Qualcomm Synopsys 1.0.0 SS phy controller +=========================================== + +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm +chipsets + +Required properties: + +- compatible: + Value type: + Definition: Should contain "qcom,usb-ssphy". + +- reg: + Value type: + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: + Definition: Should be 0. See phy/phy-bindings.txt for details. + +- clocks: + Value type: + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + pipe clocks. + +- clock-names: + Value type: + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "pipe". + +- vdd-supply: + Value type: + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: + Definition: phandle to the regulator 1.8V supply node. + +- qcom,vdd-voltage-level: + Value type: + Definition: This is a list of three integer values where + each value corresponding to voltage corner in uV. + +Optional child nodes: + +- vbus-supply: + Value type: + Definition: phandle to the VBUS supply node. + +- resets: + Value type: + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and COR resets. + +- reset-names: + Value type: + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "com" and "phy". + +Example: + +usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + vbus-supply = <&usb3_vbus_reg>; + qcom,vdd-voltage-level = <0 1050000 1050000>; +}; From patchwork Fri Dec 7 09:55:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 10717751 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C9DC17DB for ; Fri, 7 Dec 2018 09:56:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A3A12E700 for ; Fri, 7 Dec 2018 09:56:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E74B2E748; Fri, 7 Dec 2018 09:56:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 729FF2E700 for ; Fri, 7 Dec 2018 09:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726029AbeLGJ4S (ORCPT ); Fri, 7 Dec 2018 04:56:18 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:35095 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726053AbeLGJ4R (ORCPT ); Fri, 7 Dec 2018 04:56:17 -0500 Received: by mail-wm1-f68.google.com with SMTP id c126so3870797wmh.0 for ; Fri, 07 Dec 2018 01:56:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aYZfeTLKa/S3KhYjr+S7UmShnKTAgn7a31CkqqADO3E=; b=OE5INQ7kDVh5m1FO5In67bAXMmkmvlwp33b0tsOoPeu5N+TofElrh7jEZsU9pcpvgf cTI9wpGgjj9ygRomGqNgzR6F+cArXU2jbt8fZQ3HF+UffOSkDdMY20/dih+fcxkMlCnA NQdqSK42+HV9r8Gr5r5RCzm8UAMJUlyrahdeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aYZfeTLKa/S3KhYjr+S7UmShnKTAgn7a31CkqqADO3E=; b=rz0AGx0qJ1ktQTsIXej+bu4oR6cxIGmUBQP98mbtYRFKw2GU2qmHUIUgJ/POWnIXyK GSaw8XcNKk/U/r+5opDuJw9YkCekw0M1X/znhcQu3P646+uMCbz9bYgUS+4sPRc2jH3b bnNPPiZUHJoNmT1Ns6J/ZVfKJrc/CoLm8XVd2Va53/0I9un7UanjZfsjK3xc785kUpbK JdypY2stHHElxDv0ix8SlWRnqZL9TuilkInPM7GDeJDL8sLVbIzUCE9Ta/u8uD2iwg70 HHYuO9nuneuSZ9uGp+/sR7Ryo2Fj5urGlBMmX0nNBTrYi6b10DeqqRKaiUchYKQJOYv6 swUg== X-Gm-Message-State: AA+aEWZgiRvkgcvnpJi/ecsLTzEtAO90ArihppG1g0DiXE2b5GAJLGRM q1yV4w72rg8wzQXOD0NZ/Ak3Ng== X-Google-Smtp-Source: AFSGD/W3pC9DfykISpvAzkE32qxIXL41S/B/WPkTz429aMkmYg7oPaa1NEh6ilX6rPTdwX7YgzTJ3g== X-Received: by 2002:a1c:e3d7:: with SMTP id a206mr1738700wmh.80.1544176575153; Fri, 07 Dec 2018 01:56:15 -0800 (PST) Received: from localhost.localdomain (58.red-81-47-145.staticip.rima-tde.net. [81.47.145.58]) by smtp.gmail.com with ESMTPSA id h129sm3153776wma.0.2018.12.07.01.56.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Dec 2018 01:56:14 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, mark.rutland@arm.com, kishon@ti.com Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.guo@linaro.org, vkoul@kernel.org Subject: [PATCH 2/2] phy: qualcomm: usb: Add Super-Speed PHY driver Date: Fri, 7 Dec 2018 10:55:58 +0100 Message-Id: <1544176558-7946-3-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544176558-7946-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1544176558-7946-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shawn Guo Driver to control the Synopsys SS PHY 1.0.0 implemeneted in QCS404 Based on Sriharsha Allenki's original code. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Shawn Guo Reviewed-by: Vinod Koul --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 340 +++++++++++++++++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index c7b5ee8..35a5a67 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -92,3 +92,14 @@ config PHY_QCOM_USB_HS_SNPS_28NM Enable this to support the Synopsys 28nm Femto USB PHY on Qualcomm chips. This driver supports the high-speed PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB SS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on Qualcomm + chips. This driver supports the PHY which uses the QSCRATCH-based + register set for its control sequences, normally paired with newer + DWC3-based Super-Speed controllers on Qualcomm SoCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index dc238d9..7149261 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_SNPS_28NM) += phy-qcom-usb-hs-snsp-28nm.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 0000000..7b6a55e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +enum phy_vdd_level { LEVEL_NONE, LEVEL_MIN, LEVEL_MAX, LEVEL_NUM, }; + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct clk *clk_ref; + struct clk *clk_phy; + struct clk *clk_pipe; + struct regulator *vdda1p8; + struct regulator *vbus; + struct regulator *vdd; + unsigned int vdd_levels[LEVEL_NUM]; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int qcom_ssphy_config_vdd(struct ssphy_priv *priv, + enum phy_vdd_level level) +{ + return regulator_set_voltage(priv->vdd, + priv->vdd_levels[level], + priv->vdd_levels[LEVEL_MAX]); +} + +static int qcom_ssphy_ldo_enable(struct ssphy_priv *priv) +{ + int ret; + + ret = regulator_set_load(priv->vdda1p8, 23000); + if (ret < 0) { + dev_err(priv->dev, "Failed to set regulator1p8 load\n"); + return ret; + } + + ret = regulator_set_voltage(priv->vdda1p8, 1800000, 1800000); + if (ret) { + dev_err(priv->dev, "Failed to set regulator1p8 voltage\n"); + goto put_vdda1p8_lpm; + } + + ret = regulator_enable(priv->vdda1p8); + if (ret) { + dev_err(priv->dev, "Failed to enable regulator1p8\n"); + goto unset_vdda1p8; + } + + return ret; + + /* rollback regulator changes */ + +unset_vdda1p8: + regulator_set_voltage(priv->vdda1p8, 0, 1800000); + +put_vdda1p8_lpm: + regulator_set_load(priv->vdda1p8, 0); + + return ret; +} + +static void qcom_ssphy_ldo_disable(struct ssphy_priv *priv) +{ + regulator_disable(priv->vdda1p8); + regulator_set_voltage(priv->vdda1p8, 0, 1800000); + regulator_set_load(priv->vdda1p8, 0); +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + if (!priv->vbus) + goto config; + + ret = regulator_enable(priv->vbus); + if (ret) + return ret; +config: + ret = qcom_ssphy_config_vdd(priv, LEVEL_MIN); + if (ret) { + dev_err(priv->dev, "Failed to config vdd on\n"); + goto err; + } + + ret = qcom_ssphy_ldo_enable(priv); + if (ret) { + dev_err(priv->dev, "Failed to enable LDO\n"); + goto err1; + } + + ret = clk_prepare_enable(priv->clk_ref); + if (ret) { + dev_err(priv->dev, "Failed to enable the reference clock\n"); + goto err1; + } + + ret = clk_prepare_enable(priv->clk_phy); + if (ret) { + dev_err(priv->dev, "Failed to enable the phy clock\n"); + goto err2; + } + + ret = clk_prepare_enable(priv->clk_pipe); + if (ret) { + dev_err(priv->dev, "Failed to enable the pipe clock\n"); + goto err3; + } + + if (priv->reset_com && priv->reset_phy) { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to assert reset com\n"); + goto err4; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to assert reset phy\n"); + goto err4; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset com\n"); + goto err4; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset phy\n"); + goto err4; + } + + goto power_on; + } + + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, PHY_RESET); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); + +power_on: + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; + +err4: + clk_disable_unprepare(priv->clk_ref); +err3: + clk_disable_unprepare(priv->clk_phy); +err2: + clk_disable_unprepare(priv->clk_ref); +err1: + qcom_ssphy_config_vdd(priv, LEVEL_NONE); +err: + if (priv->vbus) + regulator_disable(priv->vbus); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + clk_disable_unprepare(priv->clk_pipe); + clk_disable_unprepare(priv->clk_phy); + clk_disable_unprepare(priv->clk_ref); + + qcom_ssphy_ldo_disable(priv); + qcom_ssphy_config_vdd(priv, LEVEL_NONE); + + if (priv->vbus) + regulator_disable(priv->vbus); + + return 0; +} + +static const struct phy_ops qcom_ssphy_ops = { + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = THIS_MODULE, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct resource *res; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk_ref = devm_clk_get(dev, "ref"); + if (IS_ERR(priv->clk_ref)) { + dev_err(dev, "Failed to get the reference clock\n"); + return PTR_ERR(priv->clk_ref); + } + + priv->clk_phy = devm_clk_get(dev, "phy"); + if (IS_ERR(priv->clk_phy)) { + dev_err(dev, "Failed to get the phy clock\n"); + return PTR_ERR(priv->clk_phy); + } + + priv->clk_pipe = devm_clk_get(dev, "pipe"); + if (IS_ERR(priv->clk_pipe)) { + dev_err(dev, "Failed to get the pipe clock\n"); + return PTR_ERR(priv->clk_pipe); + } + + priv->reset_com = devm_reset_control_get_optional(dev, "com"); + if (IS_ERR(priv->reset_com)) { + dev_err(dev, "Failed to get reset control com\n"); + return PTR_ERR(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->reset_phy)) { + dev_err(dev, "Failed to get reset control phy\n"); + return PTR_ERR(priv->reset_phy); + } + } + + priv->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(priv->vdd)) { + dev_err(dev, "Failed to get the vdd regulator\n"); + return PTR_ERR(priv->vdd); + } + + priv->vdda1p8 = devm_regulator_get(dev, "vdda1p8"); + if (IS_ERR(priv->vdda1p8)) { + dev_err(dev, "Failed to get the vdda1p8 regulator\n"); + return PTR_ERR(priv->vdda1p8); + } + + ret = of_property_read_u32_array(dev->of_node, + "qcom,vdd-voltage-level", + priv->vdd_levels, + ARRAY_SIZE(priv->vdd_levels)); + if (ret) { + dev_err(dev, "Failed to read qcom,vdd-voltage-level\n"); + return ret; + } + + priv->vbus = devm_regulator_get_optional(dev, "vbus"); + if (IS_ERR(priv->vbus)) { + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + priv->vbus = NULL; + } + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the ss phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ssphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom_usb_ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm Super-Speed USB PHY driver"); +MODULE_LICENSE("GPL v2");